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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization

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This commit is contained in:
Blaise Tine
2020-11-21 09:47:56 -08:00
parent a7da36c007
commit 1795980a52
50 changed files with 972 additions and 952 deletions
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2
hw/rtl/interfaces/VX_cache_core_rsp_if.v
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@@ -11,8 +11,10 @@ interface VX_cache_core_rsp_if #(
) ();
wire [NUM_REQUESTS-1:0] valid;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data;
wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_cache_dram_req_if.v
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@@ -10,11 +10,13 @@ interface VX_cache_dram_req_if #(
) ();
wire valid;
wire rw;
wire [(DRAM_LINE_WIDTH/8)-1:0] byteen;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire [DRAM_LINE_WIDTH-1:0] data;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_cache_dram_rsp_if.v
View File

@@ -9,8 +9,10 @@ interface VX_cache_dram_rsp_if #(
) ();
wire valid;
wire [DRAM_LINE_WIDTH-1:0] data;
wire [DRAM_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_cache_snp_req_if.v
View File

@@ -9,9 +9,11 @@ interface VX_cache_snp_req_if #(
) ();
wire valid;
wire [DRAM_ADDR_WIDTH-1:0] addr;
wire invalidate;
wire [SNP_TAG_WIDTH-1:0] tag;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_cache_snp_rsp_if.v
View File

@@ -8,7 +8,9 @@ interface VX_cache_snp_rsp_if #(
) ();
wire valid;
wire [SNP_TAG_WIDTH-1:0] tag;
wire ready;
endinterface

8
hw/rtl/interfaces/VX_cmt_to_csr_if.v
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@@ -5,14 +5,12 @@
interface VX_cmt_to_csr_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [$clog2(`NUM_THREADS+1)-1:0] commit_size;
wire has_fflags;
fflags_t fflags;
wire has_fflags;
fflags_t fflags;
endinterface

2
hw/rtl/interfaces/VX_csr_io_req_if.v
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@@ -6,9 +6,11 @@
interface VX_csr_io_req_if ();
wire valid;
wire [`CSR_ADDR_BITS-1:0] addr;
wire rw;
wire [31:0] data;
wire ready;
endinterface

2
hw/rtl/interfaces/VX_csr_io_rsp_if.v
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@@ -6,7 +6,9 @@
interface VX_csr_io_rsp_if ();
wire valid;
wire [31:0] data;
wire ready;
endinterface

5
hw/rtl/interfaces/VX_decode_if.v
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@@ -10,18 +10,15 @@ interface VX_decode_if ();
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`EX_BITS-1:0] ex_type;
wire [`OP_BITS-1:0] op_type;
wire [`MOD_BITS-1:0] op_mod;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NR_BITS-1:0] rs1;
wire [`NR_BITS-1:0] rs2;
wire [`NR_BITS-1:0] rs3;
wire [31:0] imm;
wire [31:0] imm;
wire rs1_is_PC;
wire rs2_is_imm;
wire use_rs3;

4
hw/rtl/interfaces/VX_exu_to_cmt_if.v
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@@ -5,13 +5,15 @@
interface VX_exu_to_cmt_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_fpu_to_cmt_if.v
View File

@@ -5,7 +5,8 @@
interface VX_fpu_to_cmt_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
@@ -14,6 +15,7 @@ interface VX_fpu_to_cmt_if ();
wire wb;
wire has_fflags;
fflags_t [`NUM_THREADS-1:0] fflags;
wire ready;
endinterface

14
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -9,15 +9,13 @@
interface VX_fpu_to_csr_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
wire fflags_NV;
wire fflags_DZ;
wire fflags_OF;
wire fflags_UF;
wire fflags_NX;
wire fflags_NV;
wire fflags_DZ;
wire fflags_OF;
wire fflags_UF;
wire fflags_NX;
endinterface

1
hw/rtl/interfaces/VX_gpr_rsp_if.v
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@@ -9,7 +9,6 @@ interface VX_gpr_rsp_if ();
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
`IGNORE_WARNINGS_END
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;

2
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -6,9 +6,11 @@
interface VX_ifetch_req_if ();
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire ready;
endinterface

4
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -5,11 +5,13 @@
interface VX_ifetch_rsp_if ();
wire valid;
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
wire [31:0] PC;
wire [31:0] instr;
wire ready;
endinterface

5
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -10,14 +10,11 @@ interface VX_lsu_req_if ();
wire [`NW_BITS-1:0] wid;
wire [`NUM_THREADS-1:0] tmask;
wire [31:0] PC;
wire rw;
wire [`BYTEEN_BITS-1:0] byteen;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire [31:0] offset;
wire [`NR_BITS-1:0] rd;
wire wb;

11
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -5,13 +5,12 @@
interface VX_warp_ctl_if ();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
gpu_tmc_t tmc;
gpu_wspawn_t wspawn;
gpu_barrier_t barrier;
gpu_split_t split;
gpu_tmc_t tmc;
gpu_wspawn_t wspawn;
gpu_barrier_t barrier;
gpu_split_t split;
endinterface

3
hw/rtl/interfaces/VX_writeback_if.v
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@@ -6,13 +6,12 @@
interface VX_writeback_if ();
wire valid;
wire [`NUM_THREADS-1:0] tmask;
wire [`NW_BITS-1:0] wid;
`IGNORE_WARNINGS_BEGIN
wire [31:0] PC;
`IGNORE_WARNINGS_END
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] data;

2
hw/rtl/interfaces/VX_wstall_if.v
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@@ -5,7 +5,7 @@
interface VX_wstall_if();
wire valid;
wire valid;
wire [`NW_BITS-1:0] wid;
endinterface