diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index f2a6fb23..d31e0ceb 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -74,8 +74,8 @@ static int vx_scope_start(vx_device_h hdevice) { vx_device_t *device = ((vx_device_t*)hdevice); // set start delay - uint64_t delay = ((0 << 3) | 4); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, delay)); + uint64_t delay = 0; + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, ((delay << 3) | 4))); // start execution CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); @@ -110,27 +110,29 @@ static int vx_scope_start(vx_device_h hdevice) { ofs << "$var reg 2 15 icache_req_tag $end" << std::endl; ofs << "$var reg 32 16 icache_rsp_data $end" << std::endl; ofs << "$var reg 2 17 icache_rsp_tag $end" << std::endl; - ofs << "$var reg 2 18 dcache_req_tag $end" << std::endl; - ofs << "$var reg 2 19 dcache_rsp_tag $end" << std::endl; - ofs << "$var reg 29 20 dram_req_tag $end" << std::endl; - ofs << "$var reg 29 21 dram_rsp_tag $end" << std::endl; + ofs << "$var reg 32 18 dcache_req_addr $end" << std::endl; + ofs << "$var reg 2 19 dcache_req_tag $end" << std::endl; + ofs << "$var reg 32 20 dcache_rsp_data $end" << std::endl; + ofs << "$var reg 2 21 dcache_rsp_tag $end" << std::endl; + ofs << "$var reg 29 22 dram_req_tag $end" << std::endl; + ofs << "$var reg 29 23 dram_rsp_tag $end" << std::endl; + ofs << "$var reg 2 24 icache_req_warp $end" << std::endl; + ofs << "$var reg 2 25 dcache_req_warp $end" << std::endl; - fwidth += 128; + fwidth += 198; - #define IS_PC_SID(x) (x == 14) - - const int num_signals = 22; + const int num_signals = 26; uint64_t frame_width, max_frames, data_valid; ofs << "enddefinitions $end" << std::endl; - do { - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0)); + do { CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); if (data_valid) break; - std::this_thread::sleep_for(std::chrono::milliseconds(1)); + std::this_thread::sleep_for(std::chrono::seconds(1)); } while (true); std::cout << "scope trace dump begin..." << std::endl; @@ -186,12 +188,7 @@ static int vx_scope_start(vx_device_h hdevice) { if (signal_offset == signal_width) { signa_data[signal_width] = 0; // string null termination - int sid = (num_signals - signal_id); - if (IS_PC_SID(sid)) { - ofs << 'b' << signa_data.data() << "00 " << sid << std::endl; - } else { - ofs << 'b' << signa_data.data() << ' ' << sid << std::endl; - } + ofs << 'b' << signa_data.data() << ' ' << (num_signals - signal_id) << std::endl; signal_offset = 0; ++signal_id; } @@ -228,22 +225,24 @@ static int vx_scope_start(vx_device_h hdevice) { break; case 15: case 17: - case 18: case 19: + case 21: + case 24: + case 25: print_signal(word, 2); break; case 5: case 7: print_signal(word, 4); break; - case 20: - case 21: + case 22: + case 23: print_signal(word, 29); break; case 14: - print_signal(word, 30); - break; case 16: + case 18: + case 20: print_signal(word, 32); break; } diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 5e21e815..5216e359 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -804,7 +804,14 @@ end `SCOPE_ASSIGN(scope_dram_rsp_tag, vx_dram_rsp_tag); `SCOPE_ASSIGN(scope_dram_rsp_ready, vx_dram_rsp_ready); -`STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 147, "oops!") +`STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 217, "oops!") + +wire force_changed = (scope_icache_req_valid && scope_icache_req_ready) + || (scope_icache_rsp_valid && scope_icache_rsp_ready) + || ((| scope_dcache_req_valid) && scope_dcache_req_ready) + || ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready) + || (scope_dram_req_valid && scope_dram_req_ready) + || (scope_dram_rsp_valid && scope_dram_rsp_ready); VX_scope #( .DATAW ($bits({`SCOPE_SIGNALS_LIST})), @@ -816,6 +823,7 @@ VX_scope #( .reset (SoftReset), .start (vx_reset), .stop (cmd_run_done), + .changed (force_changed), .data_in ({`SCOPE_SIGNALS_LIST}), .bus_in (csr_scope_cmd), .bus_out (csr_scope_data), @@ -833,6 +841,8 @@ Vortex_Socket #() vx_socket ( `SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH + `SCOPE_SIGNALS_FE_ATTACH + `SCOPE_SIGNALS_BE_ATTACH .clk (clk), .reset (vx_reset), diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 53e1d417..b082cc2b 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -13,7 +13,6 @@ module VX_alu_unit ( output reg[31:0] alu_result, output reg alu_stall ); - localparam div_pipeline_len = 20; localparam mul_pipeline_len = 8; diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index bc11ea3b..16adde01 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -3,6 +3,8 @@ module VX_back_end #( parameter CORE_ID = 0 ) ( + `SCOPE_SIGNALS_BE_IO + input wire clk, input wire reset, @@ -68,6 +70,8 @@ module VX_back_end #( VX_lsu_unit #( .CORE_ID(CORE_ID) ) lsu_unit ( + `SCOPE_SIGNALS_BE_ATTACH + .clk (clk), .reset (reset), .lsu_req_if (lsu_req_if), diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 85cdc483..384f7157 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -301,14 +301,18 @@ scope_icache_req_tag, \ scope_icache_rsp_data, \ scope_icache_rsp_tag, \ + scope_dcache_req_addr, \ scope_dcache_req_tag, \ + scope_dcache_rsp_data, \ scope_dcache_rsp_tag, \ scope_dram_req_tag, \ - scope_dram_rsp_tag + scope_dram_rsp_tag, \ + scope_icache_req_warp, \ + scope_dcache_req_warp `define SCOPE_SIGNALS_DECL \ wire scope_icache_req_valid; \ - wire [29:0] scope_icache_req_addr; \ + wire [31:0] scope_icache_req_addr; \ wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \ wire scope_icache_req_ready; \ wire scope_icache_rsp_valid; \ @@ -316,9 +320,11 @@ wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \ wire scope_icache_rsp_ready; \ wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \ + wire [31:0] scope_dcache_req_addr; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \ wire scope_dcache_req_ready; \ wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \ + wire [31:0] scope_dcache_rsp_data; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \ wire scope_dcache_rsp_ready; \ wire scope_dram_req_valid; \ @@ -327,12 +333,14 @@ wire scope_dram_rsp_valid; \ wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \ wire scope_dram_rsp_ready; \ - wire scope_schedule_delay; + wire scope_schedule_delay; \ + wire [1:0] scope_icache_req_warp; \ + wire [1:0] scope_dcache_req_warp; `define SCOPE_SIGNALS_ICACHE_IO \ /* verilator lint_off UNDRIVEN */ \ output wire scope_icache_req_valid, \ - output wire [29:0] scope_icache_req_addr, \ + output wire [31:0] scope_icache_req_addr, \ output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \ output wire scope_icache_req_ready, \ output wire scope_icache_rsp_valid, \ @@ -344,9 +352,11 @@ `define SCOPE_SIGNALS_DCACHE_IO \ /* verilator lint_off UNDRIVEN */ \ output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \ + output wire [31:0] scope_dcache_req_addr, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \ output wire scope_dcache_req_ready, \ output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \ + output wire [31:0] scope_dcache_rsp_data, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \ output wire scope_dcache_rsp_ready, \ /* verilator lint_on UNDRIVEN */ @@ -366,6 +376,16 @@ output wire scope_schedule_delay, \ /* verilator lint_on UNDRIVEN */ + `define SCOPE_SIGNALS_FE_IO \ + /* verilator lint_off UNDRIVEN */ \ + output wire [1:0] scope_icache_req_warp, \ + /* verilator lint_on UNDRIVEN */ + + `define SCOPE_SIGNALS_BE_IO \ + /* verilator lint_off UNDRIVEN */ \ + output wire [1:0] scope_dcache_req_warp, \ + /* verilator lint_on UNDRIVEN */ + `define SCOPE_SIGNALS_ICACHE_ATTACH \ .scope_icache_req_valid (scope_icache_req_valid), \ .scope_icache_req_addr (scope_icache_req_addr), \ @@ -378,9 +398,11 @@ `define SCOPE_SIGNALS_DCACHE_ATTACH \ .scope_dcache_req_valid (scope_dcache_req_valid), \ + .scope_dcache_req_addr (scope_dcache_req_addr), \ .scope_dcache_req_tag (scope_dcache_req_tag), \ .scope_dcache_req_ready (scope_dcache_req_ready), \ .scope_dcache_rsp_valid (scope_dcache_rsp_valid), \ + .scope_dcache_rsp_data (scope_dcache_rsp_data), \ .scope_dcache_rsp_tag (scope_dcache_rsp_tag), \ .scope_dcache_rsp_ready (scope_dcache_rsp_ready), @@ -395,17 +417,27 @@ `define SCOPE_SIGNALS_CORE_ATTACH \ .scope_schedule_delay (scope_schedule_delay), + `define SCOPE_SIGNALS_FE_ATTACH \ + .scope_icache_req_warp (scope_icache_req_warp), + + `define SCOPE_SIGNALS_BE_ATTACH \ + .scope_dcache_req_warp (scope_dcache_req_warp), + `define SCOPE_ASSIGN(d,s) assign d = s `else `define SCOPE_SIGNALS_ICACHE_IO `define SCOPE_SIGNALS_DCACHE_IO `define SCOPE_SIGNALS_DRAM_IO `define SCOPE_SIGNALS_CORE_IO + `define SCOPE_SIGNALS_FE_IO + `define SCOPE_SIGNALS_BE_IO `define SCOPE_SIGNALS_ICACHE_ATTACH `define SCOPE_SIGNALS_DCACHE_ATTACH `define SCOPE_SIGNALS_DRAM_ATTACH `define SCOPE_SIGNALS_CORE_ATTACH + `define SCOPE_SIGNALS_FE_ATTACH + `define SCOPE_SIGNALS_BE_ATTACH `define SCOPE_ASSIGN(d,s) `endif diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 723b3bbc..83eb45cc 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -3,6 +3,8 @@ module VX_front_end #( parameter CORE_ID = 0 ) ( + `SCOPE_SIGNALS_FE_IO + input wire clk, input wire reset, @@ -63,6 +65,8 @@ module VX_front_end #( VX_icache_stage #( .CORE_ID(CORE_ID) ) icache_stage ( + `SCOPE_SIGNALS_FE_ATTACH + .clk (clk), .reset (reset), .total_freeze (total_freeze), @@ -99,7 +103,7 @@ module VX_front_end #( .freeze (total_freeze), .frE_to_bckE_req_if (frE_to_bckE_req_if), .bckE_req_if (bckE_req_if) - ); + ); endmodule diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 79330f5c..07fee468 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -3,6 +3,8 @@ module VX_icache_stage #( parameter CORE_ID = 0 ) ( + `SCOPE_SIGNALS_FE_IO + input wire clk, input wire reset, input wire total_freeze, @@ -20,11 +22,6 @@ module VX_icache_stage #( wire valid_inst = (| fe_inst_meta_fi.valid); -`DEBUG_BEGIN - wire [`ICORE_TAG_WIDTH-1:0] mem_req_tag = icache_req_if.core_req_tag; - wire [`ICORE_TAG_WIDTH-1:0] mem_rsp_tag = icache_rsp_if.core_rsp_tag; -`DEBUG_END - wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; @@ -48,6 +45,8 @@ module VX_icache_stage #( .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num}) ); + `SCOPE_ASSIGN(scope_icache_req_warp, fe_inst_meta_fi.warp_num); + always @(posedge clk) begin if (reset) begin //-- diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 4a387d81..b199b32b 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -3,6 +3,9 @@ module VX_lsu_unit #( parameter CORE_ID = 0 ) ( + + `SCOPE_SIGNALS_BE_IO + input wire clk, input wire reset, @@ -49,6 +52,8 @@ module VX_lsu_unit #( .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) ); + `SCOPE_ASSIGN(scope_dcache_req_warp, use_warp_num); + wire core_req_rw = (use_mem_write != `BYTE_EN_NO); wire [`NUM_THREADS-1:0][4:0] mem_req_offset; diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 76aa6ea0..78c76af3 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -6,6 +6,8 @@ module VX_pipeline #( `SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_FE_IO + `SCOPE_SIGNALS_BE_IO // Clock input wire clk, @@ -56,7 +58,7 @@ module VX_pipeline #( wire schedule_delay; `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid); - `SCOPE_ASSIGN(scope_icache_req_addr, icache_req_addr); + `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_addr, 2'b0}); `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag); `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready); `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid); @@ -65,9 +67,11 @@ module VX_pipeline #( `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready); `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid); + `SCOPE_ASSIGN(scope_dcache_req_addr, {dcache_req_addr[0], 2'b0}); `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_tag); `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_ready); `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_valid); + `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_data[0]); `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_tag); `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_ready); @@ -117,6 +121,7 @@ module VX_pipeline #( VX_front_end #( .CORE_ID(CORE_ID) ) front_end ( + `SCOPE_SIGNALS_FE_ATTACH .clk (clk), .reset (reset), .warp_ctl_if (warp_ctl_if), @@ -144,6 +149,7 @@ module VX_pipeline #( VX_back_end #( .CORE_ID(CORE_ID) ) back_end ( + `SCOPE_SIGNALS_BE_ATTACH .clk (clk), .reset (reset), .schedule_delay (schedule_delay), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 321d4f1a..2eddfc02 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -6,6 +6,8 @@ module Vortex #( `SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_FE_IO + `SCOPE_SIGNALS_BE_IO // Clock input wire clk, @@ -170,6 +172,8 @@ module Vortex #( `SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH + `SCOPE_SIGNALS_FE_ATTACH + `SCOPE_SIGNALS_BE_ATTACH .clk(clk), .reset(reset), diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 5b5be57b..6fe35980 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -6,6 +6,8 @@ module Vortex_Cluster #( `SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_FE_IO + `SCOPE_SIGNALS_BE_IO // Clock input wire clk, @@ -113,6 +115,8 @@ module Vortex_Cluster #( `SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH + `SCOPE_SIGNALS_FE_ATTACH + `SCOPE_SIGNALS_BE_ATTACH .clk (clk), .reset (reset), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 0364a26b..fe9e6b08 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -4,6 +4,8 @@ module Vortex_Socket ( `SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_CORE_IO + `SCOPE_SIGNALS_FE_IO + `SCOPE_SIGNALS_BE_IO // Clock input wire clk, @@ -62,6 +64,8 @@ module Vortex_Socket ( `SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH + `SCOPE_SIGNALS_FE_ATTACH + `SCOPE_SIGNALS_BE_ATTACH .clk (clk), .reset (reset), @@ -151,6 +155,8 @@ module Vortex_Socket ( `SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH + `SCOPE_SIGNALS_FE_ATTACH + `SCOPE_SIGNALS_BE_ATTACH .clk (clk), .reset (reset), diff --git a/hw/rtl/libs/VX_scope.v b/hw/rtl/libs/VX_scope.v index 39308d89..534dc89c 100644 --- a/hw/rtl/libs/VX_scope.v +++ b/hw/rtl/libs/VX_scope.v @@ -10,6 +10,7 @@ module VX_scope #( input wire reset, input wire start, input wire stop, + input wire changed, input wire [DATAW-1:0] data_in, input wire [BUSW-1:0] bus_in, output reg [BUSW-1:0] bus_out, @@ -102,8 +103,7 @@ module VX_scope #( if (start_wait) begin delay_cntr <= delay_cntr - 1; - if (1 == delay_cntr) begin - $display("%t: scope-state: recording", $time); + if (1 == delay_cntr) begin start_wait <= 0; recording <= 1; delta <= 0; @@ -112,7 +112,8 @@ module VX_scope #( if (recording) begin if (DELTA_ENABLE) begin - if (0 == waddr + if (changed + || (0 == waddr) || (trigger_id != prev_id)) begin data_store[waddr] <= data_in; delta_store[waddr] <= delta; @@ -129,7 +130,6 @@ module VX_scope #( if (stop || (waddr == waddr_end)) begin - $display("%t: scope-state: data_valid, waddr=%0d", $time, waddr); waddr <= waddr; // keep last written address recording <= 0; data_valid <= 1;