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revert saxpy change and fix stage_1_cycles not working

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wgulian3
2020-03-20 04:49:02 -04:00
parent 05b7ffff12
commit 1c82f9a11d
2 changed files with 3 additions and 3 deletions
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2
benchmarks/opencl/saxpy/main.cc
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@@ -153,7 +153,7 @@ int main(int argc, char **argv) {
} }
cl_event kernel_completion; cl_event kernel_completion;
size_t global_work_size[1] = {NUM_DATA/2,NUM_DATA/2}; size_t global_work_size[1] = {NUM_DATA};
printf("attempting to enqueue kernel\n"); printf("attempting to enqueue kernel\n");
fflush(stdout); fflush(stdout);
CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, global_work_size, CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 1, NULL, global_work_size,

4
rtl/VX_define.v
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@@ -141,7 +141,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...} // Number of Word requests per cycle {1, 2, 4, 8, ...}
`define DNUMBER_REQUESTS `NT `define DNUMBER_REQUESTS `NT
// Number of cycles to complete stage 1 (read from memory) // Number of cycles to complete stage 1 (read from memory)
`define DSTAGE_1_CYCLES 4 `define DSTAGE_1_CYCLES 2
// Function ID // Function ID
`define DFUNC_ID 0 `define DFUNC_ID 0
@@ -192,7 +192,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...} // Number of Word requests per cycle {1, 2, 4, 8, ...}
`define INUMBER_REQUESTS 1 `define INUMBER_REQUESTS 1
// Number of cycles to complete stage 1 (read from memory) // Number of cycles to complete stage 1 (read from memory)
`define ISTAGE_1_CYCLES 4 `define ISTAGE_1_CYCLES 2
// Function ID // Function ID
`define IFUNC_ID 1 `define IFUNC_ID 1