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minor update

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This commit is contained in:
Blaise Tine
2021-08-26 14:49:57 -07:00
parent 26e94dde44
commit 28eb3cfdb2
1 changed files with 37 additions and 51 deletions
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66
hw/rtl/libs/VX_priority_encoder.v
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@@ -12,18 +12,27 @@ module VX_priority_encoder #(
output wire [LN-1:0] index, output wire [LN-1:0] index,
output wire valid_out output wire valid_out
); );
wire [N-1:0] reversed;
if (REVERSE) begin
for (genvar i = 0; i < N; ++i) begin
assign reversed[N-i-1] = data_in[i];
end
end else begin
assign reversed = data_in;
end
if (N == 1) begin if (N == 1) begin
assign onehot = data_in; assign onehot = reversed;
assign index = 0; assign index = 0;
assign valid_out = data_in; assign valid_out = reversed;
end else if (N == 2) begin end else if (N == 2) begin
assign onehot = {~data_in[REVERSE], data_in[REVERSE]}; assign onehot = {~reversed[0], reversed[0]};
assign index = ~data_in[REVERSE]; assign index = ~reversed[0];
assign valid_out = (| data_in); assign valid_out = (| reversed);
end else if (MODEL == 1) begin end else if (MODEL == 1) begin
@@ -31,24 +40,17 @@ module VX_priority_encoder #(
VX_scan #( VX_scan #(
.N (N), .N (N),
.OP (2), .OP (2)
.REVERSE (REVERSE)
) scan ( ) scan (
.data_in (data_in), .data_in (reversed),
.data_out (scan_lo) .data_out (scan_lo)
); );
if (REVERSE) begin
assign onehot = scan_lo & {1'b1, (~scan_lo[N-1:1])};
assign valid_out = scan_lo[0];
end else begin
assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
assign valid_out = scan_lo[N-1]; assign valid_out = scan_lo[N-1];
end
VX_onehot_encoder #( VX_onehot_encoder #(
.N (N), .N (N)
.REVERSE (REVERSE)
) onehot_encoder ( ) onehot_encoder (
.data_in (onehot), .data_in (onehot),
.data_out (index), .data_out (index),
@@ -60,70 +62,54 @@ module VX_priority_encoder #(
`IGNORE_WARNINGS_BEGIN `IGNORE_WARNINGS_BEGIN
wire [N-1:0] higher_pri_regs; wire [N-1:0] higher_pri_regs;
`IGNORE_WARNINGS_END `IGNORE_WARNINGS_END
assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | data_in[N-2:0]; assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | reversed[N-2:0];
assign higher_pri_regs[0] = 1'b0; assign higher_pri_regs[0] = 1'b0;
assign onehot[N-1:0] = data_in[N-1:0] & ~higher_pri_regs[N-1:0]; assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
VX_onehot_encoder #( VX_onehot_encoder #(
.N (N), .N (N)
.REVERSE (REVERSE)
) onehot_encoder ( ) onehot_encoder (
.data_in (onehot), .data_in (onehot),
.data_out (index), .data_out (index),
`UNUSED_PIN (valid_out) `UNUSED_PIN (valid_out)
); );
assign valid_out = (| data_in); assign valid_out = (| reversed);
end else if (MODEL == 3) begin end else if (MODEL == 3) begin
assign onehot = data_in & ~(data_in-1); assign onehot = reversed & ~(reversed-1);
VX_onehot_encoder #( VX_onehot_encoder #(
.N (N), .N (N)
.REVERSE (REVERSE)
) onehot_encoder ( ) onehot_encoder (
.data_in (onehot), .data_in (onehot),
.data_out (index), .data_out (index),
`UNUSED_PIN (valid_out) `UNUSED_PIN (valid_out)
); );
assign valid_out = (| data_in); assign valid_out = (| reversed);
end else begin end else begin
reg [LN-1:0] index_r; reg [LN-1:0] index_r;
reg [N-1:0] onehot_r; reg [N-1:0] onehot_r;
if (REVERSE) begin
always @(*) begin
index_r = 'x;
onehot_r = 'x;
for (integer i = 0; i < N; ++i) begin
if (data_in[i]) begin
index_r = LN'(i);
onehot_r = 0;
onehot_r[i] = 1'b1;
end
end
end
end else begin
always @(*) begin always @(*) begin
index_r = 'x; index_r = 'x;
onehot_r = 'x; onehot_r = 'x;
for (integer i = N-1; i >= 0; --i) begin for (integer i = N-1; i >= 0; --i) begin
if (data_in[i]) begin if (reversed[i]) begin
index_r = LN'(i); index_r = LN'(i);
onehot_r = 0; onehot_r = 0;
onehot_r[i] = 1'b1; onehot_r[i] = 1'b1;
end end
end end
end end
end
assign index = index_r; assign index = index_r;
assign onehot = onehot_r; assign onehot = onehot_r;
assign valid_out = (| data_in); assign valid_out = (| reversed);
end end