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rtl refactoring

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This commit is contained in:
Blaise Tine
2020-05-05 13:31:50 -04:00
parent b7e892ee16
commit 2ab90e9436
8 changed files with 186 additions and 207 deletions
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116
hw/rtl/VX_alu_unit.v
View File

@@ -76,11 +76,11 @@ module VX_alu_unit (
.result(mul_result) .result(mul_result)
); );
// MUL, MULH (signed*signed), MULHSU (signed*unsigned), MULHU (unsigned*unsigned) // ALU_MUL, ALU_MULH (signed*signed), ALU_MULHSU (signed*unsigned), ALU_MULHU (unsigned*unsigned)
wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1}; wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2}; wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};
assign mul_data_a = (alu_op == `MULHU) ? {32'b0, ALU_in1} : alu_in1_signed; assign mul_data_a = (alu_op == `ALU_MULHU) ? {32'b0, ALU_in1} : alu_in1_signed;
assign mul_data_b = (alu_op == `MULHU || alu_op == `MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed; assign mul_data_b = (alu_op == `ALU_MULHU || alu_op == `ALU_MULHSU) ? {32'b0, ALU_in2} : alu_in2_signed;
reg [15:0] curr_inst_delay; reg [15:0] curr_inst_delay;
reg [15:0] inst_delay; reg [15:0] inst_delay;
@@ -91,15 +91,15 @@ module VX_alu_unit (
always @(*) begin always @(*) begin
case (alu_op) case (alu_op)
`DIV, `ALU_DIV,
`DIVU, `ALU_DIVU,
`REM, `ALU_REM,
`REMU: curr_inst_delay = div_pipeline_len; `ALU_REMU: curr_inst_delay = div_pipeline_len;
`MUL, `ALU_MUL,
`MULH, `ALU_MULH,
`MULHSU, `ALU_MULHSU,
`MULHU: curr_inst_delay = mul_pipeline_len; `ALU_MULHU: curr_inst_delay = mul_pipeline_len;
default: curr_inst_delay = 0; default: curr_inst_delay = 0;
endcase // alu_op endcase // alu_op
end end
@@ -137,29 +137,29 @@ module VX_alu_unit (
always @(*) begin always @(*) begin
case (alu_op) case (alu_op)
`ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2); `ALU_ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2); `ALU_SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: alu_result = ALU_in1 << ALU_in2[4:0]; `ALU_SLLA: alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; `ALU_SLT: alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; `ALU_SLTU: alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: alu_result = ALU_in1 ^ ALU_in2; `ALU_XOR: alu_result = ALU_in1 ^ ALU_in2;
`SRL: alu_result = ALU_in1 >> ALU_in2[4:0]; `ALU_SRL: alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; `ALU_SRA: alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: alu_result = ALU_in1 | ALU_in2; `ALU_OR: alu_result = ALU_in1 | ALU_in2;
`AND: alu_result = ALU_in2 & ALU_in1; `ALU_AND: alu_result = ALU_in2 & ALU_in1;
`SUBU: alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; `ALU_SUBU: alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: alu_result = upper_immed; `ALU_LUI: alu_result = upper_immed;
`AUIPC_ALU: alu_result = $signed(curr_PC) + $signed(upper_immed); `ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed);
// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? // TODO: profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
`MUL: alu_result = mul_result[31:0]; `ALU_MUL: alu_result = mul_result[31:0];
`MULH: alu_result = mul_result[63:32]; `ALU_MULH: alu_result = mul_result[63:32];
`MULHSU: alu_result = mul_result[63:32]; `ALU_MULHSU: alu_result = mul_result[63:32];
`MULHU: alu_result = mul_result[63:32]; `ALU_MULHU: alu_result = mul_result[63:32];
`DIV: alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; `ALU_DIV: alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
`DIVU: alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; `ALU_DIVU: alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
`REM: alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; `ALU_REM: alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
`REMU: alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; `ALU_REMU: alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
default: alu_result = 32'h0; default: alu_result = 32'h0;
endcase // alu_op endcase // alu_op
end end
@@ -178,29 +178,29 @@ module VX_alu_unit (
always @(*) begin always @(*) begin
case (alu_op) case (alu_op)
`ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2); `ALU_ADD: alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2); `ALU_SUB: alu_result = $signed(ALU_in1) - $signed(ALU_in2);
`SLLA: alu_result = ALU_in1 << ALU_in2[4:0]; `ALU_SLLA: alu_result = ALU_in1 << ALU_in2[4:0];
`SLT: alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0; `ALU_SLT: alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
`SLTU: alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0; `ALU_SLTU: alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
`XOR: alu_result = ALU_in1 ^ ALU_in2; `ALU_XOR: alu_result = ALU_in1 ^ ALU_in2;
`SRL: alu_result = ALU_in1 >> ALU_in2[4:0]; `ALU_SRL: alu_result = ALU_in1 >> ALU_in2[4:0];
`SRA: alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; `ALU_SRA: alu_result = $signed(ALU_in1) >>> ALU_in2[4:0];
`OR: alu_result = ALU_in1 | ALU_in2; `ALU_OR: alu_result = ALU_in1 | ALU_in2;
`AND: alu_result = ALU_in2 & ALU_in1; `ALU_AND: alu_result = ALU_in2 & ALU_in1;
`SUBU: alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff; `ALU_SUBU: alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
`LUI_ALU: alu_result = upper_immed_s; `ALU_LUI: alu_result = upper_immed_s;
`AUIPC_ALU: alu_result = $signed(curr_PC) + $signed(upper_immed_s); `ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed_s);
// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible? // TODO: profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
`MUL: alu_result = mul_result[31:0]; `ALU_MUL: alu_result = mul_result[31:0];
`MULH: alu_result = mul_result[63:32]; `ALU_MULH: alu_result = mul_result[63:32];
`MULHSU: alu_result = mul_result[63:32]; `ALU_MULHSU: alu_result = mul_result[63:32];
`MULHU: alu_result = mul_result[63:32]; `ALU_MULHU: alu_result = mul_result[63:32];
`DIV: alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result; `ALU_DIV: alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
`DIVU: alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result; `ALU_DIVU: alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
`REM: alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result; `ALU_REM: alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
`REMU: alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result; `ALU_REMU: alu_result = (ALU_in2 == 0) ? ALU_in1 : unsigned_rem_result;
default: alu_result = 32'h0; default: alu_result = 32'h0;
endcase // alu_op endcase // alu_op
end end

6
hw/rtl/VX_csr_pipe.v
View File

@@ -44,9 +44,9 @@ module VX_csr_pipe #(
always @(*) begin always @(*) begin
case (csr_req_if.alu_op) case (csr_req_if.alu_op)
`CSR_ALU_RW: csr_updated_data = csr_req_if.csr_mask; `ALU_CSR_RW: csr_updated_data = csr_req_if.csr_mask;
`CSR_ALU_RS: csr_updated_data = csr_read_data | csr_req_if.csr_mask; `ALU_CSR_RS: csr_updated_data = csr_read_data | csr_req_if.csr_mask;
`CSR_ALU_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_req_if.csr_mask); `ALU_CSR_RC: csr_updated_data = csr_read_data & (32'hFFFFFFFF - csr_req_if.csr_mask);
default: csr_updated_data = 32'hdeadbeef; default: csr_updated_data = 32'hdeadbeef;
endcase endcase
end end

122
hw/rtl/VX_decode.v
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@@ -95,19 +95,19 @@ module VX_decode(
assign frE_to_bckE_req_if.PC_next = in_curr_PC + 32'h4; assign frE_to_bckE_req_if.PC_next = in_curr_PC + 32'h4;
// Write Back sigal // Write Back sigal
assign is_rtype = (curr_opcode == `R_INST); assign is_rtype = (curr_opcode == `INST_R);
assign is_linst = (curr_opcode == `L_INST); assign is_linst = (curr_opcode == `INST_L);
assign is_itype = (curr_opcode == `ALU_INST) || is_linst; assign is_itype = (curr_opcode == `INST_ALU) || is_linst;
assign is_stype = (curr_opcode == `S_INST); assign is_stype = (curr_opcode == `INST_S);
assign is_btype = (curr_opcode == `B_INST); assign is_btype = (curr_opcode == `INST_B);
assign is_jal = (curr_opcode == `JAL_INST); assign is_jal = (curr_opcode == `INST_JAL);
assign is_jalr = (curr_opcode == `JALR_INST); assign is_jalr = (curr_opcode == `INST_JALR);
assign is_lui = (curr_opcode == `LUI_INST); assign is_lui = (curr_opcode == `INST_LUI);
assign is_auipc = (curr_opcode == `AUIPC_INST); assign is_auipc = (curr_opcode == `INST_AUIPC);
assign is_csr = (curr_opcode == `SYS_INST) && (func3 != 0); assign is_csr = (curr_opcode == `INST_SYS) && (func3 != 0);
assign is_csr_immed = (is_csr) && (func3[2] == 1); assign is_csr_immed = (is_csr) && (func3[2] == 1);
assign is_gpgpu = (curr_opcode == `GPGPU_INST); assign is_gpgpu = (curr_opcode == `INST_GPGPU);
assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE assign is_tmc = is_gpgpu && (func3 == 0); // Goes to BE
assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE assign is_wspawn = is_gpgpu && (func3 == 1); // Goes to BE
@@ -129,7 +129,7 @@ module VX_decode(
assign frE_to_bckE_req_if.wb = (is_jal || is_jalr || is_etype) ? `WB_JAL : assign frE_to_bckE_req_if.wb = (is_jal || is_jalr || is_etype) ? `WB_JAL :
is_linst ? `WB_MEM : is_linst ? `WB_MEM :
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU : (is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
`NO_WB; `WB_NO;
assign frE_to_bckE_req_if.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG; assign frE_to_bckE_req_if.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
@@ -140,8 +140,8 @@ module VX_decode(
// UPPER IMMEDIATE // UPPER IMMEDIATE
always @(*) begin always @(*) begin
case (curr_opcode) case (curr_opcode)
`LUI_INST: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3}; `INST_LUI: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3};
`AUIPC_INST: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3}; `INST_AUIPC: temp_upper_immed = {func7, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.rs1, func3};
default: temp_upper_immed = 20'h0; default: temp_upper_immed = 20'h0;
endcase // curr_opcode endcase // curr_opcode
end end
@@ -168,17 +168,17 @@ module VX_decode(
// JAL // JAL
always @(*) begin always @(*) begin
case (curr_opcode) case (curr_opcode)
`JAL_INST: `INST_JAL:
begin begin
temp_jal = 1'b1 && (| in_valid); temp_jal = 1'b1 && (| in_valid);
temp_jal_offset = jal_1_offset; temp_jal_offset = jal_1_offset;
end end
`JALR_INST: `INST_JALR:
begin begin
temp_jal = 1'b1 && (| in_valid); temp_jal = 1'b1 && (| in_valid);
temp_jal_offset = jal_2_offset; temp_jal_offset = jal_2_offset;
end end
`SYS_INST: `INST_SYS:
begin begin
// $display("SYS EBREAK %h", (jal_sys_jal && (| in_valid))); // $display("SYS EBREAK %h", (jal_sys_jal && (| in_valid)));
temp_jal = jal_sys_jal && (| in_valid); temp_jal = jal_sys_jal && (| in_valid);
@@ -197,7 +197,7 @@ module VX_decode(
assign frE_to_bckE_req_if.jal_offset = temp_jal_offset; assign frE_to_bckE_req_if.jal_offset = temp_jal_offset;
// ecall/ebreak // ecall/ebreak
assign is_etype = (curr_opcode == `SYS_INST) && jal_sys_jal; assign is_etype = (curr_opcode == `INST_SYS) && jal_sys_jal;
assign frE_to_bckE_req_if.is_etype = is_etype; assign frE_to_bckE_req_if.is_etype = is_etype;
// CSR // CSR
@@ -214,10 +214,10 @@ module VX_decode(
always @(*) begin always @(*) begin
case (curr_opcode) case (curr_opcode)
`ALU_INST: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp}; `INST_ALU: temp_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
`S_INST: temp_itype_immed = {{20{func7[6]}}, func7, frE_to_bckE_req_if.rd}; `INST_S: temp_itype_immed = {{20{func7[6]}}, func7, frE_to_bckE_req_if.rd};
`L_INST: temp_itype_immed = {{20{u_12[11]}}, u_12}; `INST_L: temp_itype_immed = {{20{u_12[11]}}, u_12};
`B_INST: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]}; `INST_B: temp_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
default: temp_itype_immed = 32'hdeadbeef; default: temp_itype_immed = 32'hdeadbeef;
endcase endcase
end end
@@ -226,29 +226,29 @@ module VX_decode(
always @(*) begin always @(*) begin
case (curr_opcode) case (curr_opcode)
`B_INST: begin `INST_B: begin
// $display("BRANCH IN DECODE"); // $display("BRANCH IN DECODE");
temp_branch_stall = 1'b1 && (| in_valid); temp_branch_stall = 1'b1 && (| in_valid);
case (func3) case (func3)
3'h0: temp_branch_type = `BEQ; 3'h0: temp_branch_type = `BR_EQ;
3'h1: temp_branch_type = `BNE; 3'h1: temp_branch_type = `BR_NE;
3'h4: temp_branch_type = `BLT; 3'h4: temp_branch_type = `BR_LT;
3'h5: temp_branch_type = `BGT; 3'h5: temp_branch_type = `BR_GT;
3'h6: temp_branch_type = `BLTU; 3'h6: temp_branch_type = `BR_LTU;
3'h7: temp_branch_type = `BGTU; 3'h7: temp_branch_type = `BR_GTU;
default: temp_branch_type = `NO_BRANCH; default: temp_branch_type = `BR_NO;
endcase endcase
end end
`JAL_INST: begin `INST_JAL: begin
temp_branch_type = `NO_BRANCH; temp_branch_type = `BR_NO;
temp_branch_stall = 1'b1 && (| in_valid); temp_branch_stall = 1'b1 && (| in_valid);
end end
`JALR_INST: begin `INST_JALR: begin
temp_branch_type = `NO_BRANCH; temp_branch_type = `BR_NO;
temp_branch_stall = 1'b1 && (| in_valid); temp_branch_stall = 1'b1 && (| in_valid);
end end
default: begin default: begin
temp_branch_type = `NO_BRANCH; temp_branch_type = `BR_NO;
temp_branch_stall = 1'b0 && (| in_valid); temp_branch_stall = 1'b0 && (| in_valid);
end end
endcase endcase
@@ -262,30 +262,30 @@ module VX_decode(
always @(*) begin always @(*) begin
// ALU OP // ALU OP
case (func3) case (func3)
3'h0: alu_op = (curr_opcode == `ALU_INST) ? `ADD : (func7 == 7'h0 ? `ADD : `SUB); 3'h0: alu_op = (curr_opcode == `INST_ALU) ? `ALU_ADD : (func7 == 7'h0 ? `ALU_ADD : `ALU_SUB);
3'h1: alu_op = `SLLA; 3'h1: alu_op = `ALU_SLLA;
3'h2: alu_op = `SLT; 3'h2: alu_op = `ALU_SLT;
3'h3: alu_op = `SLTU; 3'h3: alu_op = `ALU_SLTU;
3'h4: alu_op = `XOR; 3'h4: alu_op = `ALU_XOR;
3'h5: alu_op = (func7 == 7'h0) ? `SRL : `SRA; 3'h5: alu_op = (func7 == 7'h0) ? `ALU_SRL : `ALU_SRA;
3'h6: alu_op = `OR; 3'h6: alu_op = `ALU_OR;
3'h7: alu_op = `AND; 3'h7: alu_op = `ALU_AND;
default: alu_op = `NO_ALU; default: alu_op = `ALU_NO;
endcase endcase
end end
always @(*) begin always @(*) begin
// ALU OP // ALU OP
case (func3) case (func3)
3'h0: mul_alu = `MUL; 3'h0: mul_alu = `ALU_MUL;
3'h1: mul_alu = `MULH; 3'h1: mul_alu = `ALU_MULH;
3'h2: mul_alu = `MULHSU; 3'h2: mul_alu = `ALU_MULHSU;
3'h3: mul_alu = `MULHU; 3'h3: mul_alu = `ALU_MULHU;
3'h4: mul_alu = `DIV; 3'h4: mul_alu = `ALU_DIV;
3'h5: mul_alu = `DIVU; 3'h5: mul_alu = `ALU_DIVU;
3'h6: mul_alu = `REM; 3'h6: mul_alu = `ALU_REM;
3'h7: mul_alu = `REMU; 3'h7: mul_alu = `ALU_REMU;
default: mul_alu = `NO_ALU; default: mul_alu = `ALU_NO;
endcase endcase
end end
@@ -293,20 +293,20 @@ module VX_decode(
always @(*) begin always @(*) begin
case (csr_type) case (csr_type)
2'h1: csr_alu = `CSR_ALU_RW; 2'h1: csr_alu = `ALU_CSR_RW;
2'h2: csr_alu = `CSR_ALU_RS; 2'h2: csr_alu = `ALU_CSR_RS;
2'h3: csr_alu = `CSR_ALU_RC; 2'h3: csr_alu = `ALU_CSR_RC;
default: csr_alu = `NO_ALU; default: csr_alu = `ALU_NO;
endcase endcase
end end
wire[4:0] temp_final_alu; wire[4:0] temp_final_alu;
assign temp_final_alu = is_btype ? ((frE_to_bckE_req_if.branch_type < `BLTU) ? `SUB : `SUBU) : assign temp_final_alu = is_btype ? ((frE_to_bckE_req_if.branch_type < `BR_LTU) ? `ALU_SUB : `ALU_SUBU) :
is_lui ? `LUI_ALU : is_lui ? `ALU_LUI :
is_auipc ? `AUIPC_ALU : is_auipc ? `ALU_AUIPC :
is_csr ? csr_alu : is_csr ? csr_alu :
(is_stype || is_linst) ? `ADD : (is_stype || is_linst) ? `ALU_ADD :
alu_op; alu_op;
assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu; assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;

119
hw/rtl/VX_define.vh
View File

@@ -52,80 +52,59 @@
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
`define R_INST 7'd51 `define INST_R 7'd051
`define L_INST 7'd3 `define INST_L 7'd003
`define ALU_INST 7'd19 `define INST_ALU 7'd019
`define S_INST 7'd35 `define INST_S 7'd035
`define B_INST 7'd99 `define INST_B 7'd099
`define LUI_INST 7'd55 `define INST_LUI 7'd055
`define AUIPC_INST 7'd23 `define INST_AUIPC 7'd023
`define JAL_INST 7'd111 `define INST_JAL 7'd111
`define JALR_INST 7'd103 `define INST_JALR 7'd103
`define SYS_INST 7'd115 `define INST_SYS 7'd115
`define GPGPU_INST 7'h6b `define INST_GPGPU 7'h06b
/////////////////////////////////////////////////////////////////////////////// `define RS2_IMMED 1
`define RS2_REG 0
`define WB_ALU 2'h1 `define BR_NO 3'h0
`define WB_MEM 2'h2 `define BR_EQ 3'h1
`define WB_JAL 2'h3 `define BR_NE 3'h2
`define NO_WB 2'h0 `define BR_LT 3'h3
`define BR_GT 3'h4
`define BR_LTU 3'h5
`define BR_GTU 3'h6
`define RS2_IMMED 1 `define ALU_NO 5'd15
`define RS2_REG 0 `define ALU_ADD 5'd00
`define ALU_SUB 5'd01
`define ALU_SLLA 5'd02
`define ALU_SLT 5'd03
`define ALU_SLTU 5'd04
`define ALU_XOR 5'd05
`define ALU_SRL 5'd06
`define ALU_SRA 5'd07
`define ALU_OR 5'd08
`define ALU_AND 5'd09
`define ALU_SUBU 5'd10
`define ALU_LUI 5'd11
`define ALU_AUIPC 5'd12
`define ALU_CSR_RW 5'd13
`define ALU_CSR_RS 5'd14
`define ALU_CSR_RC 5'd15
`define ALU_MUL 5'd16
`define ALU_MULH 5'd17
`define ALU_MULHSU 5'd18
`define ALU_MULHU 5'd19
`define ALU_DIV 5'd20
`define ALU_DIVU 5'd21
`define ALU_REM 5'd22
`define ALU_REMU 5'd23
`define NO_BRANCH 3'h0 `define WB_NO 2'h0
`define BEQ 3'h1 `define WB_ALU 2'h1
`define BNE 3'h2 `define WB_MEM 2'h2
`define BLT 3'h3 `define WB_JAL 2'h3
`define BGT 3'h4
`define BLTU 3'h5
`define BGTU 3'h6
`define NO_ALU 5'd15
`define ADD 5'd0
`define SUB 5'd1
`define SLLA 5'd2
`define SLT 5'd3
`define SLTU 5'd4
`define XOR 5'd5
`define SRL 5'd6
`define SRA 5'd7
`define OR 5'd8
`define AND 5'd9
`define SUBU 5'd10
`define LUI_ALU 5'd11
`define AUIPC_ALU 5'd12
`define CSR_ALU_RW 5'd13
`define CSR_ALU_RS 5'd14
`define CSR_ALU_RC 5'd15
`define MUL 5'd16
`define MULH 5'd17
`define MULHSU 5'd18
`define MULHU 5'd19
`define DIV 5'd20
`define DIVU 5'd21
`define REM 5'd22
`define REMU 5'd23
// WRITEBACK
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
`define NO_WB 2'h0
// JAL
`define JUMP 1'h1
`define NO_JUMP 1'h0
// STALLS
`define STALL 1'h1
`define NO_STALL 1'h0
`define TAKEN 1'h1
`define NOT_TAKEN 1'h0
`define ZERO_REG 5'h0
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////

24
hw/rtl/VX_exec_unit.v
View File

@@ -88,14 +88,14 @@ module VX_exec_unit (
always @(*) always @(*)
begin begin
case (exec_unit_req_if.branch_type) case (exec_unit_req_if.branch_type)
`BEQ: temp_branch_dir = (branch_use_alu_result == 0) ? `TAKEN : `NOT_TAKEN; `BR_EQ: temp_branch_dir = (branch_use_alu_result == 0);
`BNE: temp_branch_dir = (branch_use_alu_result == 0) ? `NOT_TAKEN : `TAKEN; `BR_NE: temp_branch_dir = (branch_use_alu_result != 0);
`BLT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; `BR_LT: temp_branch_dir = (branch_use_alu_result[31] != 0);
`BGT: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; `BR_GT: temp_branch_dir = (branch_use_alu_result[31] == 0);
`BLTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; `BR_LTU: temp_branch_dir = (branch_use_alu_result[31] != 0);
`BGTU: temp_branch_dir = (branch_use_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; `BR_GTU: temp_branch_dir = (branch_use_alu_result[31] == 0);
`NO_BRANCH: temp_branch_dir = `NOT_TAKEN; `BR_NO: temp_branch_dir = 0;
default: temp_branch_dir = `NOT_TAKEN; default: temp_branch_dir = 0;
endcase // in_branch_type endcase // in_branch_type
end end
@@ -128,7 +128,7 @@ module VX_exec_unit (
assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num; assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num;
// Branch rsp // Branch rsp
assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `NO_BRANCH) && (| exec_unit_req_if.valid); assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid);
assign branch_rsp_temp_if.branch_dir = temp_branch_dir; assign branch_rsp_temp_if.branch_dir = temp_branch_dir;
assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num; assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num;
assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset
@@ -168,9 +168,9 @@ module VX_exec_unit (
// always @(*) begin // always @(*) begin
// case (in_alu_op) // case (in_alu_op)
// `CSR_ALU_RW: out_csr_result = in_csr_mask; // `ALU_CSR_RW: out_csr_result = in_csr_mask;
// `CSR_ALU_RS: out_csr_result = in_csr_data | in_csr_mask; // `ALU_CSR_RS: out_csr_result = in_csr_data | in_csr_mask;
// `CSR_ALU_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask); // `ALU_CSR_RC: out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
// default: out_csr_result = 32'hdeadbeef; // default: out_csr_result = 32'hdeadbeef;
// endcase // endcase

2
hw/rtl/pipe_regs/VX_d_e_reg.v
View File

@@ -10,7 +10,7 @@ module VX_d_e_reg (
); );
wire stall = freeze; wire stall = freeze;
wire flush = (branch_stall == `STALL); wire flush = (branch_stall != 0);
VX_generic_register #( VX_generic_register #(
.N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS)

2
hw/simulate/simulator.h
View File

@@ -15,7 +15,7 @@
#include <vector> #include <vector>
//#define ENABLE_DRAM_STALLS //#define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 200 #define DRAM_LATENCY 100
#define DRAM_RQ_SIZE 16 #define DRAM_RQ_SIZE 16
#define DRAM_STALLS_MODULO 16 #define DRAM_STALLS_MODULO 16
#define PIPELINE_FLUSH_LATENCY 300 #define PIPELINE_FLUSH_LATENCY 300

2
hw/simulate/testbench.cpp
View File

@@ -10,7 +10,7 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
//#define ALL_TESTS #define ALL_TESTS
#ifdef ALL_TESTS #ifdef ALL_TESTS
bool passed = true; bool passed = true;