From 2c1f61196a21ed29066a7c24f514138a7619f434 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 11 Feb 2019 00:41:07 -0500 Subject: [PATCH] Passes all tests - SRAI --- src/enc.cpp | 22 +- src/harptool.cpp | 4 +- src/include/debug.h | 2 +- src/include/instruction.h | 2 +- src/include/mem.h | 24 ++- src/include/types.h | 6 +- src/instruction.cpp | 60 +++--- src/mem.cpp | 41 +++- src/results.txt | 419 +++++++++++++++++++++++++++++++++++++- src/test.sh | 148 +++++++------- 10 files changed, 589 insertions(+), 139 deletions(-) diff --git a/src/enc.cpp b/src/enc.cpp index 92d8b28d..52eef15b 100644 --- a/src/enc.cpp +++ b/src/enc.cpp @@ -296,7 +296,9 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx) { bool usedImm(false); Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5, - bit_12, bits_19_12, bits_10_1, bit_20, unordered; + bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3; + + // std::cout << "op: " << std::hex << op << " what " << instTable[op].iType << "\n"; switch(instTable[op].iType) { case InstType::N_TYPE: @@ -311,12 +313,23 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx) { case InstType::I_TYPE: inst.setDestReg((code>>shift_rd) & reg_mask); inst.setSrcReg((code>>shift_rs1) & reg_mask); - inst.setFunc3 ((code>>shift_func3) & func3_mask); - inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask)); + + func3 = (code>>shift_func3) & func3_mask; + inst.setFunc3 (func3); + + if ((func3 == 5) && (op != L_INST)) + { + inst.setSrcImm(signExt(((code>>shift_rs2)®_mask), 5, reg_mask)); + } + else + { + inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask)); + } + usedImm = true; break; case InstType::S_TYPE: - + // std::cout << "************STORE\n"; inst.setSrcReg((code>>shift_rs1) & reg_mask); inst.setSrcReg((code>>shift_rs2) & reg_mask); inst.setFunc3 ((code>>shift_func3) & func3_mask); @@ -324,6 +337,7 @@ Instruction *WordDecoder::decode(const std::vector &v, Size &idx) { dest_bits = (code>>shift_rd) & reg_mask; imm_bits = (code>>shift_s_b_immed & func7_mask); imeed = (imm_bits << reg_s) | dest_bits; + // std::cout << "ENC: store imeed: " << imeed << "\n"; inst.setSrcImm(signExt(imeed, 12, s_immed_mask)); usedImm = true; break; diff --git a/src/harptool.cpp b/src/harptool.cpp index 142c2844..ad570263 100644 --- a/src/harptool.cpp +++ b/src/harptool.cpp @@ -241,6 +241,7 @@ int emu_main(int argc, char **argv) { // std::cout << "TESTING: " << tests[t] << "\n"; + MemoryUnit mu(4096, arch.getWordSize(), basicMachine); Core core(arch, *dec, mu/*, ID in multicore implementations*/); @@ -248,13 +249,12 @@ int emu_main(int argc, char **argv) { RAM old_ram; old_ram.loadHexImpl(imgFileName.c_str()); // old_ram.loadHexImpl(tests[t]); - - // MemDevice * memory = &old_ram; ConsoleMemDevice console(arch.getWordSize(), cout, core, batch); mu.attach(old_ram, 0); mu.attach(console, 1ll<<(arch.getWordSize()*8 - 1)); + // mu.attach(console, 0xf0000000); while (core.running()) { console.poll(); core.step(); } diff --git a/src/include/debug.h b/src/include/debug.h index f79bb4be..36b8b08e 100644 --- a/src/include/debug.h +++ b/src/include/debug.h @@ -4,7 +4,7 @@ #ifndef __DEBUG_H #define __DEBUG_H -#define USE_DEBUG 9 +// #define USE_DEBUG 9 #ifdef USE_DEBUG #include diff --git a/src/include/instruction.h b/src/include/instruction.h index c82352a3..5c309c58 100644 --- a/src/include/instruction.h +++ b/src/include/instruction.h @@ -46,7 +46,7 @@ namespace Harp { {Opcode::R_INST, {"r_type", false, false, false, false, InstType::R_TYPE }}, {Opcode::L_INST, {"load" , false, false, false, false, InstType::I_TYPE }}, {Opcode::I_INST, {"i_type", false, false, false, false, InstType::I_TYPE }}, - {Opcode::S_INST, {"store" , false, false, false, false, InstType::I_TYPE }}, + {Opcode::S_INST, {"store" , false, false, false, false, InstType::S_TYPE }}, {Opcode::B_INST, {"branch", true , false, false, false, InstType::B_TYPE }}, {Opcode::LUI_INST, {"lui" , false, false, false, false, InstType::U_TYPE }}, {Opcode::AUIPC_INST, {"auipc" , false, false, false, false, InstType::U_TYPE }}, diff --git a/src/include/mem.h b/src/include/mem.h index d2ad14cd..e70f2c38 100644 --- a/src/include/mem.h +++ b/src/include/mem.h @@ -236,19 +236,23 @@ namespace Harp { uint8_t third = *get(address + 2); uint8_t fourth = *get(address + 3); - // uint8_t hi = (uint8_t) *get(address + 0); - // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 1); - // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 2); - // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 3); - // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n"; + + // std::cout << std::hex; + // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << (uint32_t) first << "\n"; + // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << (uint32_t) second << "\n"; + // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << (uint32_t) third << "\n"; + // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << (uint32_t) fourth << "\n"; data[0] = (data[0] << 0) | fourth; data[0] = (data[0] << 8) | third; data[0] = (data[0] << 8) | second; data[0] = (data[0] << 8) | first; + // data[0] = (data[0] << 0) | first; + // data[0] = (data[0] << 8) | second; + // data[0] = (data[0] << 8) | third; + // data[0] = (data[0] << 8) | fourth; + + // std::cout << "FINAL DATA: " << data[0] << "\n"; } @@ -309,6 +313,7 @@ namespace Harp { { uint32_t w; getWord(addr, &w); + // std::cout << "RAM: read -> " << w << " at addr: " << addr << "\n"; return (Word) w; } @@ -385,7 +390,7 @@ namespace Harp { unsigned add = nextAddr + i; *(this->get(add)) = hToI_old(line + 9 + i * 2, 2); - // std::cout << "Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl; + // std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl; } break; case 2: @@ -411,6 +416,7 @@ namespace Harp { line++; size--; } + if (content) delete[] content; } diff --git a/src/include/types.h b/src/include/types.h index ae14cd8b..1c5c86d9 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -8,9 +8,9 @@ namespace Harp { typedef uint8_t Byte; - typedef uint64_t Word; - typedef uint64_t Word_u; - typedef int64_t Word_s; + typedef uint32_t Word; + typedef uint32_t Word_u; + typedef int32_t Word_s; typedef Word_u Addr; typedef Word_u Size; diff --git a/src/instruction.cpp b/src/instruction.cpp index 76559470..182b33de 100644 --- a/src/instruction.cpp +++ b/src/instruction.cpp @@ -133,6 +133,7 @@ void Instruction::executeOn(Warp &c) { Word shift_by; Word shamt; Word temp; + Word data_read; int op1, op2; switch (op) { @@ -204,8 +205,11 @@ void Instruction::executeOn(Warp &c) { break; case L_INST: - memAddr = (reg[rsrc[0]] + immsrc) & 0xFFFFFF00; - shift_by = (reg[rsrc[0]] + immsrc) & 0x000000FF; + + memAddr = ((reg[rsrc[0]] + immsrc) & 0xFFFFFFFC); + shift_by = ((reg[rsrc[0]] + immsrc) & 0x00000003) * 8; + data_read = c.core->mem.read(memAddr, c.supervisorMode); + // std::cout < data_read: " << data_read << "\n"; #ifdef EMU_INSTRUMENTATION Harp::OSDomain::osDomain-> do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true); @@ -215,21 +219,22 @@ void Instruction::executeOn(Warp &c) { case 0: // LB - reg[rdest] = signExt((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFF, 8, 0xFF); + reg[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF); break; case 1: // LH - reg[rdest] = signExt((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF, 16, 0xFF); + // std::cout << "shifting by: " << shift_by << " final data: " << ((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF) << "\n"; + reg[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF); break; case 2: - reg[rdest] = int(c.core->mem.read(memAddr, c.supervisorMode) & 0xFFFFFFFF); + reg[rdest] = int(data_read & 0xFFFFFFFF); break; case 4: // LBU - reg[rdest] = Word_u((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFF); + reg[rdest] = unsigned((data_read >> shift_by) & 0xFF); break; case 5: - reg[rdest] = int((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF); + reg[rdest] = unsigned((data_read >> shift_by) & 0xFFFF); break; default: cout << "ERROR: UNSUPPORTED L INST\n"; @@ -309,17 +314,19 @@ void Instruction::executeOn(Warp &c) { break; case S_INST: ++c.stores; - memAddr = reg[rsrc[1]] + immsrc; + memAddr = reg[rsrc[0]] + immsrc; + // std::cout << "STORE MEM ADDRESS: " << std::hex << reg[rsrc[0]] << " + " << immsrc << "\n"; switch (func3) { case 0: - c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 1); + c.core->mem.write(memAddr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1); break; case 1: - c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 2); + // std::cout << std::hex << "INST: about to write: " << reg[rsrc[1]] << " to " << memAddr << "\n"; + c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 2); break; case 2: - c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 4); + c.core->mem.write(memAddr, reg[rsrc[1]], c.supervisorMode, 4); break; default: cout << "ERROR: UNSUPPORTED S INST\n"; @@ -344,8 +351,6 @@ void Instruction::executeOn(Warp &c) { break; case 1: // BNE - // cout << "COMPARING: " << std::hex << int(reg[rsrc[0]]) << " and " << int(reg[rsrc[1]]) << "\n"; - // cout << "COMPARING: " << std::hex << rsrc[0] << " and " << rsrc[1] << "\n"; if (int(reg[rsrc[0]]) != int(reg[rsrc[1]])) { if (!pcSet) nextPc = (c.pc - 4) + immsrc; @@ -407,8 +412,6 @@ void Instruction::executeOn(Warp &c) { { reg[rdest] = c.pc; } - // for (int z = 0; z < 32; z++) std::cout << "&&&&&&&& reg[" << z << "] = " << reg[z] << "\n"; - // std::cout << "jumping to nextPc reg: " << rsrc[0] << " : " << reg[rsrc[0]] << " + " << immsrc << "\n"; pcSet = true; break; case SYS_INST: @@ -418,70 +421,55 @@ void Instruction::executeOn(Warp &c) { case 1: if (rdest != 0) { - // std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - // std::cout << "\t and writing to csr: " << reg[rsrc[0]] << "\n"; c.csr[immsrc & 0x00000FFF] = temp; break; case 2: if (rdest != 0) { - // std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; - reg[rdest] = c.csr[immsrc & 0x00000FFF]; + reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - // std::cout << "\t and writing to csr: " << (reg[rsrc[0]] | c.csr[immsrc & 0x00000FFF]) << "\n"; c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF]; break; case 3: if (rdest != 0) - { - //std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; - + { reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - //std::cout << "\t and writing to csr: " << (temp & (~c.csr[immsrc & 0x00000FFF])) << "\n"; c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]); break; case 5: if (rdest != 0) { - //std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - //std::cout << "\t and writing to csr: " << (rsrc[0]) << "\n"; c.csr[immsrc & 0x00000FFF] = rsrc[0]; break; case 6: if (rdest != 0) - { - //std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; - + { reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - //std::cout << "\t and writing to csr: " << (rsrc[0] | c.csr[immsrc & 0x00000FFF]) << "\n"; c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF]; break; case 7: if (rdest != 0) - { - //std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF]; - - reg[rdest] = c.csr[immsrc & 0x00000FFF]; + { + reg[rdest] = c.csr[immsrc & 0x00000FFF]; } - //std::cout << "\t and writing to csr: " << (rsrc[0] & (~c.csr[immsrc & 0x00000FFF])) << "\n"; c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]); break; case 0: if (immsrc < 2) { - std::cout << "INTERRUPT ECALL\n"; + std::cout << "INTERRUPT ECALL/EBREAK\n"; nextActiveThreads = 0; c.interrupt(0); } diff --git a/src/mem.cpp b/src/mem.cpp index ef72d3da..5df2dbfb 100644 --- a/src/mem.cpp +++ b/src/mem.cpp @@ -87,14 +87,33 @@ Word MemoryUnit::ADecoder::read(Addr a, bool sup, Size wordSize) { Size bit = wordSize - 1; MemDevice &m(doLookup(a, bit)); a &= (2< "; + // std::cout << "Data: " << m.read(a) << "\n"; return m.read(a); } void MemoryUnit::ADecoder::write(Addr a, Word w, bool sup, Size wordSize) { Size bit = wordSize - 1; MemDevice &m(doLookup(a, bit)); - a &= (2<> 8) & 0xFF; + // Word third = (instruction >> 16) & 0xFF; + // Word fourth = (instruction >> 24) & 0xFF; + // instruction = (instruction & 0xFFFFFF00) | fourth; + // instruction = (instruction & 0xFFFF00FF) | (third << 8); + // instruction = (instruction & 0xFF00FFFF) | (second << 16); + // instruction = (instruction & 0x00FFFFFF) | (first << 24); + + return instruction; } void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) { @@ -162,7 +195,9 @@ void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) { TLBEntry t = tlbLookup(vAddr, flagMask); pAddr = t.pfn*pageSize + vAddr%pageSize; } + // std::cout << "MU::write: About to write: " << std::hex << pAddr << " = " << w << " with " << std::dec << 8*bytes << "\n"; ad.write(pAddr, w, sup, 8*bytes); + // std::cout << std::hex << "reading same address: " << (this->read(vAddr, sup)) << "\n"; } void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) { diff --git a/src/results.txt b/src/results.txt index 4348c04e..943bfdd1 100644 --- a/src/results.txt +++ b/src/results.txt @@ -1,12 +1,419 @@ start -./riscv_tests/rv32ui-p-lw.hex -INTERRUPT ECALL -Total steps: 45 -Total insts: 45 +./riscv_tests/rv32ui-p-add.hex +INTERRUPT ECALL/EBREAK +Total steps: 453 +Total insts: 453 === Warp 0 === -Steps : 45 -Insts : 45 +Steps : 453 +Insts : 453 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-addi.hex +INTERRUPT ECALL/EBREAK +Total steps: 230 +Total insts: 230 +=== Warp 0 === +Steps : 230 +Insts : 230 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-and.hex +INTERRUPT ECALL/EBREAK +Total steps: 473 +Total insts: 473 +=== Warp 0 === +Steps : 473 +Insts : 473 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-andi.hex +INTERRUPT ECALL/EBREAK +Total steps: 186 +Total insts: 186 +=== Warp 0 === +Steps : 186 +Insts : 186 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-auipc.hex +INTERRUPT ECALL/EBREAK +Total steps: 47 +Total insts: 47 +=== Warp 0 === +Steps : 47 +Insts : 47 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-beq.hex +INTERRUPT ECALL/EBREAK +Total steps: 279 +Total insts: 279 +=== Warp 0 === +Steps : 279 +Insts : 279 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-bge.hex +INTERRUPT ECALL/EBREAK +Total steps: 297 +Total insts: 297 +=== Warp 0 === +Steps : 297 +Insts : 297 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-bgeu.hex +INTERRUPT ECALL/EBREAK +Total steps: 322 +Total insts: 322 +=== Warp 0 === +Steps : 322 +Insts : 322 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-blt.hex +INTERRUPT ECALL/EBREAK +Total steps: 279 +Total insts: 279 +=== Warp 0 === +Steps : 279 +Insts : 279 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-bltu.hex +INTERRUPT ECALL/EBREAK +Total steps: 304 +Total insts: 304 +=== Warp 0 === +Steps : 304 +Insts : 304 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-bne.hex +INTERRUPT ECALL/EBREAK +Total steps: 279 +Total insts: 279 +=== Warp 0 === +Steps : 279 +Insts : 279 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-jal.hex +INTERRUPT ECALL/EBREAK +Total steps: 43 +Total insts: 43 +=== Warp 0 === +Steps : 43 +Insts : 43 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-jalr.hex +INTERRUPT ECALL/EBREAK +Total steps: 96 +Total insts: 96 +=== Warp 0 === +Steps : 96 +Insts : 96 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lb.hex +INTERRUPT ECALL/EBREAK +Total steps: 233 +Total insts: 233 +=== Warp 0 === +Steps : 233 +Insts : 233 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lbu.hex +INTERRUPT ECALL/EBREAK +Total steps: 233 +Total insts: 233 +=== Warp 0 === +Steps : 233 +Insts : 233 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lh.hex +INTERRUPT ECALL/EBREAK +Total steps: 245 +Total insts: 245 +=== Warp 0 === +Steps : 245 +Insts : 245 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lhu.hex +INTERRUPT ECALL/EBREAK +Total steps: 252 +Total insts: 252 +=== Warp 0 === +Steps : 252 +Insts : 252 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lui.hex +INTERRUPT ECALL/EBREAK +Total steps: 53 +Total insts: 53 +=== Warp 0 === +Steps : 53 +Insts : 53 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-lw.hex +INTERRUPT ECALL/EBREAK +Total steps: 255 +Total insts: 255 +=== Warp 0 === +Steps : 255 +Insts : 255 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-or.hex +INTERRUPT ECALL/EBREAK +Total steps: 476 +Total insts: 476 +=== Warp 0 === +Steps : 476 +Insts : 476 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-ori.hex +INTERRUPT ECALL/EBREAK +Total steps: 193 +Total insts: 193 +=== Warp 0 === +Steps : 193 +Insts : 193 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sb.hex +INTERRUPT ECALL/EBREAK +Total steps: 418 +Total insts: 418 +=== Warp 0 === +Steps : 418 +Insts : 418 +Loads : 0 +Stores: 35 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sh.hex +INTERRUPT ECALL/EBREAK +Total steps: 471 +Total insts: 471 +=== Warp 0 === +Steps : 471 +Insts : 471 +Loads : 0 +Stores: 35 +GRADE: PASSED + +./riscv_tests/rv32ui-p-simple.hex +INTERRUPT ECALL/EBREAK +Total steps: 29 +Total insts: 29 +=== Warp 0 === +Steps : 29 +Insts : 29 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sll.hex +INTERRUPT ECALL/EBREAK +Total steps: 481 +Total insts: 481 +=== Warp 0 === +Steps : 481 +Insts : 481 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-slli.hex +INTERRUPT ECALL/EBREAK +Total steps: 229 +Total insts: 229 +=== Warp 0 === +Steps : 229 +Insts : 229 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-slt.hex +INTERRUPT ECALL/EBREAK +Total steps: 447 +Total insts: 447 +=== Warp 0 === +Steps : 447 +Insts : 447 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-slti.hex +INTERRUPT ECALL/EBREAK +Total steps: 225 +Total insts: 225 +=== Warp 0 === +Steps : 225 +Insts : 225 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sltiu.hex +INTERRUPT ECALL/EBREAK +Total steps: 225 +Total insts: 225 +=== Warp 0 === +Steps : 225 +Insts : 225 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sltu.hex +INTERRUPT ECALL/EBREAK +Total steps: 447 +Total insts: 447 +=== Warp 0 === +Steps : 447 +Insts : 447 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sra.hex +INTERRUPT ECALL/EBREAK +Total steps: 500 +Total insts: 500 +=== Warp 0 === +Steps : 500 +Insts : 500 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-srai.hex +INTERRUPT ECALL/EBREAK +Total steps: 41 +Total insts: 41 +=== Warp 0 === +Steps : 41 +Insts : 41 Loads : 0 Stores: 0 GRADE: FAILED 3 +./riscv_tests/rv32ui-p-srl.hex +INTERRUPT ECALL/EBREAK +Total steps: 494 +Total insts: 494 +=== Warp 0 === +Steps : 494 +Insts : 494 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-srli.hex +INTERRUPT ECALL/EBREAK +Total steps: 238 +Total insts: 238 +=== Warp 0 === +Steps : 238 +Insts : 238 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sub.hex +INTERRUPT ECALL/EBREAK +Total steps: 445 +Total insts: 445 +=== Warp 0 === +Steps : 445 +Insts : 445 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-sw.hex +INTERRUPT ECALL/EBREAK +Total steps: 478 +Total insts: 478 +=== Warp 0 === +Steps : 478 +Insts : 478 +Loads : 0 +Stores: 34 +GRADE: PASSED + +./riscv_tests/rv32ui-p-xor.hex +INTERRUPT ECALL/EBREAK +Total steps: 475 +Total insts: 475 +=== Warp 0 === +Steps : 475 +Insts : 475 +Loads : 0 +Stores: 0 +GRADE: PASSED + +./riscv_tests/rv32ui-p-xori.hex +INTERRUPT ECALL/EBREAK +Total steps: 195 +Total insts: 195 +=== Warp 0 === +Steps : 195 +Insts : 195 +Loads : 0 +Stores: 0 +GRADE: PASSED + diff --git a/src/test.sh b/src/test.sh index 274151dd..7938b5db 100755 --- a/src/test.sh +++ b/src/test.sh @@ -1,115 +1,115 @@ echo start > results.txt -# echo ./riscv_tests/rv32ui-p-add.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-add.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-add.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-add.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-and.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-and.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-and.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-and.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-or.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-or.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-or.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-or.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt -# echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt -# ./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt +echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt +./harptool -E -a rv32i --core ./riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt