clear req after sending
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BIN
hw/unit_tests/cache/obj_dir/VVX_cache
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BIN
hw/unit_tests/cache/obj_dir/VVX_cache
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hw/unit_tests/cache/obj_dir/testbench.o
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hw/unit_tests/cache/obj_dir/testbench.o
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hw/unit_tests/cache/testbench.cpp
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8
hw/unit_tests/cache/testbench.cpp
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@@ -20,9 +20,9 @@ int main(int argc, char **argv)
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cachesim.set_core_req();
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cachesim.set_core_req();
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for (int i = 0; i < 100; ++i){
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for (int i = 0; i < 100; ++i){
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/*if(i == 1){
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if(i == 1){
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cachesim.clear_req();
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cachesim.clear_req();
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}*/
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}
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cachesim.step();
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cachesim.step();
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cachesim.get_core_rsp();
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cachesim.get_core_rsp();
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}
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}
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@@ -30,11 +30,11 @@ int main(int argc, char **argv)
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// read block
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// read block
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cachesim.set_core_req2();
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cachesim.set_core_req2();
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for (int i = 0; i < 100; ++i){
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for (int i = 0; i < 100; ++i){
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/*if(i == 1){
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if(i == 1){
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//read block from cache
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//read block from cache
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cachesim.clear_req();
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cachesim.clear_req();
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}*/
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}
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cachesim.step();
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cachesim.step();
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cachesim.get_core_rsp();
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cachesim.get_core_rsp();
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}
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}
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12729
hw/unit_tests/cache/trace.vcd
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12729
hw/unit_tests/cache/trace.vcd
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