diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 75ab0dee..e4c98706 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -9,49 +9,49 @@ module VX_back_end input wire reset, input wire schedule_delay, - VX_gpu_dcache_rsp_inter vx_dcache_rsp, - VX_gpu_dcache_req_inter vx_dcache_req, + VX_gpu_dcache_rsp_if vx_dcache_rsp, + VX_gpu_dcache_req_if vx_dcache_req, output wire out_mem_delay, output wire out_exec_delay, output wire gpr_stage_delay, - VX_jal_response_inter vx_jal_rsp, - VX_branch_response_inter vx_branch_rsp, + VX_jal_response_if vx_jal_rsp, + VX_branch_response_if vx_branch_rsp, - VX_frE_to_bckE_req_inter vx_bckE_req, - VX_wb_inter vx_writeback_inter, + VX_frE_to_bckE_req_if vx_bckE_req, + VX_wb_if vx_writeback_if, - VX_warp_ctl_inter vx_warp_ctl + VX_warp_ctl_if vx_warp_ctl ); -VX_wb_inter vx_writeback_temp(); -assign vx_writeback_inter.wb = vx_writeback_temp.wb; -assign vx_writeback_inter.rd = vx_writeback_temp.rd; -assign vx_writeback_inter.write_data = vx_writeback_temp.write_data; -assign vx_writeback_inter.wb_valid = vx_writeback_temp.wb_valid; -assign vx_writeback_inter.wb_warp_num = vx_writeback_temp.wb_warp_num; -assign vx_writeback_inter.wb_pc = vx_writeback_temp.wb_pc; +VX_wb_if vx_writeback_temp(); +assign vx_writeback_if.wb = vx_writeback_temp.wb; +assign vx_writeback_if.rd = vx_writeback_temp.rd; +assign vx_writeback_if.write_data = vx_writeback_temp.write_data; +assign vx_writeback_if.wb_valid = vx_writeback_temp.wb_valid; +assign vx_writeback_if.wb_warp_num = vx_writeback_temp.wb_warp_num; +assign vx_writeback_if.wb_pc = vx_writeback_temp.wb_pc; -// assign VX_writeback_inter(vx_writeback_temp); +// assign VX_writeback_if(vx_writeback_temp); wire no_slot_mem; wire no_slot_exec; // LSU input + output -VX_lsu_req_inter vx_lsu_req(); -VX_inst_mem_wb_inter vx_mem_wb(); +VX_lsu_req_if vx_lsu_req(); +VX_inst_mem_wb_if vx_mem_wb(); // Exec unit input + output -VX_exec_unit_req_inter vx_exec_unit_req(); -VX_inst_exec_wb_inter vx_inst_exec_wb(); +VX_exec_unit_req_if vx_exec_unit_req(); +VX_inst_exec_wb_if vx_inst_exec_wb(); // GPU unit input -VX_gpu_inst_req_inter vx_gpu_inst_req(); +VX_gpu_inst_req_if vx_gpu_inst_req(); // CSR unit inputs -VX_csr_req_inter vx_csr_req(); -VX_csr_wb_inter vx_csr_wb(); +VX_csr_req_if vx_csr_req(); +VX_csr_wb_if vx_csr_wb(); wire no_slot_csr; wire stall_gpr_csr; @@ -59,7 +59,7 @@ VX_gpr_stage vx_gpr_stage( .clk (clk), .reset (reset), .schedule_delay (schedule_delay), - .vx_writeback_inter(vx_writeback_temp), + .vx_writeback_if(vx_writeback_temp), .vx_bckE_req (vx_bckE_req), // New .vx_exec_unit_req(vx_exec_unit_req), @@ -124,7 +124,7 @@ VX_writeback vx_wb ( .vx_inst_exec_wb (vx_inst_exec_wb), .vx_csr_wb (vx_csr_wb), - .vx_writeback_inter(vx_writeback_temp), + .vx_writeback_if(vx_writeback_temp), .no_slot_mem (no_slot_mem), .no_slot_exec (no_slot_exec), .no_slot_csr (no_slot_csr) diff --git a/hw/rtl/VX_csr_handler.v b/hw/rtl/VX_csr_handler.v index a2458432..f9cbde45 100644 --- a/hw/rtl/VX_csr_handler.v +++ b/hw/rtl/VX_csr_handler.v @@ -1,7 +1,7 @@ module VX_csr_handler ( input wire clk, input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done - VX_csr_write_request_inter vx_csr_w_req, + VX_csr_write_request_if vx_csr_w_req, input wire in_wb_valid, output wire[31:0] out_decode_csr_data // done ); diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index 507ec18f..029e08ce 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -6,9 +6,9 @@ module VX_csr_pipe #( input wire clk, // Clock input wire reset, input wire no_slot_csr, - VX_csr_req_inter vx_csr_req, - VX_wb_inter vx_writeback, - VX_csr_wb_inter vx_csr_wb, + VX_csr_req_if vx_csr_req, + VX_wb_if vx_writeback, + VX_csr_wb_if vx_csr_wb, output wire stall_gpr_csr ); diff --git a/hw/rtl/VX_csr_wrapper.v b/hw/rtl/VX_csr_wrapper.v index 6c37fdc3..3fcfb31a 100644 --- a/hw/rtl/VX_csr_wrapper.v +++ b/hw/rtl/VX_csr_wrapper.v @@ -2,8 +2,8 @@ `include "VX_define.vh" module VX_csr_wrapper ( - VX_csr_req_inter vx_csr_req, - VX_csr_wb_inter vx_csr_wb + VX_csr_req_if vx_csr_req, + VX_csr_wb_if vx_csr_wb ); diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 3256eab1..de00a171 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -3,12 +3,12 @@ module VX_decode( // Fetch Inputs - VX_inst_meta_inter fd_inst_meta_de, + VX_inst_meta_if fd_inst_meta_de, // Outputs - VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, - VX_wstall_inter vx_wstall, - VX_join_inter vx_join, + VX_frE_to_bckE_req_if vx_frE_to_bckE_req, + VX_wstall_if vx_wstall, + VX_join_if vx_join, output wire terminate_sim diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 5b1d13bc..df74dd70 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -12,8 +12,13 @@ `define DEBUG_BEGIN /* verilator lint_off UNUSED */ `define DEBUG_END /* verilator lint_on UNUSED */ -`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ -`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ +`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ + /* verilator lint_off PINCONNECTEMPTY */ \ + /* verilator lint_off DECLFILENAME */ + +`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ + /* verilator lint_on PINCONNECTEMPTY */ \ + /* verilator lint_on DECLFILENAME */ `define STRINGIFY(x) `"x`" diff --git a/hw/rtl/VX_dmem_controller.v b/hw/rtl/VX_dmem_controller.v index 9da1fbf7..bd5b31c7 100644 --- a/hw/rtl/VX_dmem_controller.v +++ b/hw/rtl/VX_dmem_controller.v @@ -5,29 +5,29 @@ module VX_dmem_controller ( input wire reset, // Dram <-> Dcache - VX_gpu_dcache_dram_req_inter vx_gpu_dcache_dram_req, - VX_gpu_dcache_dram_rsp_inter vx_gpu_dcache_dram_res, - VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req, + VX_gpu_dcache_dram_req_if vx_gpu_dcache_dram_req, + VX_gpu_dcache_dram_rsp_if vx_gpu_dcache_dram_res, + VX_gpu_snp_req_rsp_if vx_gpu_dcache_snp_req, // Dram <-> Icache - VX_gpu_dcache_dram_req_inter vx_gpu_icache_dram_req, - VX_gpu_dcache_dram_rsp_inter vx_gpu_icache_dram_res, - VX_gpu_snp_req_rsp vx_gpu_icache_snp_req, + VX_gpu_dcache_dram_req_if vx_gpu_icache_dram_req, + VX_gpu_dcache_dram_rsp_if vx_gpu_icache_dram_res, + VX_gpu_snp_req_rsp_if vx_gpu_icache_snp_req, // Core <-> Dcache - VX_gpu_dcache_rsp_inter vx_dcache_rsp, - VX_gpu_dcache_req_inter vx_dcache_req, + VX_gpu_dcache_rsp_if vx_dcache_rsp, + VX_gpu_dcache_req_if vx_dcache_req, // Core <-> Icache - VX_gpu_dcache_rsp_inter vx_icache_rsp, - VX_gpu_dcache_req_inter vx_icache_req + VX_gpu_dcache_rsp_if vx_icache_rsp, + VX_gpu_dcache_req_if vx_icache_req ); - VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_smem(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_smem(); + VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_smem(); + VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_smem(); - VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_dcache(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_dcache(); + VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_dcache(); + VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_dcache(); wire to_shm = vx_dcache_req.core_req_addr[0][31:24] == 8'hFF; wire dcache_wants_wb = (|vx_dcache_rsp_dcache.core_wb_valid); @@ -66,8 +66,8 @@ module VX_dmem_controller ( assign vx_dcache_rsp.delay_req = to_shm ? vx_dcache_rsp_smem.delay_req : vx_dcache_rsp_dcache.delay_req; - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_req(); - VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_res(); + VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_req(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_res(); VX_cache #( .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), @@ -118,9 +118,9 @@ module VX_dmem_controller ( .core_wb_warp_num (vx_dcache_rsp_smem.core_wb_warp_num), .core_wb_readdata (vx_dcache_rsp_smem.core_wb_readdata), .core_wb_pc (vx_dcache_rsp_smem.core_wb_pc), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .core_wb_address (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END // DRAM response .dram_rsp_valid (vx_gpu_smem_dram_res.dram_rsp_valid), @@ -140,15 +140,15 @@ module VX_dmem_controller ( // Snoop Request .snp_req_valid (0), .snp_req_addr (0), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .snp_req_full (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END // Snoop Forward - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .snp_fwd_valid (), .snp_fwd_addr (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END .snp_fwd_full (0) ); @@ -201,9 +201,9 @@ module VX_dmem_controller ( .core_wb_warp_num (vx_dcache_rsp_dcache.core_wb_warp_num), .core_wb_readdata (vx_dcache_rsp_dcache.core_wb_readdata), .core_wb_pc (vx_dcache_rsp_dcache.core_wb_pc), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .core_wb_address (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END // DRAM response .dram_rsp_valid (vx_gpu_dcache_dram_res.dram_rsp_valid), @@ -226,10 +226,10 @@ module VX_dmem_controller ( .snp_req_full (vx_gpu_dcache_snp_req.snp_req_full), // Snoop Forward - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .snp_fwd_valid (), .snp_fwd_addr (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END .snp_fwd_full (0) ); @@ -282,9 +282,9 @@ module VX_dmem_controller ( .core_wb_warp_num (vx_icache_rsp.core_wb_warp_num), .core_wb_readdata (vx_icache_rsp.core_wb_readdata), .core_wb_pc (vx_icache_rsp.core_wb_pc), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .core_wb_address (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END // DRAM response .dram_rsp_valid (vx_gpu_icache_dram_res.dram_rsp_valid), @@ -307,10 +307,10 @@ module VX_dmem_controller ( .snp_req_full (vx_gpu_icache_snp_req.snp_req_full), // Snoop Forward - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .snp_fwd_valid (), .snp_fwd_addr (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END .snp_fwd_full (0) ); diff --git a/hw/rtl/VX_execute_unit.v b/hw/rtl/VX_execute_unit.v index 383b0eb6..f89db41e 100644 --- a/hw/rtl/VX_execute_unit.v +++ b/hw/rtl/VX_execute_unit.v @@ -4,15 +4,15 @@ module VX_execute_unit ( input wire clk, input wire reset, // Request - VX_exec_unit_req_inter vx_exec_unit_req, + VX_exec_unit_req_if vx_exec_unit_req, // Output // Writeback - VX_inst_exec_wb_inter vx_inst_exec_wb, + VX_inst_exec_wb_if vx_inst_exec_wb, // JAL Response - VX_jal_response_inter vx_jal_rsp, + VX_jal_response_if vx_jal_rsp, // Branch Response - VX_branch_response_inter vx_branch_rsp, + VX_branch_response_if vx_branch_rsp, input wire no_slot_exec, output wire out_delay @@ -109,11 +109,11 @@ module VX_execute_unit ( endgenerate - // VX_inst_exec_wb_inter vx_inst_exec_wb_temp(); + // VX_inst_exec_wb_if vx_inst_exec_wb_temp(); // JAL Response - VX_jal_response_inter vx_jal_rsp_temp(); + VX_jal_response_if vx_jal_rsp_temp(); // Branch Response - VX_branch_response_inter vx_branch_rsp_temp(); + VX_branch_response_if vx_branch_rsp_temp(); // Actual Writeback assign vx_inst_exec_wb.rd = vx_exec_unit_req.rd; diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 9b5bd934..7d4dca6f 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -3,18 +3,18 @@ module VX_fetch ( input wire clk, input wire reset, - VX_wstall_inter vx_wstall, - VX_join_inter vx_join, + VX_wstall_if vx_wstall, + VX_join_if vx_join, input wire schedule_delay, input wire icache_stage_delay, input wire[`NW_BITS-1:0] icache_stage_wid, input wire[`NUM_THREADS-1:0] icache_stage_valids, output wire out_ebreak, - VX_jal_response_inter vx_jal_rsp, - VX_branch_response_inter vx_branch_rsp, - VX_inst_meta_inter fe_inst_meta_fi, - VX_warp_ctl_inter vx_warp_ctl + VX_jal_response_if vx_jal_rsp, + VX_branch_response_if vx_branch_rsp, + VX_inst_meta_if fe_inst_meta_fi, + VX_warp_ctl_if vx_warp_ctl ); wire[`NUM_THREADS-1:0] thread_mask; diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 0bd2cce2..3cb20691 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -6,26 +6,26 @@ module VX_front_end ( input wire schedule_delay, - VX_warp_ctl_inter vx_warp_ctl, + VX_warp_ctl_if vx_warp_ctl, - VX_gpu_dcache_rsp_inter vx_icache_rsp, - VX_gpu_dcache_req_inter vx_icache_req, + VX_gpu_dcache_rsp_if vx_icache_rsp, + VX_gpu_dcache_req_if vx_icache_req, - VX_jal_response_inter vx_jal_rsp, - VX_branch_response_inter vx_branch_rsp, + VX_jal_response_if vx_jal_rsp, + VX_branch_response_if vx_branch_rsp, - VX_frE_to_bckE_req_inter vx_bckE_req, + VX_frE_to_bckE_req_if vx_bckE_req, output wire fetch_ebreak ); -VX_inst_meta_inter fe_inst_meta_fi(); -VX_inst_meta_inter fe_inst_meta_fi2(); -VX_inst_meta_inter fe_inst_meta_id(); +VX_inst_meta_if fe_inst_meta_fi(); +VX_inst_meta_if fe_inst_meta_fi2(); +VX_inst_meta_if fe_inst_meta_id(); -VX_frE_to_bckE_req_inter vx_frE_to_bckE_req(); -VX_inst_meta_inter fd_inst_meta_de(); +VX_frE_to_bckE_req_if vx_frE_to_bckE_req(); +VX_inst_meta_if fd_inst_meta_de(); wire total_freeze = schedule_delay; wire icache_stage_delay; @@ -48,8 +48,8 @@ end assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak; -VX_wstall_inter vx_wstall(); -VX_join_inter vx_join(); +VX_wstall_if vx_wstall(); +VX_join_if vx_join(); VX_fetch vx_fetch( .clk (clk), diff --git a/hw/rtl/VX_gpgpu_inst.v b/hw/rtl/VX_gpgpu_inst.v index f075a80a..74ffb7cc 100644 --- a/hw/rtl/VX_gpgpu_inst.v +++ b/hw/rtl/VX_gpgpu_inst.v @@ -2,10 +2,10 @@ module VX_gpgpu_inst ( // Input - VX_gpu_inst_req_inter vx_gpu_inst_req, + VX_gpu_inst_req_if vx_gpu_inst_req, // Output - VX_warp_ctl_inter vx_warp_ctl + VX_warp_ctl_if vx_warp_ctl ); wire[`NUM_THREADS-1:0] curr_valids = vx_gpu_inst_req.valid; wire is_split = (vx_gpu_inst_req.is_split); diff --git a/hw/rtl/VX_gpr.v b/hw/rtl/VX_gpr.v index 51a26187..e338a7a7 100644 --- a/hw/rtl/VX_gpr.v +++ b/hw/rtl/VX_gpr.v @@ -4,8 +4,8 @@ module VX_gpr ( input wire clk, input wire reset, input wire valid_write_request, - VX_gpr_read_inter vx_gpr_read, - VX_wb_inter vx_writeback_inter, + VX_gpr_read_if vx_gpr_read, + VX_wb_if vx_writeback_if, output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_a_reg_data, output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_b_reg_data @@ -13,28 +13,28 @@ module VX_gpr ( wire write_enable; `ifndef ASIC - assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)) && (vx_writeback_inter.rd != 0); + assign write_enable = valid_write_request && ((vx_writeback_if.wb != 0)) && (vx_writeback_if.rd != 0); byte_enabled_simple_dual_port_ram first_ram( .we (write_enable), .clk (clk), .reset (reset), - .waddr (vx_writeback_inter.rd), + .waddr (vx_writeback_if.rd), .raddr1(vx_gpr_read.rs1), .raddr2(vx_gpr_read.rs2), - .be (vx_writeback_inter.wb_valid), - .wdata (vx_writeback_inter.write_data), + .be (vx_writeback_if.wb_valid), + .wdata (vx_writeback_if.write_data), .q1 (out_a_reg_data), .q2 (out_b_reg_data) ); `else - assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)); - wire going_to_write = write_enable & (|vx_writeback_inter.wb_valid); + assign write_enable = valid_write_request && ((vx_writeback_if.wb != 0)); + wire going_to_write = write_enable & (|vx_writeback_if.wb_valid); wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; genvar curr_t; for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin - wire local_write = write_enable & vx_writeback_inter.wb_valid[curr_t]; + wire local_write = write_enable & vx_writeback_if.wb_valid[curr_t]; assign write_bit_mask[curr_t] = {`NUM_GPRS{~local_write}}; end @@ -65,12 +65,12 @@ module VX_gpr ( assign out_b_reg_data = temp_b; `endif - wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (vx_writeback_inter.rd != 0) ? vx_writeback_inter.write_data : 0; + wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (vx_writeback_if.rd != 0) ? vx_writeback_if.write_data : 0; genvar curr_base_thread; for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4) begin - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN rf2_32x128_wm1 first_ram ( .CENYA(), .AYA(), @@ -86,7 +86,7 @@ module VX_gpr ( .CLKB(clk), .CENB(cenb), .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), - .AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .AB(vx_writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]), .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), .EMAA(3'b011), .EMASA(1'b0), @@ -107,9 +107,9 @@ module VX_gpr ( .SEB(1'b0), .COLLDISN(1'b1) ); - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN rf2_`NUM_GPRSx128_wm1 second_ram ( .CENYA(), .AYA(), @@ -125,7 +125,7 @@ module VX_gpr ( .CLKB(clk), .CENB(cenb), .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), - .AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), + .AB(vx_writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]), .DB(to_write[(curr_base_thread+3):(curr_base_thread)]), .EMAA(3'b011), .EMASA(1'b0), @@ -146,7 +146,7 @@ module VX_gpr ( .SEB(1'b0), .COLLDISN(1'b1) ); - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END end `endif diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 6ef429e8..16a8884c 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -12,16 +12,16 @@ module VX_gpr_stage ( // inputs // Instruction Information - VX_frE_to_bckE_req_inter vx_bckE_req, + VX_frE_to_bckE_req_if vx_bckE_req, // WriteBack inputs - VX_wb_inter vx_writeback_inter, + VX_wb_if vx_writeback_if, // Outputs - VX_exec_unit_req_inter vx_exec_unit_req, - VX_lsu_req_inter vx_lsu_req, - VX_gpu_inst_req_inter vx_gpu_inst_req, - VX_csr_req_inter vx_csr_req + VX_exec_unit_req_if vx_exec_unit_req, + VX_lsu_req_if vx_lsu_req, + VX_gpu_inst_req_if vx_gpu_inst_req, + VX_csr_req_if vx_csr_req ); `DEBUG_BEGIN wire[31:0] curr_PC = vx_bckE_req.curr_PC; @@ -31,27 +31,27 @@ module VX_gpr_stage ( wire jalQual = vx_bckE_req.jalQual; `DEBUG_END - VX_gpr_read_inter vx_gpr_read(); + VX_gpr_read_if vx_gpr_read(); assign vx_gpr_read.rs1 = vx_bckE_req.rs1; assign vx_gpr_read.rs2 = vx_bckE_req.rs2; assign vx_gpr_read.warp_num = vx_bckE_req.warp_num; `ifndef ASIC - VX_gpr_jal_inter vx_gpr_jal(); + VX_gpr_jal_if vx_gpr_jal(); assign vx_gpr_jal.is_jal = vx_bckE_req.jalQual; assign vx_gpr_jal.curr_PC = vx_bckE_req.curr_PC; `else - VX_gpr_jal_inter vx_gpr_jal(); + VX_gpr_jal_if vx_gpr_jal(); assign vx_gpr_jal.is_jal = vx_exec_unit_req.jalQual; assign vx_gpr_jal.curr_PC = vx_exec_unit_req.curr_PC; `endif - VX_gpr_data_inter vx_gpr_datf(); + VX_gpr_data_if vx_gpr_datf(); VX_gpr_wrapper vx_grp_wrapper ( .clk (clk), .reset (reset), - .vx_writeback_inter(vx_writeback_inter), + .vx_writeback_if(vx_writeback_if), .vx_gpr_read (vx_gpr_read), .vx_gpr_jal (vx_gpr_jal), @@ -63,10 +63,10 @@ module VX_gpr_stage ( // assign vx_bckE_req_out.csr_mask = (vx_bckE_req.sr_immed == 1'b1) ? {27'h0, vx_bckE_req.rs1} : vx_gpr_data.a_reg_data[0]; // Outputs - VX_exec_unit_req_inter vx_exec_unit_req_temp(); - VX_lsu_req_inter vx_lsu_req_temp(); - VX_gpu_inst_req_inter vx_gpu_inst_req_temp(); - VX_csr_req_inter vx_csr_req_temp(); + VX_exec_unit_req_if vx_exec_unit_req_temp(); + VX_lsu_req_if vx_lsu_req_temp(); + VX_gpu_inst_req_if vx_gpu_inst_req_temp(); + VX_csr_req_if vx_csr_req_temp(); VX_inst_multiplex vx_inst_mult( .vx_bckE_req (vx_bckE_req), diff --git a/hw/rtl/VX_gpr_wrapper.v b/hw/rtl/VX_gpr_wrapper.v index df682245..b4d1f3bd 100644 --- a/hw/rtl/VX_gpr_wrapper.v +++ b/hw/rtl/VX_gpr_wrapper.v @@ -3,9 +3,9 @@ module VX_gpr_wrapper ( input wire clk, input wire reset, - VX_gpr_read_inter vx_gpr_read, - VX_wb_inter vx_writeback_inter, - VX_gpr_jal_inter vx_gpr_jal, + VX_gpr_read_if vx_gpr_read, + VX_wb_if vx_writeback_if, + VX_gpr_jal_if vx_gpr_jal, output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data, output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data @@ -52,13 +52,13 @@ module VX_gpr_wrapper ( for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs - wire valid_write_request = warp_index == vx_writeback_inter.wb_warp_num; + wire valid_write_request = warp_index == vx_writeback_if.wb_warp_num; VX_gpr vx_gpr( .clk (clk), .reset (reset), .valid_write_request(valid_write_request), .vx_gpr_read (vx_gpr_read), - .vx_writeback_inter (vx_writeback_inter), + .vx_writeback_if (vx_writeback_if), .out_a_reg_data (temp_a_reg_data[warp_index]), .out_b_reg_data (temp_b_reg_data[warp_index]) ); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 6aa8dfa7..d07736bd 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -7,11 +7,11 @@ module VX_icache_stage ( output wire icache_stage_delay, output wire[`NW_BITS-1:0] icache_stage_wid, output wire[`NUM_THREADS-1:0] icache_stage_valids, - VX_inst_meta_inter fe_inst_meta_fi, - VX_inst_meta_inter fe_inst_meta_id, + VX_inst_meta_if fe_inst_meta_fi, + VX_inst_meta_if fe_inst_meta_id, - VX_gpu_dcache_rsp_inter vx_icache_rsp, - VX_gpu_dcache_req_inter vx_icache_req + VX_gpu_dcache_rsp_if vx_icache_rsp, + VX_gpu_dcache_req_if vx_icache_req ); reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0]; diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index 918b9a74..a789b8b0 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -2,14 +2,14 @@ module VX_inst_multiplex ( // Inputs - VX_frE_to_bckE_req_inter vx_bckE_req, - VX_gpr_data_inter vx_gpr_data, + VX_frE_to_bckE_req_if vx_bckE_req, + VX_gpr_data_if vx_gpr_data, // Outputs - VX_exec_unit_req_inter vx_exec_unit_req, - VX_lsu_req_inter vx_lsu_req, - VX_gpu_inst_req_inter vx_gpu_inst_req, - VX_csr_req_inter vx_csr_req + VX_exec_unit_req_if vx_exec_unit_req, + VX_lsu_req_if vx_lsu_req, + VX_gpu_inst_req_if vx_gpu_inst_req, + VX_csr_req_if vx_csr_req ); wire[`NUM_THREADS-1:0] is_mem_mask; diff --git a/hw/rtl/VX_lsu.v b/hw/rtl/VX_lsu.v index 61e4e44e..cd36eaf8 100644 --- a/hw/rtl/VX_lsu.v +++ b/hw/rtl/VX_lsu.v @@ -4,13 +4,13 @@ module VX_lsu ( input wire clk, input wire reset, input wire no_slot_mem, - VX_lsu_req_inter vx_lsu_req, + VX_lsu_req_if vx_lsu_req, // Write back to GPR - VX_inst_mem_wb_inter vx_mem_wb, + VX_inst_mem_wb_if vx_mem_wb, - VX_gpu_dcache_rsp_inter vx_dcache_rsp, - VX_gpu_dcache_req_inter vx_dcache_req, + VX_gpu_dcache_rsp_if vx_dcache_rsp, + VX_gpu_dcache_req_if vx_dcache_req, output wire out_delay ); // Generate Addresses diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index 5be151f6..9bf17ea8 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -6,8 +6,8 @@ module VX_scheduler ( input wire memory_delay, input wire exec_delay, input wire gpr_stage_delay, - VX_frE_to_bckE_req_inter vx_bckE_req, - VX_wb_inter vx_writeback_inter, + VX_frE_to_bckE_req_if vx_bckE_req, + VX_wb_if vx_writeback_if, output wire schedule_delay, output wire is_empty @@ -18,7 +18,7 @@ module VX_scheduler ( reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0]; - wire valid_wb = (vx_writeback_inter.wb != 0) && (|vx_writeback_inter.wb_valid) && (vx_writeback_inter.rd != 0); + wire valid_wb = (vx_writeback_if.wb != 0) && (|vx_writeback_if.wb_valid) && (vx_writeback_if.rd != 0); wire wb_inc = (vx_bckE_req.wb != 0) && (vx_bckE_req.rd != 0); wire rs1_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rs1] != 0; @@ -59,7 +59,7 @@ module VX_scheduler ( end end else begin if (valid_wb) begin - rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] <= rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & (~vx_writeback_inter.wb_valid); + rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] <= rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] & (~vx_writeback_if.wb_valid); end if (!schedule_delay && wb_inc) begin @@ -67,7 +67,7 @@ module VX_scheduler ( end if (valid_wb - && (0 == (rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & ~vx_writeback_inter.wb_valid))) begin + && (0 == (rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] & ~vx_writeback_if.wb_valid))) begin count_valid <= count_valid - 1; end diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 696cb652..6f5ed918 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -4,20 +4,20 @@ module VX_writeback ( input wire clk, input wire reset, // Mem WB info - VX_inst_mem_wb_inter vx_mem_wb, + VX_inst_mem_wb_if vx_mem_wb, // EXEC Unit WB info - VX_inst_exec_wb_inter vx_inst_exec_wb, + VX_inst_exec_wb_if vx_inst_exec_wb, // CSR Unit WB info - VX_csr_wb_inter vx_csr_wb, + VX_csr_wb_if vx_csr_wb, // Actual WB to GPR - VX_wb_inter vx_writeback_inter, + VX_wb_if vx_writeback_if, output wire no_slot_mem, output wire no_slot_exec, output wire no_slot_csr ); - VX_wb_inter vx_writeback_tempp(); + VX_wb_if vx_writeback_tempp(); wire exec_wb = (vx_inst_exec_wb.wb != 0) && (|vx_inst_exec_wb.wb_valid); wire mem_wb = (vx_mem_wb.wb != 0) && (|vx_mem_wb.wb_valid); @@ -72,18 +72,18 @@ module VX_writeback ( .stall(zero), .flush(zero), .in ({vx_writeback_tempp.write_data, vx_writeback_tempp.wb_valid, vx_writeback_tempp.rd, vx_writeback_tempp.wb, vx_writeback_tempp.wb_warp_num, vx_writeback_tempp.wb_pc}), - .out ({use_wb_data , vx_writeback_inter.wb_valid, vx_writeback_inter.rd, vx_writeback_inter.wb, vx_writeback_inter.wb_warp_num, vx_writeback_inter.wb_pc}) + .out ({use_wb_data , vx_writeback_if.wb_valid, vx_writeback_if.rd, vx_writeback_if.wb, vx_writeback_if.wb_warp_num, vx_writeback_if.wb_pc}) ); reg[31:0] last_data_wb /* verilator public */ ; always @(posedge clk) begin - if ((|vx_writeback_inter.wb_valid) && (vx_writeback_inter.wb != 0) && (vx_writeback_inter.rd == 28)) begin + if ((|vx_writeback_if.wb_valid) && (vx_writeback_if.wb != 0) && (vx_writeback_if.rd == 28)) begin last_data_wb <= use_wb_data[0]; end end - assign vx_writeback_inter.write_data = use_wb_data; + assign vx_writeback_if.write_data = use_wb_data; endmodule : VX_writeback diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 4ae40e97..f4ffbc61 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -99,12 +99,12 @@ module Vortex wire schedule_delay; // Dcache Interface - VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual(); + VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp(); + VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req(); + VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual(); - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req(); - VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res(); + VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res(); assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid; assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr; @@ -144,11 +144,11 @@ module Vortex assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc; assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot; - VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp(); - VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req(); + VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp(); + VX_gpu_dcache_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req(); - VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req(); - VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res(); + VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req(); + VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res(); assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid; assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr; @@ -171,19 +171,19 @@ module Vortex ///////////////////////////////////////////////////////////////////////// // Front-end to Back-end -VX_frE_to_bckE_req_inter vx_bckE_req(); // New instruction request to EXE/MEM +VX_frE_to_bckE_req_if vx_bckE_req(); // New instruction request to EXE/MEM // Back-end to Front-end -VX_wb_inter vx_writeback_inter(); // Writeback to GPRs -VX_branch_response_inter vx_branch_rsp(); // Branch Resolution to Fetch -VX_jal_response_inter vx_jal_rsp(); // Jump resolution to Fetch +VX_wb_if vx_writeback_if(); // Writeback to GPRs +VX_branch_response_if vx_branch_rsp(); // Branch Resolution to Fetch +VX_jal_response_if vx_jal_rsp(); // Jump resolution to Fetch // CSR Buses -// VX_csr_write_request_inter vx_csr_w_req(); +// VX_csr_write_request_if vx_csr_w_req(); -VX_warp_ctl_inter vx_warp_ctl(); -VX_gpu_snp_req_rsp vx_gpu_icache_snp_req(); -VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req(); +VX_warp_ctl_if vx_warp_ctl(); +VX_gpu_snp_req_rsp_if vx_gpu_icache_snp_req(); +VX_gpu_snp_req_rsp_if vx_gpu_dcache_snp_req(); assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid; assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr; @@ -209,7 +209,7 @@ VX_scheduler schedule( .exec_delay (exec_delay), .gpr_stage_delay (gpr_stage_delay), .vx_bckE_req (vx_bckE_req), - .vx_writeback_inter (vx_writeback_inter), + .vx_writeback_if (vx_writeback_if), .schedule_delay (schedule_delay), .is_empty (scheduler_empty) ); @@ -224,7 +224,7 @@ VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end( .vx_branch_rsp (vx_branch_rsp), .vx_dcache_rsp (vx_dcache_rsp), .vx_dcache_req (vx_dcache_req), - .vx_writeback_inter (vx_writeback_inter), + .vx_writeback_if (vx_writeback_if), .out_mem_delay (memory_delay), .out_exec_delay (exec_delay), .gpr_stage_delay (gpr_stage_delay) @@ -257,7 +257,7 @@ VX_dmem_controller vx_dmem_controller( // .clk (clk), // .in_decode_csr_address(decode_csr_address), // .vx_csr_w_req (vx_csr_w_req), -// .in_wb_valid (vx_writeback_inter.wb_valid[0]), +// .in_wb_valid (vx_writeback_if.wb_valid[0]), // .out_decode_csr_data (csr_decode_csr_data) // ); diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index 77f252b1..fa8d7e9a 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -227,12 +227,12 @@ module Vortex_Cluster // Core Writeback .core_wb_valid (l2c_wb), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .core_wb_req_rd (), .core_wb_req_wb (), .core_wb_warp_num (), .core_wb_pc (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END .core_wb_readdata ({l2c_wb_data}), .core_wb_address (l2c_wb_addr), diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 237e518b..b3b31f94 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -225,12 +225,12 @@ module Vortex_Socket ( // Core Writeback .core_wb_valid (l3c_wb), - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN .core_wb_req_rd (), .core_wb_req_wb (), .core_wb_warp_num (), .core_wb_pc (), - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END .core_wb_readdata ({l3c_wb_data}), .core_wb_address (l3c_wb_addr), diff --git a/hw/rtl/cache/VX_cache_data.v b/hw/rtl/cache/VX_cache_data.v index 241791d8..0cefc07f 100644 --- a/hw/rtl/cache/VX_cache_data.v +++ b/hw/rtl/cache/VX_cache_data.v @@ -104,7 +104,7 @@ module VX_cache_data #( assign data_use = data_out_d; // Using ASIC MEM - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN rf2_32x128_wm1 data ( .CENYA(), .AYA(), @@ -141,7 +141,7 @@ module VX_cache_data #( .SEB(1'b0), .COLLDISN(1'b1) ); - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END wire[16:0] old_tag; wire old_valid; @@ -169,7 +169,7 @@ module VX_cache_data #( assign valid_use = old_valid; assign tag_use = old_tag; - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN rf2_32x19_wm0 meta ( .CENYA(), .AYA(), @@ -206,7 +206,7 @@ module VX_cache_data #( .SEB(1'b0), .COLLDISN(1'b1) ); - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END `endif endmodule diff --git a/hw/rtl/cache/VX_d_cache_encapsulate.v b/hw/rtl/cache/VX_d_cache_encapsulate.v index 98ce64a4..135e4a5a 100644 --- a/hw/rtl/cache/VX_d_cache_encapsulate.v +++ b/hw/rtl/cache/VX_d_cache_encapsulate.v @@ -53,32 +53,32 @@ module VX_d_cache_encapsulate ( // Inter - wire [`NUM_THREADS-1:0] i_p_valid_inter; - wire [`NUM_THREADS-1:0][31:0] i_p_addr_inter; - wire [`NUM_THREADS-1:0][31:0] i_p_writedata_inter; + wire [`NUM_THREADS-1:0] i_p_valid_if; + wire [`NUM_THREADS-1:0][31:0] i_p_addr_if; + wire [`NUM_THREADS-1:0][31:0] i_p_writedata_if; - reg [`NUM_THREADS-1:0][31:0] o_p_readdata_inter; - reg [`NUM_THREADS-1:0] o_p_readdata_valid_inter; + reg [`NUM_THREADS-1:0][31:0] o_p_readdata_if; + reg [`NUM_THREADS-1:0] o_p_readdata_valid_if; - reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter; - wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter; + reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_if; + wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_if; genvar curr_thraed, curr_bank, curr_word; generate for (curr_thraed = 0; curr_thraed < `NUM_THREADS; curr_thraed = curr_thraed + 1) begin : threads - assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed]; - assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed]; - assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed]; - assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed]; - assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed]; + assign i_p_valid_if[curr_thraed] = i_p_valid[curr_thraed]; + assign i_p_addr_if[curr_thraed] = i_p_addr[curr_thraed]; + assign i_p_writedata_if[curr_thraed] = i_p_writedata[curr_thraed]; + assign o_p_readdata[curr_thraed] = o_p_readdata_if[curr_thraed]; + assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_if[curr_thraed]; end for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank = curr_bank + 1) begin : banks for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words - assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word]; - assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word]; + assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_if[curr_bank][curr_word]; + assign i_m_readdata_if[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word]; end end @@ -87,19 +87,19 @@ module VX_d_cache_encapsulate ( VX_d_cache dcache( .clk (clk), .rst (rst), - .i_p_valid (i_p_valid_inter), - .i_p_addr (i_p_addr_inter), + .i_p_valid (i_p_valid_if), + .i_p_addr (i_p_addr_if), .i_p_initial_request(i_p_initial_request), - .i_p_writedata (i_p_writedata_inter), + .i_p_writedata (i_p_writedata_if), .i_p_read_or_write (i_p_read_or_write), - .o_p_readdata (o_p_readdata_inter), - .o_p_readdata_valid (o_p_readdata_valid_inter), + .o_p_readdata (o_p_readdata_if), + .o_p_readdata_valid (o_p_readdata_valid_if), .o_p_waitrequest (o_p_waitrequest), .o_m_addr (o_m_addr), .o_m_valid (o_m_valid), - .o_m_writedata (o_m_writedata_inter), + .o_m_writedata (o_m_writedata_if), .o_m_read_or_write (o_m_read_or_write), - .i_m_readdata (i_m_readdata_inter), + .i_m_readdata (i_m_readdata_if), .i_m_ready (i_m_ready) ); diff --git a/hw/rtl/compat/VX_divide.v b/hw/rtl/compat/VX_divide.v index 65b1ab8f..9ce4af98 100644 --- a/hw/rtl/compat/VX_divide.v +++ b/hw/rtl/compat/VX_divide.v @@ -25,9 +25,9 @@ module VX_divide #( generate if (NREP != DREP) begin - /* verilator lint_off DECLFILENAME */ + `IGNORE_WARNINGS_BEGIN different_nrep_drep_not_yet_supported non_existing_module(); - /* verilator lint_on DECLFILENAME */ + `IGNORE_WARNINGS_END end if (IMPL == "quartus") begin @@ -98,7 +98,7 @@ module VX_divide #( if (NREP == "SIGNED") begin - /*VX_divide_internal_signed #( + /*VX_divide_ifnal_signed #( .WIDTHN, .WIDTHD )div( diff --git a/hw/rtl/compat/VX_mult.v b/hw/rtl/compat/VX_mult.v index 720da1b1..b6004141 100644 --- a/hw/rtl/compat/VX_mult.v +++ b/hw/rtl/compat/VX_mult.v @@ -30,7 +30,7 @@ module VX_mult #( localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5; if (FORCE_LE == "YES") begin - /* verilator lint_off DECLFILENAME */ + `IGNORE_WARNINGS_BEGIN lpm_mult #( .LPM_WIDTHA(WIDTHA), .LPM_WIDTHB(WIDTHB), @@ -47,7 +47,7 @@ module VX_mult #( .datab(datab), .result(result) ); - /* verilator lint_on DECLFILENAME */ + `IGNORE_WARNINGS_END end else begin lpm_mult#( diff --git a/hw/rtl/interfaces/VX_branch_response_inter.v b/hw/rtl/interfaces/VX_branch_response_if.v similarity index 85% rename from hw/rtl/interfaces/VX_branch_response_inter.v rename to hw/rtl/interfaces/VX_branch_response_if.v index 01bec227..4a1617cd 100644 --- a/hw/rtl/interfaces/VX_branch_response_inter.v +++ b/hw/rtl/interfaces/VX_branch_response_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_branch_response_inter (); +interface VX_branch_response_if (); wire valid_branch; wire branch_dir; diff --git a/hw/rtl/interfaces/VX_csr_req_inter.v b/hw/rtl/interfaces/VX_csr_req_if.v similarity index 91% rename from hw/rtl/interfaces/VX_csr_req_inter.v rename to hw/rtl/interfaces/VX_csr_req_if.v index bf9fbe72..162c8937 100644 --- a/hw/rtl/interfaces/VX_csr_req_inter.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_csr_req_inter (); +interface VX_csr_req_if (); wire [`NUM_THREADS-1:0] valid; wire [`NW_BITS-1:0] warp_num; diff --git a/hw/rtl/interfaces/VX_csr_wb_inter.v b/hw/rtl/interfaces/VX_csr_wb_if.v similarity index 90% rename from hw/rtl/interfaces/VX_csr_wb_inter.v rename to hw/rtl/interfaces/VX_csr_wb_if.v index c33c6c2d..45df13d0 100644 --- a/hw/rtl/interfaces/VX_csr_wb_inter.v +++ b/hw/rtl/interfaces/VX_csr_wb_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_csr_wb_inter (); +interface VX_csr_wb_if (); wire [`NUM_THREADS-1:0] valid; wire [`NW_BITS-1:0] warp_num; diff --git a/hw/rtl/interfaces/VX_dcache_request_inter.v b/hw/rtl/interfaces/VX_dcache_request_if.v similarity index 91% rename from hw/rtl/interfaces/VX_dcache_request_inter.v rename to hw/rtl/interfaces/VX_dcache_request_if.v index 64f8bca2..e61ac455 100644 --- a/hw/rtl/interfaces/VX_dcache_request_inter.v +++ b/hw/rtl/interfaces/VX_dcache_request_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_dcache_request_inter (); +interface VX_dcache_request_if (); wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address; wire [2:0] out_cache_driver_in_mem_read; diff --git a/hw/rtl/interfaces/VX_dcache_response_inter.v b/hw/rtl/interfaces/VX_dcache_response_if.v similarity index 82% rename from hw/rtl/interfaces/VX_dcache_response_inter.v rename to hw/rtl/interfaces/VX_dcache_response_if.v index b849786c..280631bb 100644 --- a/hw/rtl/interfaces/VX_dcache_response_inter.v +++ b/hw/rtl/interfaces/VX_dcache_response_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_dcache_response_inter (); +interface VX_dcache_response_if (); wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data; wire delay; diff --git a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v b/hw/rtl/interfaces/VX_dram_req_rsp_if.v similarity index 92% rename from hw/rtl/interfaces/VX_dram_req_rsp_inter.v rename to hw/rtl/interfaces/VX_dram_req_rsp_if.v index 1edc3b3d..08c803d5 100644 --- a/hw/rtl/interfaces/VX_dram_req_rsp_inter.v +++ b/hw/rtl/interfaces/VX_dram_req_rsp_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_dram_req_rsp_inter #( +interface VX_dram_req_rsp_if #( parameter NUM_BANKS = 8, parameter NUM_WORDS_PER_BLOCK = 4 ) (); diff --git a/hw/rtl/interfaces/VX_exec_unit_req_inter.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v similarity index 96% rename from hw/rtl/interfaces/VX_exec_unit_req_inter.v rename to hw/rtl/interfaces/VX_exec_unit_req_if.v index 62a79efc..f588e41c 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_inter.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_exec_unit_req_inter (); +interface VX_exec_unit_req_if (); // Meta wire [`NUM_THREADS-1:0] valid; diff --git a/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v b/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v similarity index 96% rename from hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v rename to hw/rtl/interfaces/VX_frE_to_bckE_req_if.v index 919e9320..db58eac6 100644 --- a/hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v +++ b/hw/rtl/interfaces/VX_frE_to_bckE_req_if.v @@ -3,7 +3,7 @@ `include "VX_define.vh" -interface VX_frE_to_bckE_req_inter (); +interface VX_frE_to_bckE_req_if (); wire [11:0] csr_address; wire is_csr; diff --git a/hw/rtl/interfaces/VX_gpr_data_inter.v b/hw/rtl/interfaces/VX_gpr_data_if.v similarity index 85% rename from hw/rtl/interfaces/VX_gpr_data_inter.v rename to hw/rtl/interfaces/VX_gpr_data_if.v index 7987ecda..622f54a5 100644 --- a/hw/rtl/interfaces/VX_gpr_data_inter.v +++ b/hw/rtl/interfaces/VX_gpr_data_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_gpr_data_inter (); +interface VX_gpr_data_if (); wire [`NUM_THREADS-1:0][31:0] a_reg_data; wire [`NUM_THREADS-1:0][31:0] b_reg_data; diff --git a/hw/rtl/interfaces/VX_gpr_jal_inter.v b/hw/rtl/interfaces/VX_gpr_jal_if.v similarity index 82% rename from hw/rtl/interfaces/VX_gpr_jal_inter.v rename to hw/rtl/interfaces/VX_gpr_jal_if.v index 09efe383..17f68359 100644 --- a/hw/rtl/interfaces/VX_gpr_jal_inter.v +++ b/hw/rtl/interfaces/VX_gpr_jal_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_gpr_jal_inter (); +interface VX_gpr_jal_if (); wire is_jal; wire[31:0] curr_PC; diff --git a/hw/rtl/interfaces/VX_gpr_read_inter.v b/hw/rtl/interfaces/VX_gpr_read_if.v similarity index 84% rename from hw/rtl/interfaces/VX_gpr_read_inter.v rename to hw/rtl/interfaces/VX_gpr_read_if.v index 33d3abae..c5796c45 100644 --- a/hw/rtl/interfaces/VX_gpr_read_inter.v +++ b/hw/rtl/interfaces/VX_gpr_read_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_gpr_read_inter (); +interface VX_gpr_read_if (); wire [4:0] rs1; wire [4:0] rs2; diff --git a/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v similarity index 92% rename from hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v index 06299c95..07cac070 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_dram_req_inter #( +interface VX_gpu_dcache_dram_req_if #( parameter BANK_LINE_WORDS = 2 ) (); diff --git a/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v similarity index 89% rename from hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v index e7e270ea..5ef78c62 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_dram_rsp_inter #( +interface VX_gpu_dcache_dram_rsp_if #( parameter BANK_LINE_WORDS = 2 ) (); // DRAM Response diff --git a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_req_if.v similarity index 95% rename from hw/rtl/interfaces/VX_gpu_dcache_req_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_req_if.v index c70165e1..98521ab6 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_req_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_req_inter #( +interface VX_gpu_dcache_req_if #( parameter NUM_REQUESTS = 32 ) (); diff --git a/hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v similarity index 94% rename from hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v index 2b6f1641..80383ce2 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_rsp_inter #( +interface VX_gpu_dcache_rsp_if #( parameter NUM_REQUESTS = 32 ) (); diff --git a/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v b/hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v similarity index 82% rename from hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v rename to hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v index 254c652a..c4be1cb3 100644 --- a/hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_dcache_snp_req_inter (); +interface VX_gpu_dcache_snp_req_if (); // Snoop Req wire snp_req_valid; wire [31:0] snp_req_addr; diff --git a/hw/rtl/interfaces/VX_gpu_inst_req_inter.v b/hw/rtl/interfaces/VX_gpu_inst_req_if.v similarity index 92% rename from hw/rtl/interfaces/VX_gpu_inst_req_inter.v rename to hw/rtl/interfaces/VX_gpu_inst_req_if.v index 5a01813d..a394b12d 100644 --- a/hw/rtl/interfaces/VX_gpu_inst_req_inter.v +++ b/hw/rtl/interfaces/VX_gpu_inst_req_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_gpu_inst_req_inter(); +interface VX_gpu_inst_req_if(); wire [`NUM_THREADS-1:0] valid; wire [`NW_BITS-1:0] warp_num; diff --git a/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v b/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v similarity index 87% rename from hw/rtl/interfaces/VX_gpu_snp_req_rsp.v rename to hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v index 0b25c32b..ce6c1923 100644 --- a/hw/rtl/interfaces/VX_gpu_snp_req_rsp.v +++ b/hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v @@ -3,7 +3,7 @@ `include "../generic_cache/VX_cache_config.vh" -interface VX_gpu_snp_req_rsp (); +interface VX_gpu_snp_req_rsp_if (); // Snoop request wire snp_req_valid; diff --git a/hw/rtl/interfaces/VX_icache_request_inter.v b/hw/rtl/interfaces/VX_icache_request_if.v similarity index 88% rename from hw/rtl/interfaces/VX_icache_request_inter.v rename to hw/rtl/interfaces/VX_icache_request_if.v index 116ba841..6d02f106 100644 --- a/hw/rtl/interfaces/VX_icache_request_inter.v +++ b/hw/rtl/interfaces/VX_icache_request_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_icache_request_inter (); +interface VX_icache_request_if (); wire [31:0] pc_address; wire [2:0] out_cache_driver_in_mem_read; diff --git a/hw/rtl/interfaces/VX_icache_response_inter.v b/hw/rtl/interfaces/VX_icache_response_if.v similarity index 81% rename from hw/rtl/interfaces/VX_icache_response_inter.v rename to hw/rtl/interfaces/VX_icache_response_if.v index 0660428f..d73775e4 100644 --- a/hw/rtl/interfaces/VX_icache_response_inter.v +++ b/hw/rtl/interfaces/VX_icache_response_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_icache_response_inter (); +interface VX_icache_response_if (); // wire ready; // wire stall; diff --git a/hw/rtl/interfaces/VX_inst_exec_wb_inter.v b/hw/rtl/interfaces/VX_inst_exec_wb_if.v similarity index 90% rename from hw/rtl/interfaces/VX_inst_exec_wb_inter.v rename to hw/rtl/interfaces/VX_inst_exec_wb_if.v index a3ffa03b..47581879 100644 --- a/hw/rtl/interfaces/VX_inst_exec_wb_inter.v +++ b/hw/rtl/interfaces/VX_inst_exec_wb_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_inst_exec_wb_inter (); +interface VX_inst_exec_wb_if (); wire [`NUM_THREADS-1:0][31:0] alu_result; wire [31:0] exec_wb_pc; diff --git a/hw/rtl/interfaces/VX_inst_mem_wb_inter.v b/hw/rtl/interfaces/VX_inst_mem_wb_if.v similarity index 90% rename from hw/rtl/interfaces/VX_inst_mem_wb_inter.v rename to hw/rtl/interfaces/VX_inst_mem_wb_if.v index a5b47e9e..ed30b3cf 100644 --- a/hw/rtl/interfaces/VX_inst_mem_wb_inter.v +++ b/hw/rtl/interfaces/VX_inst_mem_wb_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_inst_mem_wb_inter (); +interface VX_inst_mem_wb_if (); wire [`NUM_THREADS-1:0][31:0] loaded_data; wire [31:0] mem_wb_pc; diff --git a/hw/rtl/interfaces/VX_inst_meta_inter.v b/hw/rtl/interfaces/VX_inst_meta_if.v similarity index 87% rename from hw/rtl/interfaces/VX_inst_meta_inter.v rename to hw/rtl/interfaces/VX_inst_meta_if.v index 9dbfc368..f925a3be 100644 --- a/hw/rtl/interfaces/VX_inst_meta_inter.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_inst_meta_inter (); +interface VX_inst_meta_if (); wire [31:0] instruction; wire [31:0] inst_pc; diff --git a/hw/rtl/interfaces/VX_jal_response_inter.v b/hw/rtl/interfaces/VX_jal_response_if.v similarity index 83% rename from hw/rtl/interfaces/VX_jal_response_inter.v rename to hw/rtl/interfaces/VX_jal_response_if.v index 85784b17..fde25f7a 100644 --- a/hw/rtl/interfaces/VX_jal_response_inter.v +++ b/hw/rtl/interfaces/VX_jal_response_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_jal_response_inter (); +interface VX_jal_response_if (); wire jal; wire [31:0] jal_dest; diff --git a/hw/rtl/interfaces/VX_join_inter.v b/hw/rtl/interfaces/VX_join_if.v similarity index 85% rename from hw/rtl/interfaces/VX_join_inter.v rename to hw/rtl/interfaces/VX_join_if.v index 98ff29e7..fa712bd1 100644 --- a/hw/rtl/interfaces/VX_join_inter.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_join_inter (); +interface VX_join_if (); wire is_join; wire [`NW_BITS-1:0] join_warp_num; diff --git a/hw/rtl/interfaces/VX_lsu_req_inter.v b/hw/rtl/interfaces/VX_lsu_req_if.v similarity index 94% rename from hw/rtl/interfaces/VX_lsu_req_inter.v rename to hw/rtl/interfaces/VX_lsu_req_if.v index 75c9682f..9db222ad 100644 --- a/hw/rtl/interfaces/VX_lsu_req_inter.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_lsu_req_inter (); +interface VX_lsu_req_if (); wire [`NUM_THREADS-1:0] valid; wire [31:0] lsu_pc; diff --git a/hw/rtl/interfaces/VX_mem_req_inter.v b/hw/rtl/interfaces/VX_mem_req_if.v similarity index 95% rename from hw/rtl/interfaces/VX_mem_req_inter.v rename to hw/rtl/interfaces/VX_mem_req_if.v index 0f0920cd..5c6afa4b 100644 --- a/hw/rtl/interfaces/VX_mem_req_inter.v +++ b/hw/rtl/interfaces/VX_mem_req_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_mem_req_inter (); +interface VX_mem_req_if (); wire [`NUM_THREADS-1:0][31:0] alu_result; wire [2:0] mem_read; diff --git a/hw/rtl/interfaces/VX_mw_wb_inter.v b/hw/rtl/interfaces/VX_mw_wb_if.v similarity index 92% rename from hw/rtl/interfaces/VX_mw_wb_inter.v rename to hw/rtl/interfaces/VX_mw_wb_if.v index a9bfeada..a0d3f5ea 100644 --- a/hw/rtl/interfaces/VX_mw_wb_inter.v +++ b/hw/rtl/interfaces/VX_mw_wb_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_mw_wb_inter (); +interface VX_mw_wb_if (); wire [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] mem_result; diff --git a/hw/rtl/interfaces/VX_warp_ctl_inter.v b/hw/rtl/interfaces/VX_warp_ctl_if.v similarity index 95% rename from hw/rtl/interfaces/VX_warp_ctl_inter.v rename to hw/rtl/interfaces/VX_warp_ctl_if.v index f0453463..254e0a90 100644 --- a/hw/rtl/interfaces/VX_warp_ctl_inter.v +++ b/hw/rtl/interfaces/VX_warp_ctl_if.v @@ -4,7 +4,7 @@ `include "../VX_define.vh" -interface VX_warp_ctl_inter (); +interface VX_warp_ctl_if (); wire [`NW_BITS-1:0] warp_num; wire change_mask; diff --git a/hw/rtl/interfaces/VX_wb_inter.v b/hw/rtl/interfaces/VX_wb_if.v similarity index 92% rename from hw/rtl/interfaces/VX_wb_inter.v rename to hw/rtl/interfaces/VX_wb_if.v index 4a7f64ab..a87ee192 100644 --- a/hw/rtl/interfaces/VX_wb_inter.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_wb_inter (); +interface VX_wb_if (); wire [`NUM_THREADS-1:0][31:0] write_data; wire [31:0] wb_pc; diff --git a/hw/rtl/interfaces/VX_wstall_inter.v b/hw/rtl/interfaces/VX_wstall_if.v similarity index 84% rename from hw/rtl/interfaces/VX_wstall_inter.v rename to hw/rtl/interfaces/VX_wstall_if.v index be215d65..b981cd91 100644 --- a/hw/rtl/interfaces/VX_wstall_inter.v +++ b/hw/rtl/interfaces/VX_wstall_if.v @@ -3,7 +3,7 @@ `include "../VX_define.vh" -interface VX_wstall_inter(); +interface VX_wstall_if(); wire wstall; wire [`NW_BITS-1:0] warp_num; diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 8be24a3b..ea6440fc 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -5,8 +5,8 @@ module VX_d_e_reg ( input wire reset, input wire in_branch_stall, input wire in_freeze, - VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, - VX_frE_to_bckE_req_inter vx_bckE_req + VX_frE_to_bckE_req_if vx_frE_to_bckE_req, + VX_frE_to_bckE_req_if vx_bckE_req ); wire stall = in_freeze; diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index 99cc82c2..83505199 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -5,8 +5,8 @@ module VX_f_d_reg ( input wire reset, input wire in_freeze, - VX_inst_meta_inter fe_inst_meta_fd, - VX_inst_meta_inter fd_inst_meta_de + VX_inst_meta_if fe_inst_meta_fd, + VX_inst_meta_if fd_inst_meta_de ); diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index 10841c57..b1c31324 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -5,8 +5,8 @@ module VX_i_d_reg ( input wire reset, input wire in_freeze, - VX_inst_meta_inter fe_inst_meta_fd, - VX_inst_meta_inter fd_inst_meta_de + VX_inst_meta_if fe_inst_meta_fd, + VX_inst_meta_if fd_inst_meta_de ); diff --git a/hw/rtl/shared_memory/VX_shared_memory_block.v b/hw/rtl/shared_memory/VX_shared_memory_block.v index c879176c..8410c6b2 100644 --- a/hw/rtl/shared_memory/VX_shared_memory_block.v +++ b/hw/rtl/shared_memory/VX_shared_memory_block.v @@ -61,7 +61,7 @@ module VX_shared_memory_block end // Using ASIC MEM - /* verilator lint_off PINCONNECTEMPTY */ + `IGNORE_WARNINGS_BEGIN rf2_128x128_wm1 first_ram ( .CENYA(), .AYA(), @@ -98,7 +98,7 @@ module VX_shared_memory_block .SEB(1'b0), .COLLDISN(1'b1) ); - /* verilator lint_on PINCONNECTEMPTY */ + `IGNORE_WARNINGS_END `endif diff --git a/simX/cache_simX.v b/simX/cache_simX.v index 2183864b..72059baf 100644 --- a/simX/cache_simX.v +++ b/simX/cache_simX.v @@ -25,7 +25,7 @@ module cache_simX ( //////////////////// ICACHE /////////////////// - VX_icache_request_inter VX_icache_req; + VX_icache_request_if VX_icache_req; assign VX_icache_req.pc_address = in_icache_pc_addr; assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE; @@ -33,11 +33,11 @@ module cache_simX ( assign VX_icache_req.out_cache_driver_in_data = 0; - VX_icache_response_inter VX_icache_rsp; + VX_icache_response_if VX_icache_rsp; assign out_icache_stall = VX_icache_rsp.delay; - VX_dram_req_rsp_inter #( + VX_dram_req_rsp_if #( .NUMBER_BANKS(`ICACHE_BANKS), .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK) @@ -52,7 +52,7 @@ module cache_simX ( //////////////////// DCACHE /////////////////// - VX_dcache_request_inter VX_dcache_req; + VX_dcache_request_if VX_dcache_req; assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read; assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write; assign VX_dcache_req.out_cache_driver_in_data = 0; @@ -64,11 +64,11 @@ module cache_simX ( assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t]; end - VX_dcache_response_inter VX_dcache_rsp; + VX_dcache_response_if VX_dcache_rsp; assign out_dcache_stall = VX_dcache_rsp.delay; - VX_dram_req_rsp_inter #( + VX_dram_req_rsp_if #( .NUMBER_BANKS(`DCACHE_BANKS), .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)