diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v
index 542da266..342e1707 100644
--- a/rtl/cache/VX_cache_data.v
+++ b/rtl/cache/VX_cache_data.v
@@ -116,7 +116,7 @@ module VX_cache_data
 
         // Using ASIC MEM
         /* verilator lint_off PINCONNECTEMPTY */
-       rf2_256x128_wm1 data (
+       rf2_32x128_wm1 data (
              .CENYA(),
              .AYA(),
              .CENYB(),
diff --git a/rtl/modelsim/vortex_tb.v b/rtl/modelsim/vortex_tb.v
index b099a238..7bb7a774 100644
--- a/rtl/modelsim/vortex_tb.v
+++ b/rtl/modelsim/vortex_tb.v
@@ -87,7 +87,7 @@ reg         out_ebreak;
 
 	initial begin
 		// $fdumpfile("vortex1.vcd");
-		load_file("../../runtime/mains/dev/vx_dev_main.hex");
+		load_file("../../runtime/mains/simple/vx_simple_main.hex");
 		//load_file("../../kernel/vortex_test.hex");
 		$dumpvars(0, vortex_tb);
 		reset = 1;