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clean up 'stage_1_cycles' from cache

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Blaise Tine
2020-09-01 03:39:03 -07:00
parent 0a45a8beb3
commit 31ffbe0d6a
7 changed files with 167 additions and 271 deletions
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25
hw/rtl/VX_config.vh
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@@ -193,11 +193,6 @@
`define DWORD_SIZE 4
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef DSTAGE_1_CYCLES
`define DSTAGE_1_CYCLES 1
`endif
// Core Request Queue Size
`ifndef DCREQ_SIZE
`define DCREQ_SIZE `NUM_WARPS
@@ -264,11 +259,6 @@
`define IWORD_SIZE 4
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef ISTAGE_1_CYCLES
`define ISTAGE_1_CYCLES 1
`endif
// Core Request Queue Size
`ifndef ICREQ_SIZE
`define ICREQ_SIZE `NUM_WARPS
@@ -330,11 +320,6 @@
`define SWORD_SIZE 4
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef SSTAGE_1_CYCLES
`define SSTAGE_1_CYCLES 1
`endif
// Core Request Queue Size
`ifndef SCREQ_SIZE
`define SCREQ_SIZE `NUM_WARPS
@@ -367,11 +352,6 @@
`define L2WORD_SIZE `L2BANK_LINE_SIZE
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef L2STAGE_1_CYCLES
`define L2STAGE_1_CYCLES 1
`endif
// Core Request Queue Size
`ifndef L2CREQ_SIZE
`define L2CREQ_SIZE 8
@@ -438,11 +418,6 @@
`define L3WORD_SIZE `L3BANK_LINE_SIZE
`endif
// Number of cycles to complete stage 1 (read from memory)
`ifndef L3STAGE_1_CYCLES
`define L3STAGE_1_CYCLES 1
`endif
// Core Request Queue Size
`ifndef L3CREQ_SIZE
`define L3CREQ_SIZE 8