wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

riscv-tests work on simx

Browse Source
This commit is contained in:
Santosh Raghav Srivatsan
2021-12-01 19:41:16 -05:00
parent f0dc04ad04
commit 3784da0d2f
108 changed files with 23 additions and 68420 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
sim/simX/decode.cpp
View File

@@ -49,7 +49,7 @@ static const char* op_string(const Instr &instr) {
HalfWord func3 = instr.getFunc3();
HalfWord func7 = instr.getFunc7();
HalfWord rs2 = instr.getRSrc(1);
HalfWord imm = instr.getImm();
Word imm = instr.getImm();
switch (instr.getOpcode()) {
case Opcode::NOP: return "NOP";
case Opcode::LUI_INST: return "LUI";
@@ -394,7 +394,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
instr->setSrcReg(rs2);
}
instr->setFunc3(func3);
HalfWord imeed = (func7 << reg_s_) | rd;
Word imeed = (func7 << reg_s_) | rd;
instr->setImm(signExt(imeed, 12, s_imm_mask_));
} break;
@@ -406,7 +406,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
HalfWord bits_4_1 = rd >> 1;
HalfWord bit_10_5 = func7 & 0x3f;
HalfWord bit_12 = func7 >> 6;
HalfWord imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
Word imeed = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
instr->setImm(signExt(imeed, 13, b_imm_mask_));
} break;
@@ -422,7 +422,7 @@ std::shared_ptr<Instr> Decoder::decode(HalfWord code, HalfWord PC) {
HalfWord bit_11 = (unordered >> 8) & 0x1;
HalfWord bits_10_1 = (unordered >> 9) & 0x3ff;
HalfWord bit_20 = (unordered >> 19) & 0x1;
HalfWord imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
if (bit_20) {
imeed |= ~j_imm_mask_;
}

7
sim/simX/execute.cpp
View File

@@ -106,7 +106,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
case NOP:
break;
case LUI_INST:
rddata = (immsrc << 12) & 0xfffff000;
rddata = signExt(((immsrc << 12) & 0xfffff000), 32, 0xFFFFFFFF);
rd_write = true;
break;
case AUIPC_INST:
@@ -205,7 +205,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
rddata = rsdata[0] - rsdata[1];
} else {
// RV32I: ADD
rddata = rsdata[0] + rsdata[1];
rddata = WordI(rsdata[0]) + WordI(rsdata[1]);//(WordI(rsdata[0]) > 0) && (WordI(rsdata[1]) > 0)? ((rsdata[0] + rsdata[1]) & 0xFFFFFFFF) :
}
break;
case 1:
@@ -253,7 +253,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
switch (func3) {
case 0:
// RV32I: ADDI
rddata = rsdata[0] + immsrc;
rddata = WordI(rsdata[0]) + WordI(immsrc);
break;
case 1:
// RV64I: SLLI
@@ -456,7 +456,6 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
case 0:
// RV64I: ADDIW
rddata = signExt((HalfWord)rsdata[0] + (HalfWord)immsrc, 32, 0xFFFFFFFF);
printf("rddata\n");
break;
case 1:
// RV64I: SLLIW

6
sim/simX/instr.h
View File

@@ -75,7 +75,7 @@ public:
void setSrcVReg(int srcReg) { rsrc_type_[num_rsrcs_] = 3; rsrc_[num_rsrcs_++] = srcReg; }
void setFunc3(HalfWord func3) { func3_ = func3; }
void setFunc7(HalfWord func7) { func7_ = func7; }
void setImm(HalfWord imm) { has_imm_ = true; imm_ = imm; }
void setImm(Word imm) { has_imm_ = true; imm_ = imm; }
void setVlsWidth(HalfWord width) { vlsWidth_ = width; }
void setVmop(HalfWord mop) { vMop_ = mop; }
void setVnf(HalfWord nf) { vNf_ = nf; }
@@ -97,7 +97,7 @@ public:
int getRDest() const { return rdest_; }
int getRDType() const { return rdest_type_; }
bool hasImm() const { return has_imm_; }
HalfWord getImm() const { return imm_; }
Word getImm() const { return imm_; }
HalfWord getVlsWidth() const { return vlsWidth_; }
HalfWord getVmop() const { return vMop_; }
HalfWord getvNf() const { return vNf_; }
@@ -120,7 +120,7 @@ private:
int isrc_mask_;
int fsrc_mask_;
int vsrc_mask_;
HalfWord imm_;
Word imm_;
int rsrc_type_[MAX_REG_SOURCES];
int rsrc_[MAX_REG_SOURCES];
int rdest_;