diff --git a/hw/rtl/Makefile b/hw/Makefile similarity index 100% rename from hw/rtl/Makefile rename to hw/Makefile diff --git a/hw/old_rtl/modelsim/Makefile b/hw/old_rtl/modelsim/Makefile deleted file mode 100644 index 7a3a4efd..00000000 --- a/hw/old_rtl/modelsim/Makefile +++ /dev/null @@ -1,124 +0,0 @@ - - -ALL:sim - -#TOOL INPUT -SRC = \ - vortex_dpi.cpp \ - vortex_tb.v \ -../VX_define.v \ -../VX_define_synth.v \ -../interfaces/VX_branch_response_inter.v \ -../interfaces/VX_csr_req_inter.v \ -../interfaces/VX_csr_wb_inter.v \ -../interfaces/VX_dcache_request_inter.v \ -../interfaces/VX_dcache_response_inter.v \ -../interfaces/VX_dram_req_rsp_inter.v \ -../interfaces/VX_exec_unit_req_inter.v \ -../interfaces/VX_frE_to_bckE_req_inter.v \ -../interfaces/VX_gpr_clone_inter.v \ -../interfaces/VX_gpr_data_inter.v \ -../interfaces/VX_gpr_jal_inter.v \ -../interfaces/VX_gpr_read_inter.v \ -../interfaces/VX_gpr_wspawn_inter.v \ -../interfaces/VX_gpu_inst_req_inter.v \ -../interfaces/VX_icache_request_inter.v \ -../interfaces/VX_icache_response_inter.v \ -../interfaces/VX_inst_exec_wb_inter.v \ -../interfaces/VX_inst_mem_wb_inter.v \ -../interfaces/VX_inst_meta_inter.v \ -../interfaces/VX_jal_response_inter.v \ -../interfaces/VX_join_inter.v \ -../interfaces/VX_lsu_req_inter.v \ -../interfaces/VX_mem_req_inter.v \ -../interfaces/VX_mw_wb_inter.v \ -../interfaces/VX_warp_ctl_inter.v \ -../interfaces/VX_wb_inter.v \ -../interfaces/VX_wstall_inter.v \ -../VX_alu.v \ -../VX_back_end.v \ -../VX_csr_handler.v \ -../VX_csr_wrapper.v \ -../VX_decode.v \ -../VX_dmem_controller.v \ -../VX_execute_unit.v \ -../VX_fetch.v \ -../VX_front_end.v \ -../VX_generic_priority_encoder.v \ -../VX_generic_register.v \ -../VX_generic_stack.v \ -../VX_gpgpu_inst.v \ -../VX_gpr.v \ -../VX_gpr_stage.v \ -../VX_gpr_wrapper.v \ -../VX_inst_multiplex.v \ -../VX_lsu.v \ -../VX_lsu_addr_gen.v \ -../VX_priority_encoder.v \ -../VX_priority_encoder_w_mask.v \ -../VX_scheduler.v \ -../VX_warp.v \ -../VX_countones.v \ -../VX_warp_scheduler.v \ -../VX_writeback.v \ -../Vortex.v \ -../byte_enabled_simple_dual_port_ram.v \ -../cache/VX_Cache_Bank.v \ -../cache/VX_cache_bank_valid.v \ -../cache/VX_cache_data.v \ -../cache/VX_d_cache.v \ -../cache/VX_generic_pe.v \ -../cache/cache_set.v \ -../cache/VX_cache_data_per_index.v \ -../pipe_regs/VX_d_e_reg.v \ -../pipe_regs/VX_f_d_reg.v \ -../shared_memory/VX_bank_valids.v \ -../shared_memory/VX_priority_encoder_sm.v \ -../shared_memory/VX_shared_memory.v \ -../shared_memory/VX_shared_memory_block.v \ -../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ -../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ -../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ -../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \ -../../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v - -# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v - -# vortex_dpi.h - - -CMD= \ --do "VoptFlow = 0; \ - vcd file vortex.vcd; \ - vcd add -r /vortex_tb/*; \ - vcd add -r /vortex/*; \ - run -all; \ - quit -f" - - -OPT=-sv -sv12compat - -LIB = vortex_lib - -# LOG=-logfile vortex_tb.log -LOG= - -# setup: source cshrc.modelsim -# vlib - -lib: - vlib vortex_lib - -comp: - vlog $(OPT) -work $(LIB) $(SRC) - # vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC) - - -sim: comp - # vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log - vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log - - - - - diff --git a/hw/old_rtl/modelsim/cshrc.modelsim b/hw/old_rtl/modelsim/cshrc.modelsim deleted file mode 100644 index 8f9133d7..00000000 --- a/hw/old_rtl/modelsim/cshrc.modelsim +++ /dev/null @@ -1,8 +0,0 @@ - setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin" - setenv MTI_VCO_MODE 1 -if (${?LM_LICENSE_FILE}) then - setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}" - else - setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu" -endif -setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu \ No newline at end of file diff --git a/hw/old_rtl/modelsim/modelsim.mpf b/hw/old_rtl/modelsim/modelsim.mpf deleted file mode 100644 index b1898d0c..00000000 --- a/hw/old_rtl/modelsim/modelsim.mpf +++ /dev/null @@ -1,2275 +0,0 @@ -; vsim modelsim.ini file, version 10.4 -[Version] -INIVersion = "10.6a" - -; Copyright 1991-2017 Mentor Graphics Corporation -; -; All Rights Reserved. -; -; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. -; - -[Library] -std = $MODEL_TECH/../std -ieee = $MODEL_TECH/../ieee -vital2000 = $MODEL_TECH/../vital2000 -; -; VITAL concerns: -; -; The library ieee contains (among other packages) the packages of the -; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use -; the physical library ieee (recommended), or use the physical library -; vital2000, but not both. The design can use logical library ieee and/or -; vital2000 as long as each of these maps to the same physical library, either -; ieee or vital2000. -; -; A design using the 1995 version of the VITAL packages, whether or not -; it also uses the 2000 version of the VITAL packages, must have logical library -; name ieee mapped to physical library vital1995. (A design cannot use library -; vital1995 directly because some packages in this library use logical name ieee -; when referring to the other packages in the library.) The design source -; should use logical name ieee when referring to any packages there except the -; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical -; name vital2000 (mapped to physical library vital2000) to refer to those -; packages. -; ieee = $MODEL_TECH/../vital1995 -; -; For compatiblity with previous releases, logical library name vital2000 maps -; to library vital2000 (a different library than library ieee, containing the -; same packages). -; A design should not reference VITAL from both the ieee library and the -; vital2000 library because the vital packages are effectively different. -; A design that references both the ieee and vital2000 libraries must have -; both logical names ieee and vital2000 mapped to the same library, either of -; these: -; $MODEL_TECH/../ieee -; $MODEL_TECH/../vital2000 -; -verilog = $MODEL_TECH/../verilog -std_developerskit = $MODEL_TECH/../std_developerskit -synopsys = $MODEL_TECH/../synopsys -modelsim_lib = $MODEL_TECH/../modelsim_lib -sv_std = $MODEL_TECH/../sv_std -mtiAvm = $MODEL_TECH/../avm -mtiRnm = $MODEL_TECH/../rnm -mtiOvm = $MODEL_TECH/../ovm-2.1.2 -mtiUvm = $MODEL_TECH/../uvm-1.1d -mtiUPF = $MODEL_TECH/../upf_lib -mtiPA = $MODEL_TECH/../pa_lib -floatfixlib = $MODEL_TECH/../floatfixlib -mc2_lib = $MODEL_TECH/../mc2_lib -osvvm = $MODEL_TECH/../osvvm - -; added mapping for ADMS -mgc_ams = $MODEL_TECH/../mgc_ams -ieee_env = $MODEL_TECH/../ieee_env - -;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release -;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release -;mvc_lib = $MODEL_TECH/../mvc_lib -infact = $MODEL_TECH/../infact -vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib - -; Automatically perform logical->physical mapping for physical libraries that -; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). -; The tail of the filesystem path name is chosen as the logical library name. -; For example, in the command “vopt -L ./path/to/lib1 –o opttop top”, -; vopt automatically performs the mapping “lib1 -> ./path/to/lib1”. -; See the User Manual for more details. -; -; AutoLibMapping = 0 - -work = work -[DefineOptionset] -; Define optionset entries for the various compilers, vmake, and vsim. -; These option sets can be used with the "-optionset " syntax. -; i.e. -; vlog -optionset COMPILEDEBUG top.sv -; vsim -optionset UVMDEBUG my_top -; -; Following are some useful examples. - -; define a vsim optionset for uvm debugging -UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop - -; define a vopt optionset for debugging -VOPTDEBUG = +acc -debugdb - - -[vcom] -; VHDL93 variable selects language version as the default. -; Default is VHDL-2002. -; Value of 0 or 1987 for VHDL-1987. -; Value of 1 or 1993 for VHDL-1993. -; Default or value of 2 or 2002 for VHDL-2002. -; Value of 3 or 2008 for VHDL-2008 -; Value of 4 or ams99 for VHDL-AMS-1999 -; Value of 5 or ams07 for VHDL-AMS-2007 -VHDL93 = 2002 - -; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. -; ignoreStandardRealVector = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn off unbound-component warnings. Default is on. -; Show_Warning1 = 0 - -; Turn off process-without-a-wait-statement warnings. Default is on. -; Show_Warning2 = 0 - -; Turn off null-range warnings. Default is on. -; Show_Warning3 = 0 - -; Turn off no-space-in-time-literal warnings. Default is on. -; Show_Warning4 = 0 - -; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. -; Show_Warning5 = 0 - -; Turn off optimization for IEEE std_logic_1164 package. Default is on. -; Optimize_1164 = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Turn on resolving of ambiguous function overloading in favor of the -; "explicit" function declaration (not the one automatically created by -; the compiler for each type declaration). Default is off. -; The .ini file has Explicit enabled so that std_logic_signed/unsigned -; will match the behavior of synthesis tools. -Explicit = 1 - -; Turn off acceleration of the VITAL packages. Default is to accelerate. -; NoVital = 1 - -; Turn off VITAL compliance checking. Default is checking on. -; NoVitalCheck = 1 - -; Ignore VITAL compliance checking errors. Default is to not ignore. -; IgnoreVitalErrors = 1 - -; Turn off VITAL compliance checking warnings. Default is to show warnings. -; Show_VitalChecksWarnings = 0 - -; Turn off PSL assertion warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Keep silent about case statement static warnings. -; Default is to give a warning. -; NoCaseStaticError = 1 - -; Keep silent about warnings caused by aggregates that are not locally static. -; Default is to give a warning. -; NoOthersStaticError = 1 - -; Treat as errors: -; case statement static warnings -; warnings caused by aggregates that are not locally static -; Overrides NoCaseStaticError, NoOthersStaticError settings. -; PedanticErrors = 1 - -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on some limited synthesis rule compliance checking. Checks only: -; -- signals used (read) by a process must be in the sensitivity list -; CheckSynthesis = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Require the user to specify a configuration for all bindings, -; and do not generate a compile time default binding for the -; component. This will result in an elaboration error of -; 'component not bound' if the user fails to do so. Avoids the rare -; issue of a false dependency upon the unused default binding. -; RequireConfigForAllDefaultBinding = 1 - -; Perform default binding at compile time. -; Default is to do default binding at load time. -; BindAtCompile = 1; - -; Inhibit range checking on subscripts of arrays. Range checking on -; scalars defined with subtypes is inhibited by default. -; NoIndexCheck = 1 - -; Inhibit range checks on all (implicit and explicit) assignments to -; scalar objects defined with subtypes. -; NoRangeCheck = 1 - -; Set the prefix to be honored for synthesis/coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Turn on code coverage in VHDL design units. Default is off. -; Coverage = sbceft - -; Turn off code coverage in VHDL subprograms. Default is on. -; CoverSub = 0 - -; Automatically exclude VHDL case statement OTHERS choice branches. -; This includes OTHERS choices in selected signal assigment statements. -; Default is to not exclude. -; CoverExcludeDefault = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Turn on or off clkOpt optimization for code coverage. Default is on. -; CoverClkOpt = 1 - -; Turn on or off clkOpt optimization builtins for code coverage. Default is on. -; CoverClkOptBuiltins = 0 - -; Inform code coverage optimizations to respect VHDL 'H' and 'L' -; values on signals in conditions and expressions, and to not automatically -; convert them to '1' and '0'. Default is to not convert. -; CoverRespectHandL = 0 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Use this directory for compiler temporary files instead of "work/_temp" -; CompilerTempDir = /tmp - -; Set this to cause the compilers to force data to be committed to disk -; when the files are closed. -; SyncCompilerFiles = 1 - -; Add VHDL-AMS declarations to package STANDARD -; Default is not to add -; AmsStandard = 1 - -; Range and length checking will be performed on array indices and discrete -; ranges, and when violations are found within subprograms, errors will be -; reported. Default is to issue warnings for violations, because subprograms -; may not be invoked. -; NoDeferSubpgmCheck = 0 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; Controls whether or not to show immediate assertions with constant expressions -; in GUI/report/UCDB etc. By default, immediate assertions with constant -; expressions are shown in GUI/report/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls how VHDL basic identifiers are stored with the design unit. -; Does not make the language case-sensitive, affects only how declarations -; declared with basic identifiers have their names stored and printed -; (in the GUI, examine, etc.). -; Default is to preserve the case as originally depicted in the VHDL source. -; Value of 0 indicates to change all basic identifiers to lower case. -; PreserveCase = 0 - -; For Configuration Declarations, controls the effect that USE clauses have -; on visibility inside the configuration items being configured. If 1 -; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, -; extend the visibility of objects made visible through USE clauses into nested -; component configurations. -; OldVHDLConfigurationVisibility = 0 - -; Allows VHDL configuration declarations to be in a different library from -; the corresponding configured entity. Default is to not allow this for -; stricter LRM-compliance. -; SeparateConfigLibrary = 1; - -; Determine how mode OUT subprogram parameters of type array and record are treated. -; If 0 (the default), then only VHDL 2008 will do this initialization. -; If 1, always initialize the mode OUT parameter to its default value. -; If 2, do not initialize the mode OUT out parameter. -; Note that prior to release 10.1, all language versions did not initialize mode -; OUT array and record type parameters, unless overridden here via this mechanism. -; In release 10.1 and later, only files compiled with VHDL 2008 will cause this -; initialization, unless overridden here. -; InitOutCompositeParam = 0 - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[vlog] -; Turn off inclusion of debugging info within design units. -; Default is to include debugging info. -; NoDebug = 1 - -; Turn on `protect compiler directive processing. -; Default is to ignore `protect directives. -; Protect = 1 - -; Turn off "Loading..." messages. Default is messages on. -; Quiet = 1 - -; Turn on Verilog hazard checking (order-dependent accessing of global vars). -; Default is off. -; Hazard = 1 - -; Turn on converting regular Verilog identifiers to uppercase. Allows case -; insensitivity for module names. Default is no conversion. -; UpCase = 1 - -; Activate optimizations on expressions that do not involve signals, -; waits, or function/procedure/task invocations. Default is off. -; ScalarOpts = 1 - -; Turns on lint-style checking. -; Show_Lint = 1 - -; Show source line containing error. Default is off. -; Show_source = 1 - -; Turn on bad option warning. Default is off. -; Show_BadOptionWarning = 1 - -; Revert back to IEEE 1364-1995 syntax, default is 0 (off). -; vlog95compat = 1 - -; Turn off PSL warning messages. Default is to show warnings. -; Show_PslChecksWarnings = 0 - -; Enable parsing of embedded PSL assertions. Default is enabled. -; EmbeddedPsl = 0 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Set the threshold for automatically identifying sparse Verilog memories. -; A memory with total size in bytes equal to or more than the sparse memory -; threshold gets marked as sparse automatically, unless specified otherwise -; in source code or by the +nosparse commandline option of vlog or vopt. -; The default is 1M. (i.e. memories with total size equal -; to or greater than 1Mb are marked as sparse) -; SparseMemThreshold = 1048576 - -; Set the prefix to be honored for synthesis and coverage pragma recognition. -; Default is "". -; AddPragmaPrefix = "" - -; Ignore synthesis and coverage pragmas with this prefix. -; Default is "". -; IgnorePragmaPrefix = "" - -; Set the option to treat all files specified in a vlog invocation as a -; single compilation unit. The default value is set to 0 which will treat -; each file as a separate compilation unit as specified in the P1800 draft standard. -; MultiFileCompilationUnit = 1 - -; Turn on code coverage in Verilog design units. Default is off. -; Coverage = sbceft - -; Automatically exclude Verilog case statement default branches. -; Default is to not automatically exclude defaults. -; CoverExcludeDefault = 1 - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable or disable Focused Expression Coverage analysis for conditions and -; expressions. Focused Expression Coverage data is provided by default when -; expression and/or condition coverage is active. -; CoverFEC = 0 - -; Enable or disable UDP Coverage analysis for conditions and expressions. -; UDP Coverage data is disabled by default when expression and/or condition -; coverage is active. -; CoverUDP = 1 - -; Enable or disable Rapid Expression Coverage mode for conditions and expressions. -; Disabling this would convert non-masking conditions in FEC tables to matching -; input patterns. -; CoverREC = 1 - -; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions -; for expression/condition coverage. -; NOTE: Enabling this may have a negative impact on simulation performance. -; CoverExpandReductionPrefix = 0 - -; Enable or disable short circuit evaluation of conditions and expressions when -; condition or expression coverage is active. Short circuit evaluation is enabled -; by default. -; CoverShortCircuit = 0 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Turn on code coverage in VLOG `celldefine modules, modules containing -; specify blocks, and modules included using vlog -v and -y. Default is off. -; CoverCells = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Control compiler and VOPT optimizations that are allowed when -; code coverage is on. This is a number from 0 to 5, with the following -; meanings (the default is 3): -; 5 -- All allowable optimizations are on. -; 4 -- Turn off removing unreferenced code. -; 3 -- Turn off process, always block and if statement merging. -; 2 -- Turn off expression optimization, converting primitives -; to continuous assignments, VHDL subprogram inlining. -; and VHDL clkOpt (converting FF's to builtins). -; 1 -- Turn off continuous assignment optimizations and clock suppression. -; 0 -- Turn off Verilog module inlining and VHDL arch inlining. -; HOWEVER, if fsm coverage is turned on, optimizations will be forced to -; level 3, with also turning off converting primitives to continuous assigns. -; CoverOpt = 3 - -; Specify the override for the default value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then LRM default -; value of 0 (zero) is used. This is a compile time option. -; SVCrossNumPrintMissingDefault = 0 - -; Setting following to 1 would cause creation of variables which -; would represent the value of Coverpoint expressions. This is used -; in conjunction with "SVCoverpointExprVariablePrefix" option -; in the modelsim.ini -; EnableSVCoverpointExprVariable = 0 - -; Specify the override for the prefix used in forming the variable names -; which represent the Coverpoint expressions. This is used in conjunction with -; "EnableSVCoverpointExprVariable" option of the modelsim.ini -; The default prefix is "expr". -; The variable name is -; variable name => _ -; SVCoverpointExprVariablePrefix = expr - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross option.goal (defined to be 100 in the LRM). -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" -; in the [vsim] section can override this value. -; SVCovergroupGoalDefault = 100 - -; Override for the default value of the SystemVerilog covergroup, -; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) -; NOTE: It does not override specific assignments in SystemVerilog -; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" -; in the [vsim] section can override this value. -; SVCovergroupTypeGoalDefault = 100 - -; Specify the override for the default value of "strobe" option for the -; Covergroup Type. This is a compile time option which forces "strobe" to -; a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). NOTE: This can be overriden by a runtime -; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. -; SVCovergroupStrobeDefault = 0 - -; Specify the override for the default value of "per_instance" option for the -; Covergroup variables. This is a compile time option which forces "per_instance" -; to a user specified default value and supersedes SystemVerilog specified -; default value of '0'(zero). -; SVCovergroupPerInstanceDefault = 0 - -; Specify the override for the default value of "get_inst_coverage" option for the -; Covergroup variables. This is a compile time option which forces -; "get_inst_coverage" to a user specified default value and supersedes -; SystemVerilog specified default value of '0'(zero). -; SVCovergroupGetInstCoverageDefault = 0 - -; -; A space separated list of resource libraries that contain precompiled -; packages. The behavior is identical to using the "-L" switch. -; -; LibrarySearchPath = [ ...] -LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact - -; The behavior is identical to the "-mixedansiports" switch. Default is off. -; MixedAnsiPorts = 1 - -; Enable SystemVerilog 3.1a $typeof() function. Default is off. -; EnableTypeOf = 1 - -; Only allow lower case pragmas. Default is disabled. -; AcceptLowerCasePragmaOnly = 1 - -; Set the maximum depth permitted for a recursive include file nesting. -; IncludeRecursionDepthMax = 5 - -; Turn ON detection of FSMs having single bit current state variable. -; FsmSingle = 1 - -; Turn off reset state transitions in FSM. -; FsmResetTrans = 0 - -; Turn off detections of FSMs having x-assignment. -; FsmXAssign = 0 - -; Turn ON detection of FSM Implicit Transitions. -; FsmImplicitTrans = 1 - -; List of file suffixes which will be read as SystemVerilog. White space -; in extensions can be specified with a back-slash: "\ ". Back-slashes -; can be specified with two consecutive back-slashes: "\\"; -; SvFileSuffixes = sv svp svh - -; This setting is the same as the vlog -sv command line switch. -; Enables SystemVerilog features and keywords when true (1). -; When false (0), the rules of IEEE Std 1364-2001 are followed and -; SystemVerilog keywords are ignored. -; Svlog = 0 - -; Prints attribute placed upon SV packages during package import -; when true (1). The attribute will be ignored when this -; entry is false (0). The attribute name is "package_load_message". -; The value of this attribute is a string literal. -; Default is true (1). -; PrintSVPackageLoadingAttribute = 1 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Controls if untyped parameters that are initialized with values greater -; than 2147483647 are mapped to generics of type INTEGER or ignored. -; If mapped to VHDL Integers, values greater than 2147483647 -; are mapped to negative values. -; Default is to map these parameter to generic of type INTEGER -; ForceUnsignedToVHDLInteger = 1 - -; Enable AMS wreal (wired real) extensions. Default is 0. -; WrealType = 1 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Generate symbols debugging database in only some special cases to save on -; the number of files in the library. For other design-units, this database is -; generated on-demand in vsim. -; Default is to to generate debugging database for all design-units. -; SmartDbgSym = 1 - -; Controls how $unit library entries are named. Valid options are: -; "file" (generate name based on the first file on the command line) -; "du" (generate name based on first design unit following an item -; found in $unit scope) -; CUAutoName = file - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -[sccom] -; Enable use of SCV include files and library. Default is off. -; UseScv = 1 - -; Add C++ compiler options to the sccom command line by using this variable. -; CppOptions = -g - -; Use custom C++ compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; CppPath = /usr/bin/g++ - -; Specify the compiler version from the list of support GNU compilers. -; examples 4.3.3, 4.5.0 -; CppInstall = 4.5.0 - -; Enable verbose messages from sccom. Default is off. -; SccomVerbose = 1 - -; sccom logfile. Default is no logfile. -; SccomLogfile = sccom.log - -; Enable use of SC_MS include files and library. Default is off. -; UseScMs = 1 - -; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. -; Sc22Mode = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - -; Enable use of UVMC library. Default is off. -; UseUvmc = 1 - -[vopt] -; Turn on code coverage in vopt. Default is off. -; Coverage = sbceft - -; Control compiler optimizations that are allowed when -; code coverage is on. Refer to the comment for this in the [vlog] area. -; CoverOpt = 3 - -; Controls set of CoverConstructs that are being considered for Coverage -; Collection. -; Some of Valid options are: default,set1,set2 -; Covermode = default - -; Controls set of HDL cover constructs that would be considered(or not considered) -; for Coverage Collection. (Default corresponds to covermode default). -; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". -; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva - -; Increase or decrease the maximum number of rows allowed in a UDP table -; implementing a VHDL condition coverage or expression coverage expression. -; More rows leads to a longer compile time, but more expressions covered. -; CoverMaxUDPRows = 192 - -; Increase or decrease the maximum number of input patterns that are present -; in FEC table. This leads to a longer compile time with more expressions -; covered with FEC metric. -; CoverMaxFECRows = 192 - -; Increase or decrease the limit on the size of expressions and conditions -; considered for expression and condition coverages. Higher FecUdpEffort leads -; to higher compile, optimize and simulation time, but more expressions and -; conditions are considered for coverage in the design. FecUdpEffort can -; be set to a number ranging from 1 (low) to 3 (high), defined as: -; 1 - (low) Only small expressions and conditions considered for coverage. -; 2 - (medium) Bigger expressions and conditions considered for coverage. -; 3 - (high) Very large expressions and conditions considered for coverage. -; The default setting is 1 (low). -; FecUdpEffort = 1 - -; Enable code coverage reporting of code that has been optimized away. -; The default is not to report. -; CoverReportCancelled = 1 - -; Enable deglitching of code coverage in combinatorial, non-clocked, processes. -; Default is no deglitching. -; CoverDeglitchOn = 1 - -; Enable compiler statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; Control the code coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a -; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; CoverDeglitchPeriod = 0 - -; Do not show immediate assertions with constant expressions in -; GUI/reports/UCDB etc. By default immediate assertions with constant -; expressions are shown in GUI/reports/UCDB etc. This does not affect -; evaluation of immediate assertions. -; ShowConstantImmediateAsserts = 0 - -; Set the maximum number of iterations permitted for a generate loop. -; Restricting this permits the implementation to recognize infinite -; generate loops. -; GenerateLoopIterationMax = 100000 - -; Set the maximum depth permitted for a recursive generate instantiation. -; Restricting this permits the implementation to recognize infinite -; recursions. -; GenerateRecursionDepthMax = 200 - -; Set the number of processes created during the code generation phase. -; By default a heuristic is used to set this value. This may be set to 0 -; to disable this feature completely. -; ParallelJobs = 0 - -; Controls SystemVerilog Language Extensions. These options enable -; some non-LRM compliant behavior. -; SvExtensions = [+|-][,[+|-]*] - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Disable SystemVerilog elaboration system task messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Enable or disable automatic creation of missing libraries. -; Default is 1 (enabled) -; CreateLib = 1 - - -[vsim] -; vopt flow -; Set to turn on automatic optimization of a design. -; Default is on -VoptFlow = 1 - -; Simulator resolution -; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. -Resolution = ns - -; Disable certain code coverage exclusions automatically. -; Assertions and FSM are exluded from the code coverage by default -; Set AutoExclusionsDisable = fsm to enable code coverage for fsm -; Set AutoExclusionsDisable = assertions to enable code coverage for assertions -; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions -; Or specify comma or space separated list -;AutoExclusionsDisable = fsm,assertions - -; User time unit for run commands -; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the -; unit specified for Resolution. For example, if Resolution is 100ps, -; then UserTimeUnit defaults to ps. -; Should generally be set to default. -UserTimeUnit = default - -; Default run length -RunLength = 100 - -; Maximum iterations that can be run without advancing simulation time -IterationLimit = 10000000 - -; Specify libraries to be searched for precompiled modules -; LibrarySearchPath = [ ...] - -; Set XPROP assertion fail limit. Default is 5. -; Any positive integer, -1 for infinity. -; XpropAssertionLimit = 5 - -; Control PSL and Verilog Assume directives during simulation -; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts -; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts -; SimulateAssumeDirectives = 1 - -; Control the simulation of PSL and SVA -; These switches can be overridden by the vsim command line switches: -; -psl, -nopsl, -sva, -nosva. -; Set SimulatePSL = 0 to disable PSL simulation -; Set SimulatePSL = 1 to enable PSL simulation (default) -; SimulatePSL = 1 -; Set SimulateSVA = 0 to disable SVA simulation -; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) -; SimulateSVA = 1 - -; Control SVA and VHDL immediate assertion directives during simulation -; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts -; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts -; SimulateImmedAsserts = 1 - -; License feature mappings for Verilog and VHDL -; qhsimvh Single language VHDL license -; qhsimvl Single language Verilog license -; msimhdlsim Language neutral license for either Verilog or VHDL -; msimhdlmix Second language only, language neutral license for either -; Verilog or VHDL -; -; Directives to license manager can be set either as single value or as -; space separated multi-values: -; vhdl Immediately checkout and hold a VHDL license (i.e., one of -; qhsimvh, msimhdlsim, or msimhdlmix) -; vlog Immediately checkout and hold a Verilog license (i.e., one of -; qhsimvl, msimhdlsim, or msimhdlmix) -; plus Immediately checkout and hold a VHDL license and a Verilog license -; noqueue Do not wait in the license queue when a license is not available -; viewsim Try for viewer license but accept simulator license(s) instead -; of queuing for viewer license (PE ONLY) -; noviewer Disable checkout of msimviewer license feature (PE ONLY) -; noslvhdl Disable checkout of qhsimvh license feature -; noslvlog Disable checkout of qhsimvl license feature -; nomix Disable checkout of msimhdlmix license feature -; nolnl Disable checkout of msimhdlsim license feature -; mixedonly Disable checkout of qhsimvh and qhsimvl license features -; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features -; -; Examples (remove ";" comment character to activate licensing directives): -; Single directive: -; License = plus -; Multi-directive (Note: space delimited directives): -; License = noqueue plus - -; Severity level of a VHDL assertion message or of a SystemVerilog severity system task -; which will cause a running simulation to stop. -; VHDL assertions and SystemVerilog severity system task that occur with the -; given severity or higher will cause a running simulation to stop. -; This value is ignored during elaboration. -; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal -BreakOnAssertion = 3 - -; Severity level of a tool message which will cause a running simulation to -; stop. This value is ignored during elaboration. Default is to not break. -; 0 = Note 1 = Warning 2 = Error 3 = Fatal -;BreakOnMessage = 2 - -; The class debug feature enables more visibility and tracking of class instances -; during simulation. By default this feature is disabled (0). To enable this -; feature set ClassDebug to 1. -; ClassDebug = 1 - -; Message Format conversion specifications: -; %S - Severity Level of message/assertion -; %R - Text of message -; %T - Time of message -; %D - Delta value (iteration number) of Time -; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected -; %i - Instance/Region/Signal pathname with Process name (if available) -; %I - shorthand for one of these: -; " %K: %i" -; " %K: %i File: %F" (when path is not Process or Signal) -; except that the %i in this case does not report the Process name -; %O - Process name -; %P - Instance/Region path without leaf process -; %F - File name -; %L - Line number; if assertion message, then line number of assertion or, if -; assertion is in a subprogram, line from which the call is made -; %u - Design unit name in form library.primary -; %U - Design unit name in form library.primary(secondary) -; %% - The '%' character itself -; -; If specific format for Severity Level is defined, use that format. -; Else, for a message that occurs during elaboration: -; -- Failure/Fatal message in VHDL region that is not a Process, and in -; certain non-VHDL regions, uses MessageFormatBreakLine; -; -- Failure/Fatal message otherwise uses MessageFormatBreak; -; -- Note/Warning/Error message uses MessageFormat. -; Else, for a message that occurs during runtime and triggers a breakpoint because -; of the BreakOnAssertion setting: -; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; -; -- otherwise uses MessageFormatBreak. -; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. -; -; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" -; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" -; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" -; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" - -; Error File - alternate file for storing error messages -; ErrorFile = error.log - -; Simulation Breakpoint messages -; This flag controls the display of function names when reporting the location -; where the simulator stops because of a breakpoint or fatal error. -; Example with function name: # Break in Process ctr at counter.vhd line 44 -; Example without function name: # Break at counter.vhd line 44 -; Default value is 1. -ShowFunctions = 1 - -; Default radix for all windows and commands. -; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned -; Flags may be one of: enumnumeric, showbase, wreal -DefaultRadix = hexadecimal -DefaultRadixFlags = showbase -; Set to 1 for make the signal_force VHDL and Verilog functions use the -; default radix when processing the force value. Prior to 10.2 signal_force -; used the default radix, now it always uses symbolic unless value explicitly indicates base -;SignalForceFunctionUseDefaultRadix = 0 - -; VSIM Startup command -; Startup = do startup.do - -; VSIM Shutdown file -; Filename to save u/i formats and configurations. -; ShutdownFile = restart.do -; To explicitly disable auto save: -; ShutdownFile = --disable-auto-save - -; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. -; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. -; BatchMode = 1 - -; File for saving command transcript when -batch option used -; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero -; default is unset so command transcript only goes to stdout for better performance -; BatchTranscriptFile = transcript - -; File for saving command transcript, this option is ignored when -batch option is used -TranscriptFile = transcript - -; Transcript file long line wrapping mode(s) -; mode == 0 :: no wrapping, line recorded as is -; mode == 1 :: wrap at first whitespace after WSColumn -; or at Column. -; mode == 2 :: wrap as above, but add continuation -; character ('\') at end of each wrapped line -; -; WrapMode = 0 -; WrapColumn = 30000 -; WrapWSColumn = 27000 - -; File for saving command history -; CommandHistory = cmdhist.log - -; Specify whether paths in simulator commands should be described -; in VHDL or Verilog format. -; For VHDL, PathSeparator = / -; For Verilog, PathSeparator = . -; Must not be the same character as DatasetSeparator. -PathSeparator = / - -; Specify the dataset separator for fully rooted contexts. -; The default is ':'. For example: sim:/top -; Must not be the same character as PathSeparator. -DatasetSeparator = : - -; Specify a unique path separator for the Signal Spy set of functions. -; The default will be to use the PathSeparator variable. -; Must not be the same character as DatasetSeparator. -; SignalSpyPathSeparator = / - -; Used to control parsing of HDL identifiers input to the tool. -; This includes CLI commands, vsim/vopt/vlog/vcom options, -; string arguments to FLI/VPI/DPI calls, etc. -; If set to 1, accept either Verilog escaped Id syntax or -; VHDL extended id syntax, regardless of source language. -; If set to 0, the syntax of the source language must be used. -; Each identifier in a hierarchical name may need different syntax, -; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or -; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" -; GenerousIdentifierParsing = 1 - -; Disable VHDL assertion messages -; IgnoreNote = 1 -; IgnoreWarning = 1 -; IgnoreError = 1 -; IgnoreFailure = 1 - -; Disable SystemVerilog assertion messages -; IgnoreSVAInfo = 1 -; IgnoreSVAWarning = 1 -; IgnoreSVAError = 1 -; IgnoreSVAFatal = 1 - -; Do not print any additional information from Severity System tasks. -; Only the message provided by the user is printed along with severity -; information. -; SVAPrintOnlyUserMessage = 1; - -; Default force kind. May be freeze, drive, deposit, or default -; or in other terms, fixed, wired, or charged. -; A value of "default" will use the signal kind to determine the -; force kind, drive for resolved signals, freeze for unresolved signals -; DefaultForceKind = freeze - -; Control the iteration of events when a VHDL signal is forced to a value -; This flag can be set to honour the signal update event in next iteration, -; the default is to update and propagate in the same iteration. -; ForceSigNextIter = 1 - -; Enable simulation statistics. Specify one or more arguments: -; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] -; Add '-' to disable specific statistics. Default is [time,cmd,msg]. -; Stats = time,cmd,msg - -; If zero, open files when elaborated; otherwise, open files on -; first read or write. Default is 0. -; DelayFileOpen = 1 - -; Control VHDL files opened for write. -; 0 = Buffered, 1 = Unbuffered -UnbufferedOutput = 0 - -; Control the number of VHDL files open concurrently. -; This number should always be less than the current ulimit -; setting for max file descriptors. -; 0 = unlimited -ConcurrentFileLimit = 40 - -; If nonzero, close files as soon as there is either an explicit call to -; file_close, or when the file variable's scope is closed. When zero, a -; file opened in append mode is not closed in case it is immediately -; reopened in append mode; otherwise, the file will be closed at the -; point it is reopened. -; AppendClose = 1 - -; Control the number of hierarchical regions displayed as -; part of a signal name shown in the Wave window. -; A value of zero tells VSIM to display the full name. -; The default is 0. -; WaveSignalNameWidth = 0 - -; Turn off warnings when changing VHDL constants and generics -; Default is 1 to generate warning messages -; WarnConstantChange = 0 - -; Turn off warnings from accelerated versions of the std_logic_arith, -; std_logic_unsigned, and std_logic_signed packages. -; StdArithNoWarnings = 1 - -; Turn off warnings from accelerated versions of the IEEE numeric_std -; and numeric_bit packages. -; NumericStdNoWarnings = 1 - -; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names -; in the design hierarchy. -; This style is controlled by the value of the GenerateFormat -; value described next. Default is to use new-style names, which -; comprise the generate statement label, '(', the value of the generate -; parameter, and a closing ')'. -; Set this to 1 to use old-style names. -; OldVhdlForGenNames = 1 - -; Control the format of the old-style VHDL FOR generate statement region -; name for each iteration. Do not quote the value. -; The format string here must contain the conversion codes %s and %d, -; in that order, and no other conversion codes. The %s represents -; the generate statement label; the %d represents the generate parameter value -; at a particular iteration (this is the position number if the generate parameter -; is of an enumeration type). Embedded whitespace is allowed (but discouraged); -; leading and trailing whitespace is ignored. -; Application of the format must result in a unique region name over all -; loop iterations for a particular immediately enclosing scope so that name -; lookup can function properly. The default is %s__%d. -; GenerateFormat = %s__%d - -; Enable more efficient logging of VHDL Variables. -; Logging VHDL variables without this enabled, while possible, is very -; inefficient. Enabling this will provide a more efficient logging methodology -; at the expense of more memory usage. By default this feature is disabled (0). -; To enabled this feature, set this variable to 1. -; VhdlVariableLogging = 1 - -; Enable logging of VHDL access type variables and their designated objects. -; This setting will allow both variables of an access type ("access variables") -; and their designated objects ("access objects") to be logged. Logging a -; variable of an access type will automatically also cause the designated -; object(s) of that variable to be logged as the simulation progresses. -; Further, enabling this allows access objects to be logged by name. By default -; this feature is disabled (0). To enable this feature, set this variable to 1. -; Enabling this will automatically enable the VhdlVariableLogging feature also. -; AccessObjDebug = 1 - -; Make each VHDL package in a PDU has its own separate copy of the package instead -; of sharing the package between PDUs. The default is to share packages. -; To ensure that each PDU has its own set of packages, set this variable to 1. -; VhdlSeparatePduPackage = 1 - -; Specify whether checkpoint files should be compressed. -; The default is 1 (compressed). -; CheckpointCompressMode = 0 - -; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. -; Use custom gcc compiler located at this path rather than the default path. -; The path should point directly at a compiler executable. -; DpiCppPath = /bin/gcc - -; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. -; The term "out-of-the-blue" refers to SystemVerilog export function calls -; made from C functions that don't have the proper context setup -; (as is the case when running under "DPI-C" import functions). -; When this is enabled, one can call a DPI export function -; (but not task) from any C code. -; the setting of this variable can be one of the following values: -; 0 : dpioutoftheblue call is disabled (default) -; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. -; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. -; DpiOutOfTheBlue = 1 - -; Specify whether continuous assignments are run before other normal priority -; processes scheduled in the same iteration. This event ordering minimizes race -; differences between optimized and non-optimized designs, and is the default -; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set -; ImmediateContinuousAssign to 0. -; The default is 1 (enabled). -; ImmediateContinuousAssign = 0 - -; List of dynamically loaded objects for Verilog PLI applications -; Veriuser = veriuser.sl - -; Which default VPI object model should the tool conform to? -; The 1364 modes are Verilog-only, for backwards compatibility with older -; libraries, and SystemVerilog objects are not available in these modes. -; -; In the absence of a user-specified default, the tool default is the -; latest available LRM behavior. -; Options for PliCompatDefault are: -; VPI_COMPATIBILITY_VERSION_1364v1995 -; VPI_COMPATIBILITY_VERSION_1364v2001 -; VPI_COMPATIBILITY_VERSION_1364v2005 -; VPI_COMPATIBILITY_VERSION_1800v2005 -; VPI_COMPATIBILITY_VERSION_1800v2008 -; -; Synonyms for each string are also recognized: -; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) -; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) -; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) -; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) -; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) - - -; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 - -; Specify whether the Verilog system task $fopen or vpi_mcd_open() -; will create directories that do not exist when opening the file -; in "a" or "w" mode. -; The default is 0 (do not create non-existent directories) -; CreateDirForFileAccess = 1 - -; Specify default options for the restart command. Options can be one -; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions -; DefaultRestartOptions = -force - - -; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. -; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. -; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". -; The list of options must be delimited by commas, without spaces or tabs. -; -; Some examples -; To turn on all available UVM-aware debug features: -; UVMControl = all -; To turn on the struct window, mesage logging, and transaction logging: -; UVMControl = struct,msglog,trlog -; To turn on all options except certe: -; UVMControl = all,-certe -; To completely disable all UVM-aware debug functionality: -; UVMControl = disable - -; Specify the WildcardFilter setting. -; A space separated list of object types to be excluded when performing -; wildcard matches with log, wave, etc commands. The default value for this variable is: -; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" -; See "Using the WildcardFilter Preference Variable" in the documentation for -; details on how to use this variable and for descriptions of the filter types. -WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile - -; Specify the WildcardSizeThreshold setting. -; This integer setting specifies the size at which objects will be excluded when -; performing wildcard matches with log, wave, etc commands. Objects of size equal -; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard -; matches. The size is a simple calculation of number of bits or items in the object. -; The default value is 8k (8192). Setting this value to 0 will disable the checking -; of object size against this threshold and allow all objects of any size to be logged. -WildcardSizeThreshold = 8192 - -; Specify whether warning messages are output when objects are filtered out due to the -; WildcardSizeThreshold. The default is 0 (no messages generated). -WildcardSizeThresholdVerbose = 0 - -; Turn on (1) or off (0) WLF file compression. -; The default is 1 (compress WLF file). -; WLFCompress = 0 - -; Specify whether to save all design hierarchy (1) in the WLF file -; or only regions containing logged signals (0). -; The default is 0 (save only regions with logged signals). -; WLFSaveAllRegions = 1 - -; WLF file time limit. Limit WLF file by time, as closely as possible, -; to the specified amount of simulation time. When the limit is exceeded -; the earliest times get truncated from the file. -; If both time and size limits are specified the most restrictive is used. -; UserTimeUnits are used if time units are not specified. -; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} -; WLFTimeLimit = 0 - -; WLF file size limit. Limit WLF file size, as closely as possible, -; to the specified number of megabytes. If both time and size limits -; are specified then the most restrictive is used. -; The default is 0 (no limit). -; WLFSizeLimit = 1000 - -; Specify whether or not a WLF file should be deleted when the -; simulation ends. A value of 1 will cause the WLF file to be deleted. -; The default is 0 (do not delete WLF file when simulation ends). -; WLFDeleteOnQuit = 1 - -; Specify whether or not a WLF file should be optimized during -; simulation. If set to 0, the WLF file will not be optimized. -; The default is 1, optimize the WLF file. -; WLFOptimize = 0 - -; Specify the name of the WLF file. -; The default is vsim.wlf -; WLFFilename = vsim.wlf - -; Specify whether to lock the WLF file. -; Locking the file prevents other invocations of ModelSim/Questa tools from -; inadvertently overwriting the WLF file. -; The default is 1, lock the WLF file. -; WLFFileLock = 0 - -; Specify the update interval for the WLF file in live simulation. -; The interval is given in seconds. -; The value is the smallest interval between WLF file updates. The WLF file -; will be flushed (updated) after (at least) the interval has elapsed, ensuring -; that the data is correct when viewed from a separate viewer. -; A value of 0 means that no updating will occur. -; The default value is 10 seconds. -; WLFUpdateInterval = 10 - -; Specify the WLF cache size limit for WLF files. -; The value is given in megabytes. A value of 0 turns off the cache. -; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). -; On Windows, the default value is 1000 (megabytes) to help to avoid filling -; process memory. -; WLFSimCacheSize allows a different cache size to be set for a live simulation -; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize -; is not set, it defaults to the WLFCacheSize value. -; WLFCacheSize = 2000 -; WLFSimCacheSize = 500 - -; Specify the WLF file event collapse mode. -; 0 = Preserve all events and event order. (same as -wlfnocollapse) -; 1 = Only record values of logged objects at the end of a simulator iteration. -; (same as -wlfcollapsedelta) -; 2 = Only record values of logged objects at the end of a simulator time step. -; (same as -wlfcollapsetime) -; The default is 1. -; WLFCollapseMode = 0 - -; Specify whether WLF file logging can use threads on multi-processor machines. -; If 0, no threads will be used; if 1, threads will be used if the system has -; more than one processor. -; WLFUseThreads = 1 - -; Specify the size of objects that will trigger "large object" messages -; at log/wave/list time. The size calculation of the object is the same as that -; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. -; Setting LargeObjectSize to 0 will disable these messages. -; LargeObjectSize = 500000 - -; Specify the depth of stack frames returned by $stacktrace([level]). -; This depth will be picked up when the optional 'level' argument -; is not specified or its value is not a positive integer. -; StackTraceDepth = 100 - -; Turn on/off undebuggable SystemC type warnings. Default is on. -; ShowUndebuggableScTypeWarning = 0 - -; Turn on/off unassociated SystemC name warnings. Default is off. -; ShowUnassociatedScNameWarning = 1 - -; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. -; ScShowIeeeDeprecationWarnings = 1 - -; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. -; ScEnableScSignalWriteCheck = 1 - -; Set SystemC default time unit. -; Set to fs, ps, ns, us, ms, or sec with optional -; prefix of 1, 10, or 100. The default is 1 ns. -; The ScTimeUnit value is honored if it is coarser than Resolution. -; If ScTimeUnit is finer than Resolution, it is set to the value -; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, -; then the default time unit will be 1 ns. However if Resolution -; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. -ScTimeUnit = ns - -; Set SystemC sc_main stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends -; on the amount of data on the sc_main() stack and the memory required -; to succesfully execute the longest function call chain of sc_main(). -ScMainStackSize = 10 Mb - -; Set SystemC thread stack size. The stack size is set as an integer -; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or -; Gb(Giga-byte). The stack size for sc_thread depends -; on the amount of data on the sc_thread stack and the memory required -; to succesfully execute the thread. -; ScStackSize = 1 Mb - -; Turn on/off execution of remainder of sc_main upon quitting the current -; simulation session. If the cumulative length of sc_main() in terms of -; simulation time units is less than the length of the current simulation -; run upon quit or restart, sc_main() will be in the middle of execution. -; This switch gives the option to execute the remainder of sc_main upon -; quitting simulation. The drawback of not running sc_main till the end -; is memory leaks for objects created by sc_main. If on, the remainder of -; sc_main will be executed ignoring all delays. This may cause the simulator -; to crash if the code in sc_main is dependent on some simulation state. -; Default is on. -ScMainFinishOnQuit = 1 - -; Enable calling of the DPI export taks/functions from the -; SystemC start_of_simulation() callback. -; The default is off. -; EnableDpiSosCb = 1 - - -; Set the SCV relationship name that will be used to identify phase -; relations. If the name given to a transactor relation matches this -; name, the transactions involved will be treated as phase transactions -ScvPhaseRelationName = mti_phase - -; Customize the vsim kernel shutdown behavior at the end of the simulation. -; Some common causes of the end of simulation are $finish (implicit or explicit), -; sc_stop(), tf_dofinish(), and assertion failures. -; This should be set to "ask", "exit", or "stop". The default is "ask". -; "ask" -- In batch mode, the vsim kernel will abruptly exit. -; In GUI mode, a dialog box will pop up and ask for user confirmation -; whether or not to quit the simulation. -; "stop" -- Cause the simulation to stay loaded in memory. This can make some -; post-simulation tasks easier. -; "exit" -- The simulation will abruptly exit without asking for any confirmation. -; "final" -- Run SystemVerilog final blocks then behave as "stop". -; Note: This variable can be overridden with the vsim "-onfinish" command line switch. -OnFinish = ask - -; Print pending deferred assertion messages. -; Deferred assertion messages may be scheduled after the $finish in the same -; time step. Deferred assertions scheduled to print after the $finish are -; printed before exiting with severity level NOTE since it's not known whether -; the assertion is still valid due to being printed in the active region -; instead of the reactive region where they are normally printed. -; OnFinishPendingAssert = 1; - -; Print "simstats" result. Default is 0. -; 0 == do not print simstats -; 1 == print at end of simulation -; 2 == print at end of each run command and end of simulation -; PrintSimStats = 1 - -; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages -; AssertFile = assert.log - -; Enable assertion counts. Default is off. -; AssertionCover = 1 - -; Run simulator in assertion debug mode. Default is off. -; AssertionDebug = 1 - -; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. -; AssertionEnable = 0 - -; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. -; Any positive integer, -1 for infinity. -; AssertionLimit = 1 - -; Turn on/off concurrent assertion pass log. Default is off. -; Assertion pass logging is only enabled when assertion is browseable -; and assertion debug is enabled. -; AssertionPassLog = 1 - -; Turn on/off PSL concurrent assertion fail log. Default is on. -; The flag does not affect SVA -; AssertionFailLog = 0 - -; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. -; AssertionFailLocalVarLog = 0 - -; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. -; 0 = Continue 1 = Break 2 = Exit -; AssertionFailAction = 1 - -; Enable the active thread monitor in the waveform display when assertion debug is enabled. -; AssertionActiveThreadMonitor = 1 - -; Control how many waveform rows will be used for displaying the active threads. Default is 5. -; AssertionActiveThreadMonitorLimit = 5 - -; Assertion thread limit after which assertion would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for an assertion go -; beyond this limit, the assertion would be either switched off or killed. This -; limit applies to only assert directives. -;AssertionThreadLimit = -1 - -; Action to be taken once the assertion thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only assert directives. -;AssertionThreadLimitAction = kill - -; Cover thread limit after which cover would be killed/switched off. -; The default is -1 (unlimited). If the number of threads for a cover go -; beyond this limit, the cover would be either switched off or killed. This -; limit applies to only cover directives. -;CoverThreadLimit = -1 - -; Action to be taken once the cover thread limit is reached. Default -; is kill. It can have a value of off or kill. In case of kill, all the existing -; threads are terminated and no new attempts are started. In case of off, the -; existing attempts keep on evaluating but no new attempts are started. This -; variable applies to only cover directives. -;CoverThreadLimitAction = kill - - -; By default immediate assertions do not participate in Assertion Coverage calculations -; unless they are executed. This switch causes all immediate assertions in the design -; to participate in Assertion Coverage calculations, whether attempted or not. -; UnattemptedImmediateAssertions = 0 - -; By default immediate covers participate in Coverage calculations -; whether they are attempted or not. This switch causes all unattempted -; immediate covers in the design to stop participating in Coverage -; calculations. -; UnattemptedImmediateCovers = 0 - -; By default pass action block is not executed for assertions on vacuous -; success. The following variable is provided to enable execution of -; pass action block on vacuous success. The following variable is only effective -; if the user does not disable pass action block execution by using either -; system tasks or CLI. Also there is a performance penalty for enabling -; the following variable. -;AssertionEnableVacuousPassActionBlock = 1 - -; As per strict 1850-2005 PSL LRM, an always property can either pass -; or fail. However, by default, Questa reports multiple passes and -; multiple fails on top always/never property (always/never operator -; is the top operator under Verification Directive). The reason -; being that Questa reports passes and fails on per attempt of the -; top always/never property. Use the following flag to instruct -; Questa to strictly follow LRM. With this flag, all assert/never -; directives will start an attempt once at start of simulation. -; The attempt can either fail, match or match vacuously. -; For e.g. if always is the top operator under assert, the always will -; keep on checking the property at every clock. If the property under -; always fails, the directive will be considered failed and no more -; checking will be done for that directive. A top always property, -; if it does not fail, will show a pass at end of simulation. -; The default value is '0' (i.e. zero is off). For example: -; PslOneAttempt = 1 - -; Specify the number of clock ticks to represent infinite clock ticks. -; This affects eventually!, until! and until_!. If at End of Simulation -; (EOS) an active strong-property has not clocked this number of -; clock ticks then neither pass or fail (vacuous match) is returned -; else respective fail/pass is returned. The default value is '0' (zero) -; which effectively does not check for clock tick condition. For example: -; PslInfinityThreshold = 5000 - -; Control how many thread start times will be preserved for ATV viewing for a given assertion -; instance. Default is -1 (ALL). -; ATVStartTimeKeepCount = -1 - -; Turn on/off code coverage -; CodeCoverage = 0 - -; This option applies to condition and expression coverage UDP tables. It -; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. -; If this option is used and a match occurs in more than one row in the UDP table, -; none of the counts for all matching rows is incremented. By default, counts are -; incremented for all matching rows. -; CoverCountAll = 1 - -; Turn off automatic inclusion of VHDL integers in toggle coverage. Default -; is to include them. -; ToggleNoIntegers = 1 - -; Set the maximum number of values that are collected for toggle coverage of -; VHDL integers. Default is 100; -; ToggleMaxIntValues = 100 - -; Set the maximum number of values that are collected for toggle coverage of -; Verilog real. Default is 100; -; ToggleMaxRealValues = 100 - -; Turn on automatic inclusion of Verilog integers in toggle coverage, except -; for enumeration types. Default is to include them. -; ToggleVlogIntegers = 0 - -; Turn on automatic inclusion of Verilog real type in toggle coverage, except -; for shortreal types. Default is to not include them. -; ToggleVlogReal = 1 - -; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays -; and VHDL arrays-of-arrays in toggle coverage. -; Default is to not include them. -; ToggleFixedSizeArray = 1 - -; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, -; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. -; This leads to a longer simulation time with bigger arrays covered with toggle coverage. -; Default is 1024. -; ToggleMaxFixedSizeArray = 1024 - -; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized -; one-dimensional packed vectors for toggle coverage. Default is 0. -; TogglePackedAsVec = 0 - -; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for -; toggle coverage. Default is 0. -; ToggleVlogEnumBits = 0 - -; Turn off automatic inclusion of VHDL records in toggle coverage. -; Default is to include them. -; ToggleVHDLRecords = 0 - -; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. -; For unlimited width, set to 0. -; ToggleWidthLimit = 128 - -; Limit the counts that are tracked for toggle coverage. When all edges for a bit have -; reached this count, further activity on the bit is ignored. Default is 1. -; For unlimited counts, set to 0. -; ToggleCountLimit = 1 - -; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. -; Following is the toggle coverage calculation criteria based on extended toggle mode: -; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). -; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. -; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. -; ExtendedToggleMode = 3 - -; Enable toggle statistics collection only for ports. Default is 0. -; TogglePortsOnly = 1 - -; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; FecCountLimit = 1 - -; Limit the counts that are tracked for UDP Coverage. When a bin has -; reached this count, further tracking of the input patterns linked to it is ignored. -; Default is 1. For unlimited counts, set to 0. -; NOTE: Changing this value from its default value may affect simulation performance. -; UdpCountLimit = 1 - -; Control toggle coverage deglitching period. A period of 0, eliminates delta -; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either -; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". -; ToggleDeglitchPeriod = 10.0ps - -; Turn on/off all PSL/SVA cover directive enables. Default is on. -; CoverEnable = 0 - -; Turn on/off PSL/SVA cover log. Default is off "0". -; CoverLog = 1 - -; Set "at_least" value for all PSL/SVA cover directives. Default is 1. -; CoverAtLeast = 2 - -; Set "limit" value for all PSL/SVA cover directives. Default is -1. -; Any positive integer, -1 for infinity. -; CoverLimit = 1 - -; Specify the coverage database filename. -; Default is "" (i.e. database is NOT automatically saved on close). -; UCDBFilename = vsim.ucdb - -; Specify the maximum limit for the number of Cross (bin) products reported -; in XML and UCDB report against a Cross. A warning is issued if the limit -; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this -; setting. -; MaxReportRhsSVCrossProducts = 1000 - -; Specify the override for the "auto_bin_max" option for the Covergroups. -; If not specified then value from Covergroup "option" is used. -; SVCoverpointAutoBinMax = 64 - -; Specify the override for the value of "cross_num_print_missing" -; option for the Cross in Covergroups. If not specified then value -; specified in the "option.cross_num_print_missing" is used. This -; is a runtime option. NOTE: This overrides any "cross_num_print_missing" -; value specified by user in source file and any SVCrossNumPrintMissingDefault -; specified in modelsim.ini. -; SVCrossNumPrintMissing = 0 - -; Specify whether to use the value of "cross_num_print_missing" -; option in report and GUI for the Cross in Covergroups. If not specified then -; cross_num_print_missing is ignored for creating reports and displaying -; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". -; UseSVCrossNumPrintMissing = 0 - -; Specify the threshold of Coverpoint wildcard bin value range size, above which -; a warning will be triggered. The default is 4K -- 12 wildcard bits. -; SVCoverpointWildCardBinValueSizeWarn = 4096 - -; Specify the override for the value of "strobe" option for the -; Covergroup Type. If not specified then value in "type_option.strobe" -; will be used. This is runtime option which forces "strobe" to -; user specified value and supersedes user specified values in the -; SystemVerilog Code. NOTE: This also overrides the compile time -; default value override specified using "SVCovergroupStrobeDefault" -; SVCovergroupStrobe = 0 - -; Override for explicit assignments in source code to "option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". -; SVCovergroupGoal = 100 - -; Override for explicit assignments in source code to "type_option.goal" of -; SystemVerilog covergroup, coverpoint, and cross. It also overrides the -; default value of "type_option.goal" (defined to be 100 in the SystemVerilog -; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". -; SVCovergroupTypeGoal = 100 - -; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() -; builtin functions, and report. This setting changes the default values of -; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 -; behavior if explicit assignments are not made on option.get_inst_coverage and -; type_option.merge_instances by the user. There are two vsim command line -; options, -cvg63 and -nocvg63 to override this setting from vsim command line. -; The default value of this variable from release 6.6 onwards is 0. This default -; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. -; SVCovergroup63Compatibility = 0 - -; Enforce the default behavior of covergroup get_coverage() builtin function, GUI -; and report. This variable sets the default value of type_option.merge_instances. -; There are two vsim command line options, -cvgmergeinstances and -; -nocvgmergeinstances to override this setting from vsim command line. -; The default value of this variable, -1 (don't care), allows the tool to determine -; the effective value, based on factors related to capacity and optimization. -; The type_option.merge_instances appears in the GUI and coverage reports as either -; auto(1) or auto(0), depending on whether the effective value was determined to -; be a 1 or a 0. -; SVCovergroupMergeInstancesDefault = -1 - -; Enable or disable generation of more detailed information about the sampling -; of covergroup, cross, and coverpoints. It provides the details of the number -; of times the covergroup instance and type were sampled, as well as details -; about why covergroup, cross and coverpoint were not covered. A non-zero value -; is to enable this feature. 0 is to disable this feature. Default is 0 -; SVCovergroupSampleInfo = 0 - -; Specify the maximum number of Coverpoint bins in whole design for -; all Covergroups. -; MaxSVCoverpointBinsDesign = 2147483648 - -; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins -; MaxSVCoverpointBinsInst = 1048576 - -; Specify the maximum number of Cross bins in whole design for -; all Covergroups. -; MaxSVCrossBinsDesign = 2147483648 - -; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins -; MaxSVCrossBinsInst = 67108864 - -; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. -; By default, this variable is set 0, in which case option.no_collect setting will take effect. -; If this variable is set to 1, all zero-weight coverage items will not be saved. -; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting -; of this variable. -; CvgZWNoCollect = 1 - -; Specify a space delimited list of double quoted TCL style -; regular expressions which will be matched against the text of all messages. -; If any regular expression is found to be contained within any message, the -; status for that message will not be propagated to the UCDB TESTSTATUS. -; If no match is detected, then the status will be propagated to the -; UCDB TESTSTATUS. More than one such regular expression text is allowed, -; and each message text is compared for each regular expression in the list. -; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" - -; Set weight for all PSL/SVA cover directives. Default is 1. -; CoverWeight = 2 - -; Check vsim plusargs. Default is 0 (off). -; 0 = Don't check plusargs -; 1 = Warning on unrecognized plusarg -; 2 = Error and exit on unrecognized plusarg -; CheckPlusargs = 1 - -; Load the specified shared objects with the RTLD_GLOBAL flag. -; This gives global visibility to all symbols in the shared objects, -; meaning that subsequently loaded shared objects can bind to symbols -; in the global shared objects. The list of shared objects should -; be whitespace delimited. This option is not supported on the -; Windows or AIX platforms. -; GlobalSharedObjectList = example1.so example2.so example3.so - -; Generate the stub definitions for the undefined symbols in the shared libraries being -; loaded in the simulation. When this flow is turned on, the undefined symbols will not -; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. -; The valid arguments are: on, off, verbose. -; on : turn on the automatic generation of stub definitions. -; off: turn off the flow. The undefined symbols will trigger an immediate load failure. -; verbose: Turn on the flow and report the undefined symbols for each shared library. -; NOTE: This variable can be overriden with vsim switch "-undefsyms". -; The default is on. -; -; UndefSyms = off - -; Enable the support for checkpointing foreign C++ libraries. -; The valid arguments are: 1 and 0. -; 1 : turn on the support -; 0 : turn off the support (default) -; This option is not supported on the Windows platforms. -; -; AllowCheckpointCpp = 1 - -; Initial seed for the random number generator of the root thread (SystemVerilog). -; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. -; The default value is 0. -; Sv_Seed = 0 - -; Specify the solver "engine" that vsim will select for constrained random -; generation. -; Valid values are: -; "auto" - automatically select the best engine for the current -; constraint scenario -; "bdd" - evaluate all constraint scenarios using the BDD solver engine -; "act" - evaluate all constraint scenarios using the ACT solver engine -; While the BDD solver engine is generally efficient with constraint scenarios -; involving bitwise logical relationships, the ACT solver engine can exhibit -; superior performance with constraint scenarios involving large numbers of -; random variables related via arithmetic operators (+, *, etc). -; NOTE: This variable can be overridden with the vsim "-solveengine" command -; line switch. -; The default value is "auto". -; SolveEngine = auto - -; Specify if the solver should attempt to ignore overflow/underflow semantics -; for arithmetic constraints (multiply, addition, subtraction) in order to -; improve performance. The "solveignoreoverflow" attribute can be specified on -; a per-call basis to randomize() to override this setting. -; The default value is 0 (overflow/underflow is not ignored). Set to 1 to -; ignore overflow/underflow. -; SolveIgnoreOverflow = 0 - -; Specifies the maximum size that a dynamic array may be resized to by the -; solver. If the solver attempts to resize a dynamic array to a size greater -; than the specified limit, the solver will abort with an error. -; The default value is 10000. A value of 0 indicates no limit. -; SolveArrayResizeMax = 10000 - -; Error message severity when randomize() failure is detected. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; The default is 0 (no error). -; SolveFailSeverity = 0 - -; Error message severity for suppressible errors that are detected in a -; solve/before constraint. -; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" -; command line switch. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; The default is 3 (failure). -; SolveBeforeErrorSeverity = 3 - -; Error message severity for suppressible errors that are related to -; solve engine capacity limits -; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" -; command line switch. -; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal -; The default is 3 (failure). -; SolveEngineErrorSeverity = 3 - -; Enable/disable debug information for randomize() failures. -; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command -; line switch. -; The default is 0 (disabled). Set to 1 to enable basic debug (with no -; performance penalty). Set to 2 for enhanced debug (will result in slower -; runtime performance). -; SolveFailDebug = 0 - -; Upon encountering a randomize() failure, generate a simplified testcase that -; will reproduce the failure. Optionally output the testcase to a file. -; Testcases for 'no-solution' failures will only be produced if SolveFailDebug -; is enabled (see above). -; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" -; command line switch. -; The default is OFF (do not generate a testcase). To enable testcase -; generation, uncomment this variable. To redirect testcase generation to a -; file, specify the name of the output file. -; SolveFailTestcase = - -; Specify solver timeout threshold (in seconds). randomize() will fail if the -; CPU time required to evaluate any randset exceeds the specified timeout. -; The default value is 500. A value of 0 will disable timeout failures. -; SolveTimeout = 500 - -; Specify the maximum size of the solution graph generated by the BDD solver. -; This value can be used to force the BDD solver to abort the evaluation of a -; complex constraint scenario that cannot be evaluated with finite memory. -; This value is specified in 1000s of nodes. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxSize = 10000 - -; Specify the maximum number of evaluations that may be performed on the -; solution graph by the BDD solver. This value can be used to force the BDD -; solver to abort the evaluation of a complex constraint scenario that cannot -; be evaluated in finite time. This value is specified in 10000s of evaluations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveGraphMaxEval = 10000 - -; Specify the maximum number of tests that the ACT solver may evaluate before -; abandoning an attempt to solve a particular constraint scenario. -; The default value is 2000000. A value of 0 indicates no limit. -; SolveACTMaxTests = 2000000 - -; Specify the maximum number of operations that the ACT solver may perform -; before abandoning an attempt to solve a particular constraint scenario. The -; value is specified in 1000000s of operations. -; The default value is 10000. A value of 0 indicates no limit. -; SolveACTMaxOps = 10000 - -; Specify the number of times the ACT solver will retry to evaluate a constraint -; scenario that fails due to the SolveACTMax[Tests|Ops] threshold. -; The default value is 0 (no retry). -; SolveACTRetryCount = 0 - -; Specify random sequence compatiblity with a prior letter release. This -; option is used to get the same random sequences during simulation as -; as a prior letter release. Only prior letter releases (of the current -; number release) are allowed. -; NOTE: Only those random sequence changes due to solver optimizations are -; reverted by this variable. Random sequence changes due to solver bugfixes -; cannot be un-done. -; NOTE: This variable can be overridden with the vsim "-solverev" command -; line switch. -; Default value set to "" (no compatibility). -; SolveRev = - -; Environment variable expansion of command line arguments has been depricated -; in favor shell level expansion. Universal environment variable expansion -; inside -f files is support and continued support for MGC Location Maps provide -; alternative methods for handling flexible pathnames. -; The following line may be uncommented and the value set to 1 to re-enable this -; deprecated behavior. The default value is 0. -; DeprecatedEnvironmentVariableExpansion = 0 - -; Specify the memory threshold for the System Verilog garbage collector. -; The value is the number of megabytes of class objects that must accumulate -; before the garbage collector is run. -; The GCThreshold setting is used when class debug mode is disabled to allow -; less frequent garbage collection and better simulation performance. -; The GCThresholdClassDebug setting is used when class debug mode is enabled -; to allow for more frequent garbage collection. -; GCThreshold = 100 -; GCThresholdClassDebug = 5 - -; Turn on/off collapsing of bus ports in VCD dumpports output -DumpportsCollapse = 1 - -; Location of Multi-Level Verification Component (MVC) installation. -; The default location is the product installation directory. -MvcHome = $MODEL_TECH/.. - -; Location of InFact installation. The default is $MODEL_TECH/../../infact -; -; InFactHome = $MODEL_TECH/../../infact - -; Initialize SystemVerilog enums using the base type's default value -; instead of the leftmost value. -; EnumBaseInit = 1 - -; Suppress file type registration. -; SuppressFileTypeReg = 1 - -; Enable/disable non-LRM compliant SystemVerilog language extensions. -; Valid extensions are: -; cfce - generate an error if $cast fails as a function -; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks -; expdfmt - enable format string extensions for $display/$sformatf -; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) -; fmtcap - prints capital hex digits with %X/%H in display calls -; iddp - ignore DPI disable protocol check -; noexptc - ignore DPI export type name overloading check -; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") -; realrand - support randomize() with real variables and constraints (Default) -; SvExtensions = [+|-][,[+|-]*] - -; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. -; Valid extensions are: -; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles -; forkjoinstab - preserve parent thread random stability when seeding fork/join sub-threads (Default) -; nonrandstab - disable seeding of "non-random" class instances (Default) -; nodist - interpret 'dist' constraint as 'inside' (ACT only) -; noorder - ignore solve/before ordering constraints (ACT only) -; packrandidx - allow random index for packed variable in constraint (Default) -; promotedist - promote priority of 'dist' constraint if LHS has no solve/before -; randskew - skew randomize results (ACT only) -; SvRandExtensions = [+|-][,[+|-]*] - -; Controls the formatting of '%p' and '%P' conversion specification, used in $display -; and similar system tasks. -; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. -; The 'I' flag when present causes relevant data types to be expanded and indented into -; a more readable format. -; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). -; 2. SVPrettyPrintFlags=L limits the output to lines. -; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). -; 3. SVPrettyPrintFlags=C limits the output to characters. -; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). -; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). -; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes -; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). -; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . -; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). -; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. -; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). -; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. -; 8. Items 1-7 above can be combined as a comma separated list. -; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) -; SVPrettyPrintFlags=I4S - -[lmc] -; The simulator's interface to Logic Modeling's SmartModel SWIFT software -libsm = $MODEL_TECH/libsm.sl -; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) -; libsm = $MODEL_TECH/libsm.dll -; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) -; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl -; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) -; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o -; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) -; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Windows NT) -; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll -; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so -; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) -; libswift = $LMC_HOME/lib/linux.lib/libswift.so - -; The simulator's interface to Logic Modeling's hardware modeler SFI software -libhm = $MODEL_TECH/libhm.sl -; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) -; libhm = $MODEL_TECH/libhm.dll -; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) -; libsfi = /lib/hp700/libsfi.sl -; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) -; libsfi = /lib/rs6000/libsfi.a -; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) -; libsfi = /lib/sun4.solaris/libsfi.so -; Logic Modeling's hardware modeler SFI software (Windows NT) -; libsfi = /lib/pcnt/lm_sfi.dll -; Logic Modeling's hardware modeler SFI software (Linux) -; libsfi = /lib/linux/libsfi.so - -[msg_system] -; Change a message severity or suppress a message. -; The format is: = [,...] -; suppress can be used to achieve +nowarn functionality -; The format is: suppress = ,,[,,...] -; Examples: -suppress = 8780 ;an explanation can be had by running: verror 8780 -; note = 3009 -; warning = 3033 -; error = 3010,3016 -; fatal = 3016,3033 -; suppress = 3009,3016,3601 -; suppress = 3009,CNNODP,3601,TFMPC -; suppress = 8683,8684 -; The command verror can be used to get the complete -; description of a message. - -; Control transcripting of Verilog display system task messages and -; PLI/FLI print function call messages. The system tasks include -; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They -; also include the analogous file I/O tasks that write to STDOUT -; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, -; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default -; is to have messages appear only in the transcript. The other -; settings are to send messages to the wlf file only (messages that -; are recorded in the wlf file can be viewed in the MsgViewer) or -; to both the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; displaymsgmode = tran - -; Control transcripting of elaboration/runtime messages not -; addressed by the displaymsgmode setting. The default is to -; have messages appear only in the transcript. The other settings -; are to send messages to the wlf file only (messages that are -; recorded in the wlf file can be viewed in the MsgViewer) or to both -; the transcript and the wlf file. The valid values are -; tran {transcript only (default)} -; wlf {wlf file only} -; both {transcript and wlf file} -; msgmode = tran - -; Controls number of displays of a particluar message -; default value is 5 -; MsgLimitCount = 5 - -[utils] -; Default Library Type (while creating a library with "vlib") -; 0 - legacy library using subdirectories for design units -; 2 - flat library -; DefaultLibType = 2 - -; Flat Library Page Size (while creating a library with "vlib") -; Set the size in bytes for flat library file pages. Libraries containing -; very large files may benefit from a larger value. -; FlatLibPageSize = 8192 - -; Flat Library Page Cleanup Percentage (while creating a library with "vlib") -; Set the percentage of total pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeleteThreshold. -; FlatLibPageDeletePercentage = 50 - -; Flat Library Page Cleanup Threshold (while creating a library with "vlib") -; Set the number of pages deleted before library cleanup can occur. -; This setting is applied together with FlatLibPageDeletePercentage. -; FlatLibPageDeleteThreshold = 1000 - -[Project] -; Warning -- Do not edit the project properties directly. -; Property names are dynamic in nature and property -; values have special syntax. Changing property data directly -; can result in a corrupt MPF file. All project properties -; can be modified through project window dialogs. -Project_Version = 6 -Project_DefaultLib = work -Project_SortMethod = unused -Project_Files_Count = 56 -Project_File_0 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory.v -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 54 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_1 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_clone_inter.v -Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 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{Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_18 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_exec_unit_req_inter.v -Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_19 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_cache_data.v -Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_20 = /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_register.v -Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_21 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v -Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 42 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_22 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Bank.v -Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_23 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v -Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 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Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 48 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_26 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v -Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 38 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_27 = /nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v -Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572061058 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_28 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_read_inter.v -Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 34 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_29 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mw_wb_inter.v -Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 46 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_30 = /nethome/felsabbagh3/research/Vortex/rtl/byte_enabled_simple_dual_port_ram.v -Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_31 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v -Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_32 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_data_inter.v -Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 32 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_33 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_set_bit.v -Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 53 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_34 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v -Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_35 = /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v -Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1572058635 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_36 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v -Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_37 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v -Project_File_P_37 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 40 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_38 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v -Project_File_P_38 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 37 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_39 = /nethome/felsabbagh3/research/Vortex/rtl/VX_execute_unit.v -Project_File_P_39 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work 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0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 45 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_42 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dram_req_rsp_inter.v -Project_File_P_42 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1572058636 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_43 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_priority_encoder_sm.v -Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 52 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_44 = /nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v -Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1572058635 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_45 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_warp_ctl_inter.v -Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 47 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_46 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_Cache_Block_DM.v -Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_47 = /nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v -Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1571845660 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} 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vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_50 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache_encapsulate.v -Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_51 = /nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_shared_memory_block.v -Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1571845660 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 55 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_52 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v -Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_53 = /nethome/felsabbagh3/research/Vortex/rtl/pipe_regs/VX_d_e_reg.v -Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 50 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_54 = /nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v -Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1572058635 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_55 = /nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_jal_inter.v -Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 vlog_noload 0 last_compile 1571845660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 33 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_Sim_Count = 0 -Project_Folder_Count = 0 -Echo_Compile_Output = 0 -Save_Compile_Report = 1 -Project_Opt_Count = 0 -ForceSoftPaths = 0 -ProjectStatusDelay = 5000 -VERILOG_DoubleClick = Edit -VERILOG_CustomDoubleClick = -SYSTEMVERILOG_DoubleClick = Edit -SYSTEMVERILOG_CustomDoubleClick = -VHDL_DoubleClick = Edit -VHDL_CustomDoubleClick = -PSL_DoubleClick = Edit -PSL_CustomDoubleClick = -TEXT_DoubleClick = Edit -TEXT_CustomDoubleClick = -SYSTEMC_DoubleClick = Edit -SYSTEMC_CustomDoubleClick = -TCL_DoubleClick = Edit -TCL_CustomDoubleClick = -MACRO_DoubleClick = Edit -MACRO_CustomDoubleClick = -VCD_DoubleClick = Edit -VCD_CustomDoubleClick = -SDF_DoubleClick = Edit -SDF_CustomDoubleClick = -XML_DoubleClick = Edit -XML_CustomDoubleClick = -LOGFILE_DoubleClick = Edit -LOGFILE_CustomDoubleClick = -UCDB_DoubleClick = Edit -UCDB_CustomDoubleClick = -TDB_DoubleClick = Edit -TDB_CustomDoubleClick = -UPF_DoubleClick = Edit -UPF_CustomDoubleClick = -PCF_DoubleClick = Edit -PCF_CustomDoubleClick = -PROJECT_DoubleClick = Edit -PROJECT_CustomDoubleClick = -VRM_DoubleClick = Edit -VRM_CustomDoubleClick = -DEBUGDATABASE_DoubleClick = Edit -DEBUGDATABASE_CustomDoubleClick = -DEBUGARCHIVE_DoubleClick = Edit -DEBUGARCHIVE_CustomDoubleClick = -Project_Major_Version = 10 -Project_Minor_Version = 6 diff --git a/hw/old_rtl/modelsim/vortex_dpi.cpp b/hw/old_rtl/modelsim/vortex_dpi.cpp deleted file mode 100644 index 67af68ab..00000000 --- a/hw/old_rtl/modelsim/vortex_dpi.cpp +++ /dev/null @@ -1,328 +0,0 @@ - -// #include - -// #include "VX_define.h" - - -#include <../simulate/ram.h> -#include -#include -#include "svdpi.h" - -#include "../simulate/VX_define.h" - -// #include "vortex_dpi.h" - -extern "C" { - void load_file (char * filename); - void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); - void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); - void io_handler (bool clk, bool io_valid, unsigned io_data); - void gracefulExit(int); -} - -RAM ram; -bool refill; -unsigned refill_addr; -bool i_refill; -unsigned i_refill_addr; - -unsigned num_cycles; - -unsigned getIndex(int, int, int); -unsigned calculate_bits_per_bank_num(int); - -unsigned getIndex(int r, int c, int numCols) -{ - return (r * numCols) + c; -} - -unsigned calculate_bits_per_bank_num(int num) -{ - int shifted_num = 0; - for(int i = 0; i < num; i++){ - shifted_num = (shifted_num << 1)| 1 ; - } - return shifted_num; -} - - -void load_file(char * filename) -{ - num_cycles = 0; - // printf("\n\n\n\n**********************\n"); - // printf("Inside load_file\n"); - - fprintf(stderr, "\n\n\n\n**********************\n"); - loadHexImpl(filename, &ram); - // printf("Filename: %s\n", filename); - refill = false; - i_refill = false; -} - -void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready) -{ - - - // Default values - { - s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; - (*i_m_ready) = false; - for (int i = 0; i < cache_banks; i++) - { - for (int j = 0; j < num_words_per_block; j++) - { - - unsigned index = getIndex(i,j, num_words_per_block); - - real_i_m_readdata[index].aval = 0x506070; - - // svGetArrElemPtr2(i_m_readdata, i, j); - // svPutLogicArrElem2VecVal(i_m_readdata, i, j); - // i_m_readdata[getIndex(i,j, num_words_per_block)] = 0; - } - } - } - - - if (clk) - { - // Do nothing on positive edge - } - else - { - - if (i_refill) - { - // svGetArrElemPtr2((*i_m_readdata), 0,0); - // fprintf(stderr, "--------------------------------\n"); - i_refill = false; - - - *i_m_ready = true; - s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; - for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) - { - unsigned new_addr = i_refill_addr + (4*curr_e); - - - unsigned addr_without_byte = new_addr >> 2; - - unsigned bits_per_bank = (int)log2(cache_banks); - // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); - unsigned maskbits_per_bank = cache_banks - 1; - unsigned bank_num = addr_without_byte & maskbits_per_bank; - unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; - unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); - - unsigned value; - ram.getWord(new_addr, &value); - - fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value); - unsigned index = getIndex(bank_num,offset_num, num_words_per_block); - - // fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value); - - real_i_m_readdata[index].aval = value; - - } - } - else - { - if (o_m_valid) - { - - s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata; - - if (o_m_read_or_write) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - - for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) - { - unsigned new_addr = (o_m_evict_addr) + (4*curr_e); - - - unsigned addr_without_byte = new_addr >> 2; - unsigned bits_per_bank = (int)log2(cache_banks); - // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); - unsigned maskbits_per_bank = cache_banks - 1; - unsigned bank_num = addr_without_byte & maskbits_per_bank; - unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; - unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); - // unsigned offset_num = addr_wihtout_bank & 0x3; - unsigned index = getIndex(bank_num,offset_num, num_words_per_block); - - - - unsigned new_value = real_o_m_writedata[index].aval; - - // new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num); - // new_value = getElem(o_m_writedata, index); - // unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)]; - - - ram.writeWord( new_addr, &new_value); - - fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value); - } - - } - - // Respond next cycle - i_refill = true; - i_refill_addr = o_m_read_addr; - } - } - - } -} - - -void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready) -{ - - - // Default values - { - s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; - (*i_m_ready) = false; - for (int i = 0; i < cache_banks; i++) - { - for (int j = 0; j < num_words_per_block; j++) - { - - unsigned index = getIndex(i,j, num_words_per_block); - - real_i_m_readdata[index].aval = 0x506070; - - // svGetArrElemPtr2(i_m_readdata, i, j); - // svPutLogicArrElem2VecVal(i_m_readdata, i, j); - // i_m_readdata[getIndex(i,j, num_words_per_block)] = 0; - } - } - } - - - if (clk) - { - // Do nothing on positive edge - } - else - { - - if (refill) - { - // svGetArrElemPtr2((*i_m_readdata), 0,0); - // fprintf(stderr, "--------------------------------\n"); - refill = false; - - - *i_m_ready = true; - s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata; - for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) - { - unsigned new_addr = refill_addr + (4*curr_e); - - - unsigned addr_without_byte = new_addr >> 2; - - unsigned bits_per_bank = (int)log2(cache_banks); - // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); - unsigned maskbits_per_bank = cache_banks - 1; - unsigned bank_num = addr_without_byte & maskbits_per_bank; - unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; - unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); - - unsigned value; - ram.getWord(new_addr, &value); - - fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value); - unsigned index = getIndex(bank_num,offset_num, num_words_per_block); - - // fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value); - - real_i_m_readdata[index].aval = value; - - } - } - else - { - if (o_m_valid) - { - - s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata; - - if (o_m_read_or_write) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - - for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++) - { - unsigned new_addr = (o_m_evict_addr) + (4*curr_e); - - - unsigned addr_without_byte = new_addr >> 2; - unsigned bits_per_bank = (int)log2(cache_banks); - // unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank); - unsigned maskbits_per_bank = cache_banks - 1; - unsigned bank_num = addr_without_byte & maskbits_per_bank; - unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank; - unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1); - // unsigned offset_num = addr_wihtout_bank & 0x3; - unsigned index = getIndex(bank_num,offset_num, num_words_per_block); - - - - unsigned new_value = real_o_m_writedata[index].aval; - - // new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num); - // new_value = getElem(o_m_writedata, index); - // unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)]; - - - ram.writeWord( new_addr, &new_value); - - fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value); - } - - } - - // Respond next cycle - refill = true; - refill_addr = o_m_read_addr; - } - } - - } -} - - -void io_handler(bool clk, bool io_valid, unsigned io_data) -{ - // printf("Inside io_handler\n"); - if (clk) - { - // Do nothing - } - else - { - if (io_valid) - { - uint32_t data_write = (uint32_t) (io_data); - - fprintf(stderr, "%c", (char) data_write); - fflush(stderr); - } - } -} - -void gracefulExit(int cycles) -{ - fprintf(stderr, "*********************\n\n"); - fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles); -} - - - - diff --git a/hw/old_rtl/modelsim/vortex_dpi.h b/hw/old_rtl/modelsim/vortex_dpi.h deleted file mode 100644 index 4a3509d0..00000000 --- a/hw/old_rtl/modelsim/vortex_dpi.h +++ /dev/null @@ -1,8 +0,0 @@ - -extern "C" { - void load_file (char * filename); - void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); - void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready); - void io_handler (bool clk, bool io_valid, unsigned io_data); - void gracefulExit(); -} \ No newline at end of file diff --git a/hw/old_rtl/modelsim/vortex_tb.v b/hw/old_rtl/modelsim/vortex_tb.v deleted file mode 100644 index 1db58aed..00000000 --- a/hw/old_rtl/modelsim/vortex_tb.v +++ /dev/null @@ -1,160 +0,0 @@ - -`include "../VX_define.v" - -//`define NUMBER_BANKS 8 -//`define NUM_WORDS_PER_BLOCK 4 - -`define ARM_UD_MODEL - -`timescale 1ns/1ps - -import "DPI-C" load_file = function void load_file(input string filename); - -/* -import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr, - output int instruction); - */ - -import "DPI-C" ibus_driver = function void ibus_driver( input logic clk, - input int o_m_read_addr, - input int o_m_evict_addr, - input logic o_m_valid, - input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], - input logic o_m_read_or_write, - input int cache_banks, - input int words_per_block, - // Rsp - output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0], - output logic i_m_ready); - -import "DPI-C" dbus_driver = function void dbus_driver( input logic clk, - input int o_m_read_addr, - input int o_m_evict_addr, - input logic o_m_valid, - input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], - input logic o_m_read_or_write, - input int cache_banks, - input int words_per_block, - // Rsp - output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0], - output logic i_m_ready); - - -import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data); - -import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num); - -module vortex_tb ( - -); - - int cycle_num; - -reg clk; -reg reset; -reg[31:0] icache_response_instruction; -reg[31:0] icache_request_pc_address; -// IO -reg io_valid; -reg[31:0] io_data; -// Req - reg [31:0] o_m_read_addr_d; - reg [31:0] o_m_evict_addr_d; - reg o_m_valid_d; - reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; - reg o_m_read_or_write_d; - - // Rsp - reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0]; - reg i_m_ready_d; - -// Req - reg [31:0] o_m_read_addr_i; - reg [31:0] o_m_evict_addr_i; - reg o_m_valid_i; - reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; - reg o_m_read_or_write_i; - - // Rsp - reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0]; - reg i_m_ready_i; -reg out_ebreak; - - - reg[31:0] hi; - - integer temp; - - initial begin - // $fdumpfile("vortex1.vcd"); - load_file("../../runtime/mains/simple/vx_simple_main.hex"); - // load_file("../../emulator/riscv_tests/rv32ui-p-add.hex"); - //load_file("../../kernel/vortex_test.hex"); - $dumpvars(0, vortex_tb); - reset = 1; - clk = 0; - #5 reset = 1; - clk = 1; - cycle_num = 0; - end - - Vortex vortex( - .clk (clk), - .reset (reset), - .icache_response_instruction (icache_response_instruction), - .icache_request_pc_address (icache_request_pc_address), - .io_valid (io_valid), - .io_data (io_data), - .o_m_read_addr_d (o_m_read_addr_d), - .o_m_evict_addr_d (o_m_evict_addr_d), - .o_m_valid_d (o_m_valid_d), - .o_m_writedata_d (o_m_writedata_d), - .o_m_read_or_write_d (o_m_read_or_write_d), - .i_m_readdata_d (i_m_readdata_d), - .i_m_ready_d (i_m_ready_d), - .o_m_read_addr_i (o_m_read_addr_i), - .o_m_evict_addr_i (o_m_evict_addr_i), - .o_m_valid_i (o_m_valid_i), - .o_m_writedata_i (o_m_writedata_i), - .o_m_read_or_write_i (o_m_read_or_write_i), - .i_m_readdata_i (i_m_readdata_i), - .i_m_ready_i (i_m_ready_i), - .out_ebreak (out_ebreak) - ); - - always @(negedge clk) begin - ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i); - dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d); - io_handler (clk, io_valid, io_data); - - end - - always @(posedge clk) begin - if (out_ebreak) begin - gracefulExit(cycle_num); - #40 $finish; - end - end - - always @(posedge clk) begin - cycle_num = cycle_num + 1; - end - - always @(clk, posedge reset) begin - if (reset) begin - reset = 0; - clk = 0; - end - - #5 clk <= ~clk; - - end - -endmodule - - - - - - - diff --git a/hw/old_rtl/modelsim/work/_info b/hw/old_rtl/modelsim/work/_info deleted file mode 100644 index 00edac9f..00000000 --- a/hw/old_rtl/modelsim/work/_info +++ /dev/null @@ -1,1084 +0,0 @@ -m255 -K4 -z2 -13 -!s112 1.1 -!i10d 8192 -!i10e 25 -!i10f 100 -cModel Technology -d/nethome/felsabbagh3 -vbyte_enabled_simple_dual_port_ram -Z0 DXx6 sv_std 3 std 0 22 AD7iAPLo6nTIKk>?2fFo2 -R2 -!s105 VX_back_end_v_unit -S1 -R3 -R9 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v -L0 1 -R5 -r1 -!s85 0 -31 -!s108 1572060852.000000 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_back_end.v| -!i113 0 -R7 -R8 -n@v@x_back_end -vVX_bank_valids -R0 -!s110 1572060870 -!i10b 1 -!s100 8J^J:@i9Meh3ejJzoMNRl1 -IVMcgc?onFY87NP^=[feO_0 -R2 -!s105 VX_bank_valids_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v -F/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v -L0 4 -R5 -r1 -!s85 0 -31 -!s108 1572060870.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/shared_memory/VX_bank_valids.v| -!i113 0 -R7 -R8 -n@v@x_bank_valids -YVX_branch_response_inter -R0 -Z11 !s110 1572060860 -!i10b 1 -!s100 ?IdSOM2]VFSUk;4?QYfAj1 -IRZ9enLe49LL`mLAeG1dL41 -R2 -!s105 VX_branch_response_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -Z12 !s108 1572060860.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_branch_response_inter.v| -!i113 0 -R7 -R8 -n@v@x_branch_response_inter -vVX_Cache_Bank -R0 -!s110 1572060857 -!i10b 1 -!s100 j9_Ic?]NV;A]SX?YSN022 -R2 -!s105 VX_csr_req_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R12 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_req_inter.v| -!i113 0 -R7 -R8 -n@v@x_csr_req_inter -YVX_csr_wb_inter -R0 -!s110 1572060861 -!i10b 1 -!s100 1VNJF?9koZ[iz<2a_AEIe3 -I_ALoZD>YDHkHgSF>F;>HQ2 -R2 -!s105 VX_csr_wb_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -!s108 1572060861.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_csr_wb_inter.v| -!i113 0 -R7 -R8 -n@v@x_csr_wb_inter -vVX_csr_wrapper -R0 -!s110 1572061082 -!i10b 1 -!s100 LbYbMNCf=0AzhCB>CP4gV1 -ImWJ;a=;GMB9KeJ;cTDEl30 -R2 -!s105 VX_csr_wrapper_v_unit -S1 -R3 -w1572061058 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v -L0 3 -R5 -r1 -!s85 0 -31 -!s108 1572061081.000000 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_csr_wrapper.v| -!i113 0 -R7 -R8 -n@v@x_csr_wrapper -vVX_d_cache -R0 -!s110 1572060859 -!i10b 1 -!s100 OI>VY^XI_AKKhz`Z>2kf=0 -Ih:mHKdjd9hE?1H5WRS>;:2 -R2 -!s105 VX_d_cache_v_unit -S1 -R3 -R9 -8/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v -F/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v -L0 16 -R5 -r1 -!s85 0 -31 -!s108 1572060859.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/cache/VX_d_cache.v| -!i113 0 -R7 -R8 -n@v@x_d_cache -YVX_dcache_request_inter -R0 -!s110 1572060862 -!i10b 1 -!s100 7cnI6Rc92LVQ67`57EET>1 -IMzzF:AXEm?=JAV9ceXl713 -R2 -!s105 VX_dcache_request_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -Z13 !s108 1572060862.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_request_inter.v| -!i113 0 -R7 -R8 -n@v@x_dcache_request_inter -YVX_dcache_response_inter -R0 -Z14 !s110 1572060863 -!i10b 1 -!s100 H9LFf[:T8ZFdGUznKiDN_2 -IZ1aNoi`DU3KPgF;LQFF[`3 -R2 -!s105 VX_dcache_response_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R13 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_dcache_response_inter.v| -!i113 0 -R7 -R8 -n@v@x_dcache_response_inter -vVX_decode -R0 -Z15 !s110 1572060854 -!i10b 1 -!s100 NVHcmOEV]oO`:ha0UUMGZ2 -I_H?4Go:N4bjfOHiN=@mYC3 -R2 -!s105 VX_decode_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v -L0 4 -R5 -r1 -!s85 0 -31 -Z16 !s108 1572060854.000000 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_decode.v| -!i113 0 -R7 -R8 -n@v@x_decode -vVX_dmem_controller -R0 -R15 -!i10b 1 -!s100 RPQH;KGJ9lb=hPcTmNSPlAOAD3 -R2 -!s105 VX_fetch_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v -L0 4 -R5 -r1 -!s85 0 -31 -!s108 1572060855.000000 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_fetch.v| -!i113 0 -R7 -R8 -n@v@x_fetch -YVX_frE_to_bckE_req_inter -R0 -R14 -!i10b 1 -!s100 9@N3T^SL_K01m@5jA4Nh31 -IFoT0^;QA;]9WTCkS<5_TH2 -R2 -!s105 VX_frE_to_bckE_req_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R17 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_frE_to_bckE_req_inter.v| -!i113 0 -R7 -R8 -n@v@x_fr@e_to_bck@e_req_inter -vVX_front_end -R0 -Z18 !s110 1572060856 -!i10b 1 -!s100 7;7EOV3``ei]nDZMQlPGk0 -I@SFf;nk4B=?86`VOB^@0O0 -R2 -!s105 VX_front_end_v_unit -S1 -R3 -R9 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v -L0 3 -R5 -r1 -!s85 0 -31 -Z19 !s108 1572060856.000000 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_front_end.v| -!i113 0 -R7 -R8 -n@v@x_front_end -vVX_generic_priority_encoder -R0 -R18 -!i10b 1 -!s100 :aK28Kh=@lT9ZCaTamzg>3 -IMZRCchbF_@P0IooMfHhlR3 -R2 -!s105 VX_generic_priority_encoder_v_unit -S1 -R3 -R9 -8/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v -F/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v -L0 1 -R5 -r1 -!s85 0 -31 -R19 -!s107 /nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/VX_generic_priority_encoder.v| -!i113 0 -R7 -R8 -n@v@x_generic_priority_encoder -vVX_generic_register -R0 -R18 -!i10b 1 -!s100 fL2^LczAkWP@cTbY69kFO3 -I@OIJ[h;oQlY1Z]md:O]Ce0 -R2 -!s105 VX_gpr_wspawn_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v -L0 7 -R5 -r1 -!s85 0 -31 -R23 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpr_wspawn_inter.v| -!i113 0 -R7 -R8 -n@v@x_gpr_wspawn_inter -YVX_gpu_inst_req_inter -R0 -R22 -!i10b 1 -!s100 jcVnabg7Ze4Un5[R73S4^3 -IjoUY9Bcc6eGJkkOZN11l21 -R2 -!s105 VX_gpu_inst_req_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v -L0 7 -R5 -r1 -!s85 0 -31 -R23 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_gpu_inst_req_inter.v| -!i113 0 -R7 -R8 -n@v@x_gpu_inst_req_inter -YVX_icache_request_inter -R0 -R22 -!i10b 1 -!s100 0hM8K@;[W3:=Oz64H8G_31 -IaObkPk42UFP9UNAH78DbT1 -R2 -!s105 VX_icache_request_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R23 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_request_inter.v| -!i113 0 -R7 -R8 -n@v@x_icache_request_inter -YVX_icache_response_inter -R0 -Z24 !s110 1572060867 -!i10b 1 -!s100 EB8b2:S0:KXlokE5O?dK70 -IVc;fhnJfHN`bdcOCabTaL2 -R2 -!s105 VX_icache_response_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -Z25 !s108 1572060867.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_icache_response_inter.v| -!i113 0 -R7 -R8 -n@v@x_icache_response_inter -YVX_inst_exec_wb_inter -R0 -R24 -!i10b 1 -!s100 nOge=]_K`4;kMhR7eddR60 -I=THghFo4g^GNl149SNfhR0 -R2 -!s105 VX_inst_exec_wb_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R25 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_exec_wb_inter.v| -!i113 0 -R7 -R8 -n@v@x_inst_exec_wb_inter -YVX_inst_mem_wb_inter -R0 -R24 -!i10b 1 -!s100 8:P3XhBMD@mALW[^O64lH0 -IeJ;ki1@RDNUj1 -R2 -!s105 VX_inst_mem_wb_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R25 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_mem_wb_inter.v| -!i113 0 -R7 -R8 -n@v@x_inst_mem_wb_inter -YVX_inst_meta_inter -R0 -R24 -!i10b 1 -!s100 dUY[BFW==7aoDdYzOfX4T0 -I_jRGl<^:B27il66X2?N?M2 -R2 -!s105 VX_inst_meta_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v -L0 7 -R5 -r1 -!s85 0 -31 -R25 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_inst_meta_inter.v| -!i113 0 -R7 -R8 -n@v@x_inst_meta_inter -YVX_jal_response_inter -R0 -Z26 !s110 1572060868 -!i10b 1 -!s100 a2a9H52CnaVl9oW5Ta^3L1 -Im?4OnRiS;gYggKBh2NDQM0 -R2 -!s105 VX_jal_response_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -Z27 !s108 1572060868.000000 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_jal_response_inter.v| -!i113 0 -R7 -R8 -n@v@x_jal_response_inter -YVX_join_inter -R0 -R26 -!i10b 1 -!s100 nCBXlS2G:6=Q[XaVm;MOX2 -INlTJiDP]L4?d^[:lobD6Be0CP2 -I`l^EVY@lSGhGG6g9@;0 -R2 -!s105 VX_lsu_req_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R27 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_lsu_req_inter.v| -!i113 0 -R7 -R8 -n@v@x_lsu_req_inter -YVX_mem_req_inter -R0 -R26 -!i10b 1 -!s100 FO>D61ZR=8=Q2 -R2 -!s105 VX_mem_req_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v -L0 7 -R5 -r1 -!s85 0 -31 -R27 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_mem_req_inter.v| -!i113 0 -R7 -R8 -n@v@x_mem_req_inter -YVX_mw_wb_inter -R0 -Z28 !s110 1572060869 -!i10b 1 -!s100 [0[Le^MnRRZA8ZL;OHdo3z8B05JoaadD_3 -R2 -!s105 VX_wstall_inter_v_unit -S1 -R3 -R4 -8/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v -F/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v -L0 8 -R5 -r1 -!s85 0 -31 -R29 -!s107 ../VX_define.v|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v| -!s90 -reportprogress|300|-work|work|-vopt|-sv|-stats=none|/nethome/felsabbagh3/research/Vortex/rtl/interfaces/VX_wstall_inter.v| -!i113 0 -R7 -R8 -n@v@x_wstall_inter diff --git a/hw/old_rtl/modelsim/work/_lib.qdb b/hw/old_rtl/modelsim/work/_lib.qdb deleted file mode 100644 index 4c2a9642..00000000 Binary files a/hw/old_rtl/modelsim/work/_lib.qdb and /dev/null differ diff --git a/hw/old_rtl/modelsim/work/_lib1_0.qdb b/hw/old_rtl/modelsim/work/_lib1_0.qdb deleted file mode 100644 index 5a944de5..00000000 Binary files a/hw/old_rtl/modelsim/work/_lib1_0.qdb and /dev/null differ diff --git a/hw/old_rtl/modelsim/work/_lib1_0.qpg b/hw/old_rtl/modelsim/work/_lib1_0.qpg deleted file mode 100644 index 913607dc..00000000 Binary files a/hw/old_rtl/modelsim/work/_lib1_0.qpg and /dev/null differ diff --git a/hw/old_rtl/modelsim/work/_lib1_0.qtl b/hw/old_rtl/modelsim/work/_lib1_0.qtl deleted file mode 100644 index d0d62306..00000000 Binary files a/hw/old_rtl/modelsim/work/_lib1_0.qtl and /dev/null differ diff --git a/hw/old_rtl/modelsim/work/_vmake b/hw/old_rtl/modelsim/work/_vmake deleted file mode 100644 index 37aa36a8..00000000 --- a/hw/old_rtl/modelsim/work/_vmake +++ /dev/null @@ -1,4 +0,0 @@ -m255 -K4 -z0 -cModel Technology diff --git a/hw/old_rtl/quartus/Makefile b/hw/old_rtl/quartus/Makefile deleted file mode 100644 index 7e3e5f25..00000000 --- a/hw/old_rtl/quartus/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -PROJECT = Vortex -TOP_LEVEL_ENTITY = Vortex -SRC_FILE = Vortex.v -PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf - -# Part, Family -FAMILY = "Arria 10" -DEVICE = 10AX115N4F45I3SG - -# Executable Configuration -SYN_ARGS = --read_settings_files=on -FIT_ARGS = --part=$(DEVICE) --read_settings_files=on -ASM_ARGS = -STA_ARGS = --do_report_timing - -# Build targets -all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt - -syn: smart.log $(PROJECT).syn.rpt - -fit: smart.log $(PROJECT).fit.rpt - -asm: smart.log $(PROJECT).asm.rpt - -sta: smart.log $(PROJECT).sta.rpt - -smart: smart.log - -# Target implementations -STAMP = echo done > - -$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES) - /tools/reconfig/intel/18.0/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS) - $(STAMP) fit.chg - -$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt - /tools/reconfig/intel/18.0/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS) - $(STAMP) asm.chg - $(STAMP) sta.chg - -$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt - /tools/reconfig/intel/18.0/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS) - -$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt - /tools/reconfig/intel/18.0/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS) - -smart.log: $(PROJECT_FILES) - /tools/reconfig/intel/18.0/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log - -# Project initialization -$(PROJECT_FILES): - /tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc - -syn.chg: - $(STAMP) syn.chg - -fit.chg: - $(STAMP) fit.chg - -sta.chg: - $(STAMP) sta.chg - -asm.chg: - $(STAMP) asm.chg - -program: $(PROJECT).sof - quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof" - -clean: - rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox diff --git a/hw/old_rtl/quartus/VX_gpr_syn.qpf b/hw/old_rtl/quartus/VX_gpr_syn.qpf deleted file mode 100644 index 8938d2a9..00000000 --- a/hw/old_rtl/quartus/VX_gpr_syn.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition -# Date created = 00:18:19 September 11, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "18.0" -DATE = "00:18:19 September 11, 2019" - -# Revisions - -PROJECT_REVISION = "VX_gpr_syn" diff --git a/hw/old_rtl/quartus/VX_gpr_syn.qsf b/hw/old_rtl/quartus/VX_gpr_syn.qsf deleted file mode 100644 index 26b4649b..00000000 --- a/hw/old_rtl/quartus/VX_gpr_syn.qsf +++ /dev/null @@ -1,63 +0,0 @@ -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition" -set_global_assignment -name FAMILY "Arria 10" -set_global_assignment -name DEVICE 10AX115N4F45I3SG -set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn -set_global_assignment -name SEARCH_PATH ../ -set_global_assignment -name VERILOG_FILE ../VX_define.v -set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v -set_global_assignment -name VERILOG_FILE ../VX_alu.v -set_global_assignment -name VERILOG_FILE ../VX_back_end.v -set_global_assignment -name VERILOG_FILE ../VX_context.v -set_global_assignment -name VERILOG_FILE ../VX_context_slave.v -set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v -set_global_assignment -name VERILOG_FILE ../VX_decode.v -set_global_assignment -name VERILOG_FILE ../VX_execute.v -set_global_assignment -name VERILOG_FILE ../VX_fetch.v -set_global_assignment -name VERILOG_FILE ../VX_forwarding.v -set_global_assignment -name VERILOG_FILE ../VX_front_end.v -set_global_assignment -name VERILOG_FILE ../VX_generic_register.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v -set_global_assignment -name VERILOG_FILE ../VX_memory.v -set_global_assignment -name VERILOG_FILE ../VX_register_file.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v -set_global_assignment -name VERILOG_FILE ../VX_warp.v -set_global_assignment -name VERILOG_FILE ../VX_writeback.v -set_global_assignment -name VERILOG_FILE ../Vortex.v -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL diff --git a/hw/old_rtl/quartus/asm.chg b/hw/old_rtl/quartus/asm.chg deleted file mode 100644 index 19f86f49..00000000 --- a/hw/old_rtl/quartus/asm.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/hw/old_rtl/quartus/fit.chg b/hw/old_rtl/quartus/fit.chg deleted file mode 100644 index 19f86f49..00000000 --- a/hw/old_rtl/quartus/fit.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/hw/old_rtl/quartus/map.chg b/hw/old_rtl/quartus/map.chg deleted file mode 100644 index d155914e..00000000 --- a/hw/old_rtl/quartus/map.chg +++ /dev/null @@ -1 +0,0 @@ -Wed Sep 11 00:18:22 2019 diff --git a/hw/old_rtl/quartus/project.tcl b/hw/old_rtl/quartus/project.tcl deleted file mode 100644 index 49e1d8ac..00000000 --- a/hw/old_rtl/quartus/project.tcl +++ /dev/null @@ -1,88 +0,0 @@ -package require cmdline - -set options { \ - { "project.arg" "" "Project name" } \ - { "family.arg" "" "Device family name" } \ - { "device.arg" "" "Device name" } \ - { "top.arg" "" "Top level module" } \ - { "sdc.arg" "" "Timing Design Constraints file" } \ - { "src.arg" "" "Verilog source file" } \ -} - -array set opts [::cmdline::getoptions quartus(args) $options] - -project_new $opts(project) -overwrite - -set_global_assignment -name FAMILY $opts(family) -set_global_assignment -name DEVICE $opts(device) -set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) - -set_global_assignment -name SEARCH_PATH ../ - -set_global_assignment -name VERILOG_FILE ../VX_define.v - -set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v - -set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v -set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v - -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v -set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v - -set_global_assignment -name VERILOG_FILE ../VX_alu.v -set_global_assignment -name VERILOG_FILE ../VX_back_end.v -set_global_assignment -name VERILOG_FILE ../VX_context.v -set_global_assignment -name VERILOG_FILE ../VX_context_slave.v -set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v -set_global_assignment -name VERILOG_FILE ../VX_decode.v -set_global_assignment -name VERILOG_FILE ../VX_define.v -set_global_assignment -name VERILOG_FILE ../VX_execute.v -set_global_assignment -name VERILOG_FILE ../VX_fetch.v -set_global_assignment -name VERILOG_FILE ../VX_forwarding.v -set_global_assignment -name VERILOG_FILE ../VX_front_end.v -set_global_assignment -name VERILOG_FILE ../VX_generic_register.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v -set_global_assignment -name VERILOG_FILE ../VX_memory.v -set_global_assignment -name VERILOG_FILE ../VX_register_file.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v -set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v -set_global_assignment -name VERILOG_FILE ../VX_warp.v -set_global_assignment -name VERILOG_FILE ../VX_writeback.v -set_global_assignment -name VERILOG_FILE ../Vortex.v - -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL - -project_close - -# set_global_assignment -name VERILOG_FILE $opts(src) - diff --git a/hw/old_rtl/quartus/smart.log b/hw/old_rtl/quartus/smart.log deleted file mode 100644 index 540778b5..00000000 --- a/hw/old_rtl/quartus/smart.log +++ /dev/null @@ -1,27 +0,0 @@ -Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support. -Info: ******************************************************************* -Info: Running Quartus Prime Shell - Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition - Info: Copyright (C) 2018 Intel Corporation. All rights reserved. - Info: Your use of Intel Corporation's design tools, logic functions - Info: and other software and tools, and its AMPP partner logic - Info: functions, and any output files from any of the foregoing - Info: (including device programming or simulation files), and any - Info: associated documentation or information are expressly subject - Info: to the terms and conditions of the Intel Program License - Info: Subscription Agreement, the Intel Quartus Prime License Agreement, - Info: the Intel FPGA IP License Agreement, or other applicable license - Info: agreement, including, without limitation, that your use is for - Info: the sole purpose of programming logic devices manufactured by - Info: Intel and sold by Intel or its authorized distributors. Please - Info: refer to the applicable agreement for further details. - Info: Processing started: Wed Sep 11 00:18:22 2019 -Info: Command: quartus_sh --determine_smart_action VX_gpr_syn -Info: Quartus(args): VX_gpr_syn -Info: SMART_ACTION = SOURCE -Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful -Info: Quartus Prime Shell was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 687 megabytes - Info: Processing ended: Wed Sep 11 00:18:22 2019 - Info: Elapsed time: 00:00:00 - Info: Total CPU time (on all processors): 00:00:00 diff --git a/hw/old_rtl/quartus/sta.chg b/hw/old_rtl/quartus/sta.chg deleted file mode 100644 index 19f86f49..00000000 --- a/hw/old_rtl/quartus/sta.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/hw/old_rtl/quartus/syn.chg b/hw/old_rtl/quartus/syn.chg deleted file mode 100644 index 19f86f49..00000000 --- a/hw/old_rtl/quartus/syn.chg +++ /dev/null @@ -1 +0,0 @@ -done diff --git a/hw/old_rtl/quartus/vortex.ini b/hw/old_rtl/quartus/vortex.ini deleted file mode 100644 index e2fb4516..00000000 --- a/hw/old_rtl/quartus/vortex.ini +++ /dev/null @@ -1,40 +0,0 @@ -load_package flow - - -set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v -set_global_assignment -name VERILOG_FILE ../VX_gpr.v -set_global_assignment -name SDC_FILE vortex.sdc -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL - -# pins configuration -package require cmdline - -proc make_all_pins_virtual { args } { - - set options {\ - { "exclude.arg" "" "List of signals to exclude" } \ - } - array set opts [::cmdline::getoptions quartus(args) $options] - - remove_all_instance_assignments -name VIRTUAL_PIN - execute_module -tool map - set name_ids [get_names -filter * -node_type pin] - - foreach_in_collection name_id $name_ids { - set pin_name [get_name_info -info full_path $name_id] - - if { -1 == [lsearch -exact $opts(excludes) $pin_name] } { - post_message "Making VIRTUAL_PIN assignment to $pin_name" - set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON - } else { - post_message "Skipping VIRTUAL_PIN assignment to $pin_name" - } - } - export_assignments -} - - -make_all_pins_virtual -exclude { clk, reset } \ No newline at end of file diff --git a/hw/old_rtl/quartus/vortex.sdc b/hw/old_rtl/quartus/vortex.sdc deleted file mode 100644 index eafe4ff7..00000000 --- a/hw/old_rtl/quartus/vortex.sdc +++ /dev/null @@ -1 +0,0 @@ -create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] diff --git a/hw/old_rtl/simulate/VX_define.h b/hw/old_rtl/simulate/VX_define.h deleted file mode 100644 index ed10c77f..00000000 --- a/hw/old_rtl/simulate/VX_define.h +++ /dev/null @@ -1,100 +0,0 @@ -#define NT 4 -#define NT_M1 (NT-1) - -#define NW 8 - -#define CACHE_NUM_BANKS 8 -#define CACHE_WORDS_PER_BLOCK 4 - -#define R_INST 51 -#define L_INST 3 -#define ALU_INST 19 -#define S_INST 35 -#define B_INST 99 -#define LUI_INST 55 -#define AUIPC_INST 23 -#define JAL_INST 111 -#define JALR_INST 103 -#define SYS_INST 115 - - -#define WB_ALU 1 -#define WB_MEM 2 -#define WB_JAL 3 -#define NO_WB 0 - - -#define RS2_IMMED 1 -#define RS2_REG 0 - - -#define NO_MEM_READ 7 -#define LB_MEM_READ 0 -#define LH_MEM_READ 1 -#define LW_MEM_READ 2 -#define LBU_MEM_READ 4 -#define LHU_MEM_READ 5 - - -#define NO_MEM_WRITE 7 -#define SB_MEM_WRITE 0 -#define SH_MEM_WRITE 1 -#define SW_MEM_WRITE 2 - - -#define NO_BRANCH 0 -#define BEQ 1 -#define BNE 2 -#define BLT 3 -#define BGT 4 -#define BLTU 5 -#define BGTU 6 - - -#define NO_ALU 15 -#define ADD 0 -#define SUB 1 -#define SLLA 2 -#define SLT 3 -#define SLTU 4 -#define XOR 5 -#define SRL 6 -#define SRA 7 -#define OR 8 -#define AND 9 -#define SUBU 10 -#define LUI_ALU 11 -#define AUIPC_ALU 12 -#define CSR_ALU_RW 13 -#define CSR_ALU_RS 14 -#define CSR_ALU_RC 15 - - - -// WRITEBACK -#define WB_ALU 1 -#define WB_MEM 2 -#define WB_JAL 3 -#define NO_WB 0 - - -// JAL -#define JUMP 1 -#define NO_JUMP 0 - -// STALLS -#define STALL 1 -#define NO_STALL 0 - - -#define TAKEN 1 -#define NOT_TAKEN 0 - - -#define ZERO_REG 0 - - -// COLORS -#define GREEN "\033[32m" -#define RED "\033[31m" -#define DEFAULT "\033[39m" diff --git a/hw/old_rtl/simulate/ram.h b/hw/old_rtl/simulate/ram.h deleted file mode 100644 index 13f78e94..00000000 --- a/hw/old_rtl/simulate/ram.h +++ /dev/null @@ -1,245 +0,0 @@ -#ifndef __RAM__ - -#define __RAM__ - -// #include "string.h" -#include -#include -// #include - -// #define NULL 0 - -class RAM; - -uint32_t hti(char); -uint32_t hToI(char *, uint32_t); -void loadHexImpl(char *,RAM*); - -class RAM{ -public: - uint8_t* mem[1 << 12]; - - RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL; - } - ~RAM(){ - for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i]; - } - - void clear(){ - for(uint32_t i = 0;i < (1 << 12);i++) - { - if(mem[i]) - { - delete mem[i]; - mem[i] = NULL; - } - } - } - - uint8_t* get(uint32_t address){ - - if(mem[address >> 20] == NULL) { - uint8_t* ptr = new uint8_t[1024*1024]; - for(uint32_t i = 0;i < 1024*1024;i+=4) { - ptr[i + 0] = 0x00; - ptr[i + 1] = 0x00; - ptr[i + 2] = 0x00; - ptr[i + 3] = 0x00; - } - mem[address >> 20] = ptr; - } - return &mem[address >> 20][address & 0xFFFFF]; - } - - void read(uint32_t address,uint32_t length, uint8_t *data){ - for(unsigned i = 0;i < length;i++){ - data[i] = (*this)[address + i]; - } - } - - void write(uint32_t address,uint32_t length, uint8_t *data){ - for(unsigned i = 0;i < length;i++){ - (*this)[address + i] = data[i]; - } - } - - void getBlock(uint32_t address, uint8_t *data) - { - uint32_t block_number = address & 0xffffff00; // To zero out block offset - uint32_t bytes_num = 256; - - this->read(block_number, bytes_num, data); - } - - void getWord(uint32_t address, uint32_t * data) - { - data[0] = 0; - - uint8_t first = *get(address + 0); - uint8_t second = *get(address + 1); - uint8_t third = *get(address + 2); - uint8_t fourth = *get(address + 3); - - // uint8_t hi = (uint8_t) *get(address + 0); - // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 1); - // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 2); - // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n"; - // hi = (uint8_t) *get(address + 3); - // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n"; - - data[0] = (data[0] << 0) | fourth; - data[0] = (data[0] << 8) | third; - data[0] = (data[0] << 8) | second; - data[0] = (data[0] << 8) | first; - - } - - void writeWord(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - for (int i = 0; i < 4; i++) - { - // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; - // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; - // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; - (*this)[address + i] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - } - } - - void writeHalf(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - for (int i = 0; i < 2; i++) - { - // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n"; - // std::cout << "RAM: DATA TO MASK " << byte_mask << "\n"; - // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n"; - (*this)[address + i] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - } - } - - void writeByte(uint32_t address, uint32_t * data) - { - uint32_t data_to_write = *data; - - uint32_t byte_mask = 0xFF; - - (*this)[address] = data_to_write & byte_mask; - data_to_write = data_to_write >> 8; - - } - - uint8_t& operator [](uint32_t address) { - return *get(address); - } - -}; - - -// MEMORY UTILS - -uint32_t hti(char c) { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; -} - -uint32_t hToI(char *c, uint32_t size) { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti(c[i]) << ((size - i - 1) * 4); - } - return value; -} - - - -void loadHexImpl(const char *path, RAM* mem) { - mem->clear(); - FILE *fp = fopen(path, "r"); - if(fp == 0){ - printf("Path not found %s\n", path); - return; - // std::cout << path << " not found" << std::endl; - } - //Preload 0x0 <-> 0x80000000 jumps - ((uint32_t*)mem->get(0))[1] = 0xf1401073; - - ((uint32_t*)mem->get(0))[2] = 0x30101073; - - ((uint32_t*)mem->get(0))[3] = 0x800000b7; - ((uint32_t*)mem->get(0))[4] = 0x000080e7; - - ((uint32_t*)mem->get(0x80000000))[0] = 0x00000097; - - ((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023; - // F00FFF10 - ((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678; - - - - - fseek(fp, 0, SEEK_END); - uint32_t size = ftell(fp); - fseek(fp, 0, SEEK_SET); - char* content = new char[size]; - fread(content, 1, size, fp); - - int offset = 0; - char* line = content; - // std::cout << "WHTA\n"; - while (1) { - if (line[0] == ':') { - uint32_t byteCount = hToI(line + 1, 2); - uint32_t nextAddr = hToI(line + 3, 4) + offset; - uint32_t key = hToI(line + 7, 2); - switch (key) { - case 0: - for (uint32_t i = 0; i < byteCount; i++) { - - unsigned add = nextAddr + i; - - *(mem->get(add)) = hToI(line + 9 + i * 2, 2); - } - break; - case 2: -// cout << offset << endl; - offset = hToI(line + 9, 4) << 4; - break; - case 4: -// cout << offset << endl; - offset = hToI(line + 9, 4) << 16; - break; - default: -// cout << "??? " << key << endl; - break; - } - } - - while (*line != '\n' && size != 0) { - line++; - size--; - } - if (size <= 1) - break; - line++; - size--; - } - - if (content) delete[] content; -} - -#endif \ No newline at end of file diff --git a/hw/old_rtl/simulate/tb_debug.h b/hw/old_rtl/simulate/tb_debug.h deleted file mode 100644 index 711663cc..00000000 --- a/hw/old_rtl/simulate/tb_debug.h +++ /dev/null @@ -1 +0,0 @@ -#define VCD_OFF diff --git a/hw/old_rtl/simulate/test_bench.cpp b/hw/old_rtl/simulate/test_bench.cpp deleted file mode 100644 index 2becfb89..00000000 --- a/hw/old_rtl/simulate/test_bench.cpp +++ /dev/null @@ -1,105 +0,0 @@ -#include "test_bench.h" - -#define NUM_TESTS 46 - -int main(int argc, char **argv) -{ - - // Verilated::debug(1); - - Verilated::commandArgs(argc, argv); - - Verilated::traceEverOn(true); - - -#define ALL_TESTS -#ifdef ALL_TESTS - bool passed = true; - std::string tests[NUM_TESTS] = { - "../../emulator/riscv_tests/rv32ui-p-add.hex", - "../../emulator/riscv_tests/rv32ui-p-addi.hex", - "../../emulator/riscv_tests/rv32ui-p-and.hex", - "../../emulator/riscv_tests/rv32ui-p-andi.hex", - "../../emulator/riscv_tests/rv32ui-p-auipc.hex", - "../../emulator/riscv_tests/rv32ui-p-beq.hex", - "../../emulator/riscv_tests/rv32ui-p-bge.hex", - "../../emulator/riscv_tests/rv32ui-p-bgeu.hex", - "../../emulator/riscv_tests/rv32ui-p-blt.hex", - "../../emulator/riscv_tests/rv32ui-p-bltu.hex", - "../../emulator/riscv_tests/rv32ui-p-bne.hex", - "../../emulator/riscv_tests/rv32ui-p-jal.hex", - "../../emulator/riscv_tests/rv32ui-p-jalr.hex", - "../../emulator/riscv_tests/rv32ui-p-lb.hex", - "../../emulator/riscv_tests/rv32ui-p-lbu.hex", - "../../emulator/riscv_tests/rv32ui-p-lh.hex", - "../../emulator/riscv_tests/rv32ui-p-lhu.hex", - "../../emulator/riscv_tests/rv32ui-p-lui.hex", - "../../emulator/riscv_tests/rv32ui-p-lw.hex", - "../../emulator/riscv_tests/rv32ui-p-or.hex", - "../../emulator/riscv_tests/rv32ui-p-ori.hex", - "../../emulator/riscv_tests/rv32ui-p-sb.hex", - "../../emulator/riscv_tests/rv32ui-p-sh.hex", - "../../emulator/riscv_tests/rv32ui-p-simple.hex", - "../../emulator/riscv_tests/rv32ui-p-sll.hex", - "../../emulator/riscv_tests/rv32ui-p-slli.hex", - "../../emulator/riscv_tests/rv32ui-p-slt.hex", - "../../emulator/riscv_tests/rv32ui-p-slti.hex", - "../../emulator/riscv_tests/rv32ui-p-sltiu.hex", - "../../emulator/riscv_tests/rv32ui-p-sltu.hex", - "../../emulator/riscv_tests/rv32ui-p-sra.hex", - "../../emulator/riscv_tests/rv32ui-p-srai.hex", - "../../emulator/riscv_tests/rv32ui-p-srl.hex", - "../../emulator/riscv_tests/rv32ui-p-srli.hex", - "../../emulator/riscv_tests/rv32ui-p-sub.hex", - "../../emulator/riscv_tests/rv32ui-p-sw.hex", - "../../emulator/riscv_tests/rv32ui-p-xor.hex", - "../../emulator/riscv_tests/rv32ui-p-xori.hex", - "../../emulator/riscv_tests/rv32um-p-div.hex", - "../../emulator/riscv_tests/rv32um-p-divu.hex", - "../../emulator/riscv_tests/rv32um-p-mul.hex", - "../../emulator/riscv_tests/rv32um-p-mulh.hex", - "../../emulator/riscv_tests/rv32um-p-mulhsu.hex", - "../../emulator/riscv_tests/rv32um-p-mulhu.hex", - "../../emulator/riscv_tests/rv32um-p-rem.hex", - "../../emulator/riscv_tests/rv32um-p-remu.hex" - }; - - for (std::string s : tests) { - Vortex v; - - std::cerr << s << std::endl; - - bool curr = v.simulate(s); - if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl; - passed = passed && curr; - } - - if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; - if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; - - return !passed; - - #else - - char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex"; - Vortex v; - const char *testing; - - if (argc >= 2) { - testing = argv[1]; - } else { - testing = "../../kernel/vortex_test.hex"; - } - - std::cerr << testing << std::endl; - - - bool curr = v.simulate(testing); - if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; - if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; - - return !curr; - -#endif -} diff --git a/hw/old_rtl/simulate/test_bench.h b/hw/old_rtl/simulate/test_bench.h deleted file mode 100644 index 3a001377..00000000 --- a/hw/old_rtl/simulate/test_bench.h +++ /dev/null @@ -1,433 +0,0 @@ -// C++ libraries -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "VX_define.h" -#include "ram.h" -#include "VVortex.h" -#include "verilated.h" - -#include "tb_debug.h" - -#ifdef VCD_OUTPUT -#include -#endif - -unsigned long time_stamp = 0; - -double sc_time_stamp() -{ - return time_stamp / 1000.0; -} - -class Vortex -{ - public: - Vortex(); - ~Vortex(); - bool simulate(std::string); - private: - void ProcessFile(void); - void print_stats(bool = true); - bool ibus_driver(); - bool dbus_driver(); - void io_handler(); - - RAM ram; - - VVortex * vortex; - - unsigned start_pc; - bool refill_d; - unsigned refill_addr_d; - bool refill_i; - unsigned refill_addr_i; - long int curr_cycle; - bool stop; - bool unit_test; - std::string instruction_file_name; - std::ofstream results; - int stats_static_inst; - int stats_dynamic_inst; - int stats_total_cycles; - int stats_fwd_stalls; - int stats_branch_stalls; - int debug_state; - int ibus_state; - int dbus_state; - int debug_return; - int debug_wait_num; - int debug_inst_num; - int debug_end_wait; - int debug_debugAddr; - double stats_sim_time; - #ifdef VCD_OUTPUT - VerilatedVcdC *m_trace; - #endif -}; - - - -Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1), - stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0), - debug_state(0), ibus_state(0), dbus_state(0), debug_return(0), - debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) -{ - this->vortex = new VVortex; - #ifdef VCD_OUTPUT - this->m_trace = new VerilatedVcdC; - this->vortex->trace(m_trace, 99); - this->m_trace->open("trace.vcd"); - #endif - this->results.open("../results.txt"); -} - -Vortex::~Vortex() -{ - #ifdef VCD_OUTPUT - m_trace->close(); - #endif - this->results.close(); - delete this->vortex; -} - - -void Vortex::ProcessFile(void) -{ - loadHexImpl(this->instruction_file_name.c_str(), &this->ram); -} - -void Vortex::print_stats(bool cycle_test) -{ - - if (cycle_test) - { - this->results << std::left; - // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; - this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; - this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; - this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - else - { - this->results << std::left; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - - - uint32_t status; - ram.getWord(0, &status); - - if (this->unit_test) - { - if (status == 1) - { - this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; - } else - { - this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; - } - } - else - { - this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; - } - - this->stats_static_inst = 0; - this->stats_dynamic_inst = -1; - this->stats_total_cycles = 0; - this->stats_fwd_stalls = 0; - this->stats_branch_stalls = 0; - -} - -bool Vortex::ibus_driver() -{ - - vortex->i_m_ready_i = false; - - { - - // int dcache_num_words_per_block - - if (refill_i) - { - refill_i = false; - vortex->i_m_ready_i = true; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; - unsigned curr_addr = refill_addr_i + (4*curr_index); - - unsigned curr_value; - ram.getWord(curr_addr, &curr_value); - - vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value; - - } - } - } - else - { - if (vortex->o_m_valid_i) - { - - if (vortex->o_m_read_or_write_i) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - unsigned base_addr = vortex->o_m_evict_addr_i; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank; - unsigned curr_addr = base_addr + (4*curr_index); - - unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word]; - - ram.writeWord( curr_addr, &curr_value); - } - } - } - - // Respond next cycle - refill_i = true; - refill_addr_i = vortex->o_m_read_addr_i; - } - } - - } - - - return false; - -} - -void Vortex::io_handler() -{ - if (vortex->io_valid) - { - uint32_t data_write = (uint32_t) vortex->io_data; - - char c = (char) data_write; - std::cerr << c; - // std::cout << c; - } -} - - -bool Vortex::dbus_driver() -{ - - vortex->i_m_ready_d = false; - - { - - // int dcache_num_words_per_block - - if (refill_d) - { - refill_d = false; - vortex->i_m_ready_d = true; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; - unsigned curr_addr = refill_addr_d + (4*curr_index); - - unsigned curr_value; - ram.getWord(curr_addr, &curr_value); - - vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value; - - } - } - } - else - { - if (vortex->o_m_valid_d) - { - - if (vortex->o_m_read_or_write_d) - { - // fprintf(stderr, "++++++++++++++++++++++++++++++++\n"); - unsigned base_addr = vortex->o_m_evict_addr_d; - - for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++) - { - for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++) - { - unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank; - unsigned curr_addr = base_addr + (4*curr_index); - - unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word]; - - ram.writeWord( curr_addr, &curr_value); - } - } - } - - // Respond next cycle - refill_d = true; - refill_addr_d = vortex->o_m_read_addr_d; - } - } - - } - - - return false; -} - - - -bool Vortex::simulate(std::string file_to_simulate) -{ - - this->instruction_file_name = file_to_simulate; - // this->results << "\n****************\t" << file_to_simulate << "\t****************\n"; - - this->ProcessFile(); - - // auto start_time = std::chrono::high_resolution_clock::now(); - - - static bool stop = false; - static int counter = 0; - counter = 0; - stop = false; - - // auto start_time = clock(); - - - // vortex->reset = 1; - - - // vortex->reset = 0; - - unsigned curr_inst; - unsigned new_PC; - - // while (this->stop && (!(stop && (counter > 5)))) - // { - - // // std::cout << "************* Cycle: " << cycle << "\n"; - // bool istop = ibus_driver(); - // bool dstop = !dbus_driver(); - - // vortex->clk = 1; - // vortex->eval(); - - - - // vortex->clk = 0; - // vortex->eval(); - - - // stop = istop && dstop; - - // if (stop) - // { - // counter++; - // } else - // { - // counter = 0; - // } - - // cycle++; - // } - - bool istop; - bool dstop; - bool cont = false; - // for (int i = 0; i < 500; i++) - - vortex->reset = 1; - vortex->clk = 0; - vortex->eval(); - // m_trace->dump(10); - vortex->reset = 1; - vortex->clk = 1; - vortex->eval(); - // m_trace->dump(11); - vortex->reset = 0; - vortex->clk = 0; - - // unsigned cycles; - counter = 0; - this->stats_total_cycles = 12; - while (this->stop && ((counter < 5))) - // while (this->stats_total_cycles < 10) - { - - // printf("-------------------------\n"); - // std::cout << "Counter: " << counter << "\n"; - // if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n"; - // dstop = !dbus_driver(); - #ifdef VCD_OUTPUT - m_trace->dump(2*this->stats_total_cycles); - #endif - vortex->clk = 1; - vortex->eval(); - istop = ibus_driver(); - dstop = !dbus_driver(); - io_handler(); - - #ifdef VCD_OUTPUT - m_trace->dump((2*this->stats_total_cycles)+1); - #endif - vortex->clk = 0; - vortex->eval(); - // stop = istop && dstop; - stop = vortex->out_ebreak; - - if (stop || cont) - // if (istop) - { - cont = true; - counter++; - } else - { - counter = 0; - } - - ++time_stamp; - ++stats_total_cycles; - } - - std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n"; - - int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf; - - // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n"; - - // std::cout << "Something: " << result << '\n'; - - // uint32_t status; - // ram.getWord(0, &status); - - this->print_stats(); - - - - return (status == 1); - // return (1 == 1); -} \ No newline at end of file diff --git a/hw/rtl/VX_cache/VX_bank.v b/hw/rtl/generic_cache/VX_bank.v similarity index 100% rename from hw/rtl/VX_cache/VX_bank.v rename to hw/rtl/generic_cache/VX_bank.v diff --git a/hw/rtl/VX_cache/VX_cache.v b/hw/rtl/generic_cache/VX_cache.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache.v rename to hw/rtl/generic_cache/VX_cache.v diff --git a/hw/rtl/VX_cache/VX_cache_config.v b/hw/rtl/generic_cache/VX_cache_config.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_config.v rename to hw/rtl/generic_cache/VX_cache_config.v diff --git a/hw/rtl/VX_cache/VX_cache_core_req_bank_sel.v b/hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_core_req_bank_sel.v rename to hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v diff --git a/hw/rtl/VX_cache/VX_cache_dfq_queue.v b/hw/rtl/generic_cache/VX_cache_dfq_queue.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_dfq_queue.v rename to hw/rtl/generic_cache/VX_cache_dfq_queue.v diff --git a/hw/rtl/VX_cache/VX_cache_dram_req_arb.v b/hw/rtl/generic_cache/VX_cache_dram_req_arb.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_dram_req_arb.v rename to hw/rtl/generic_cache/VX_cache_dram_req_arb.v diff --git a/hw/rtl/VX_cache/VX_cache_miss_resrv.v b/hw/rtl/generic_cache/VX_cache_miss_resrv.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_miss_resrv.v rename to hw/rtl/generic_cache/VX_cache_miss_resrv.v diff --git a/hw/rtl/VX_cache/VX_cache_req_queue.v b/hw/rtl/generic_cache/VX_cache_req_queue.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_req_queue.v rename to hw/rtl/generic_cache/VX_cache_req_queue.v diff --git a/hw/rtl/VX_cache/VX_cache_wb_sel_merge.v b/hw/rtl/generic_cache/VX_cache_wb_sel_merge.v similarity index 100% rename from hw/rtl/VX_cache/VX_cache_wb_sel_merge.v rename to hw/rtl/generic_cache/VX_cache_wb_sel_merge.v diff --git a/hw/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v b/hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v similarity index 100% rename from hw/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v rename to hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v diff --git a/hw/rtl/VX_cache/VX_fill_invalidator.v b/hw/rtl/generic_cache/VX_fill_invalidator.v similarity index 100% rename from hw/rtl/VX_cache/VX_fill_invalidator.v rename to hw/rtl/generic_cache/VX_fill_invalidator.v diff --git a/hw/rtl/VX_cache/VX_mrv_queue.v b/hw/rtl/generic_cache/VX_mrv_queue.v similarity index 100% rename from hw/rtl/VX_cache/VX_mrv_queue.v rename to hw/rtl/generic_cache/VX_mrv_queue.v diff --git a/hw/rtl/VX_cache/VX_prefetcher.v b/hw/rtl/generic_cache/VX_prefetcher.v similarity index 100% rename from hw/rtl/VX_cache/VX_prefetcher.v rename to hw/rtl/generic_cache/VX_prefetcher.v diff --git a/hw/rtl/VX_cache/VX_snp_fwd_arb.v b/hw/rtl/generic_cache/VX_snp_fwd_arb.v similarity index 100% rename from hw/rtl/VX_cache/VX_snp_fwd_arb.v rename to hw/rtl/generic_cache/VX_snp_fwd_arb.v diff --git a/hw/rtl/VX_cache/VX_tag_data_access.v b/hw/rtl/generic_cache/VX_tag_data_access.v similarity index 100% rename from hw/rtl/VX_cache/VX_tag_data_access.v rename to hw/rtl/generic_cache/VX_tag_data_access.v diff --git a/hw/rtl/VX_cache/VX_tag_data_structure.v b/hw/rtl/generic_cache/VX_tag_data_structure.v similarity index 100% rename from hw/rtl/VX_cache/VX_tag_data_structure.v rename to hw/rtl/generic_cache/VX_tag_data_structure.v