From 3e64cb43800ec3f4645474d5d361da0f9d0d3edd Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 21 Apr 2020 22:24:05 -0400 Subject: [PATCH] minor update --- hw/rtl/VX_dmem_ctrl.v | 22 +++++++++++----------- hw/rtl/VX_lsu_unit.v | 4 ++-- hw/rtl/Vortex.v | 6 +++--- hw/rtl/cache/VX_cache_dram_req_arb.v | 10 +++++----- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/hw/rtl/VX_dmem_ctrl.v b/hw/rtl/VX_dmem_ctrl.v index ca3edd65..1c1a2e65 100644 --- a/hw/rtl/VX_dmem_ctrl.v +++ b/hw/rtl/VX_dmem_ctrl.v @@ -176,19 +176,19 @@ module VX_dmem_ctrl ( .FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE), .SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES) ) gpu_dcache ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // Core req - .core_req_valid (dcache_req_dcache_if.core_req_valid), - .core_req_read (dcache_req_dcache_if.core_req_read), - .core_req_write (dcache_req_dcache_if.core_req_write), - .core_req_addr (dcache_req_dcache_if.core_req_addr), - .core_req_data (dcache_req_dcache_if.core_req_data), - .core_req_rd (dcache_req_dcache_if.core_req_rd), - .core_req_wb (dcache_req_dcache_if.core_req_wb), - .core_req_warp_num (dcache_req_dcache_if.core_req_warp_num), - .core_req_pc (dcache_req_dcache_if.core_req_pc), + .core_req_valid (dcache_req_dcache_if.core_req_valid), + .core_req_read (dcache_req_dcache_if.core_req_read), + .core_req_write (dcache_req_dcache_if.core_req_write), + .core_req_addr (dcache_req_dcache_if.core_req_addr), + .core_req_data (dcache_req_dcache_if.core_req_data), + .core_req_rd (dcache_req_dcache_if.core_req_rd), + .core_req_wb (dcache_req_dcache_if.core_req_wb), + .core_req_warp_num (dcache_req_dcache_if.core_req_warp_num), + .core_req_pc (dcache_req_dcache_if.core_req_pc), // Can submit core Req .core_req_ready (dcache_req_dcache_if.core_req_ready), diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 4bbff8f6..664833f0 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -15,7 +15,7 @@ module VX_lsu_unit ( ); // Generate Addresses wire[`NUM_THREADS-1:0][31:0] address; - VX_lsu_addr_gen VX_lsu_addr_gen ( + VX_lsu_addr_gen VX_lsu_addr_gen ( .base_address (lsu_req_if.base_address), .offset (lsu_req_if.offset), .address (address) @@ -35,7 +35,7 @@ module VX_lsu_unit ( VX_generic_register #( .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) - ) lsu_buffer( + ) lsu_buffer ( .clk (clk), .reset(reset), .stall(delay), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index bc96636f..afc703d7 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -133,11 +133,11 @@ VX_frE_to_bckE_req_if bckE_req_if(); // New instruction request to EXE/ME // Back-end to Front-end VX_wb_if writeback_if(); // Writeback to GPRs -VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch -VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch +VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch +VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch // Warp controls -VX_warp_ctl_if warp_ctl_if(); +VX_warp_ctl_if warp_ctl_if(); // Cache snooping VX_gpu_snp_req_rsp_if gpu_icache_snp_req_if(); diff --git a/hw/rtl/cache/VX_cache_dram_req_arb.v b/hw/rtl/cache/VX_cache_dram_req_arb.v index bb413bcd..4444d2fe 100644 --- a/hw/rtl/cache/VX_cache_dram_req_arb.v +++ b/hw/rtl/cache/VX_cache_dram_req_arb.v @@ -36,17 +36,17 @@ module VX_cache_dram_req_arb #( parameter LLVQ_SIZE = 16, // Fill Invalidator Size {Fill invalidator must be active} - parameter FILL_INVALIDAOR_SIZE = 16, + parameter FILL_INVALIDAOR_SIZE = 16, // Prefetcher parameter PRFQ_SIZE = 64, parameter PRFQ_STRIDE = 2, -// Dram knobs + // Dram knobs parameter SIMULATED_DRAM_LATENCY_CYCLES = 10 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, // Fill Request output wire dfqq_full, @@ -72,7 +72,7 @@ module VX_cache_dram_req_arb #( wire pref_valid; wire[31:0] pref_addr; - wire dwb_valid; + wire dwb_valid; wire dfqq_req; assign pref_pop = !dwb_valid && !dfqq_req && dram_req_ready && pref_valid;