diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index a177b9db..d0f17edc 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -23,8 +23,8 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DEBUG=1 -SCOPE=1 +#DEBUG=1 +#SCOPE=1 CFLAGS += -fPIC diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index bc57aa39..3d2a388a 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -26,14 +26,14 @@ #define ALLOC_BASE_ADDR 0x10000000 #define LOCAL_MEM_SIZE 0xffffffff -#define CHECK_RES(_expr) \ - do { \ - fpga_result res = _expr; \ - if (res == FPGA_OK) \ - break; \ - printf("[VXDRV] Error: '%s' returned %d, %s!\n", \ - #_expr, (int)res, fpgaErrStr(res)); \ - return -1; \ +#define CHECK_RES(_expr) \ + do { \ + fpga_result res = _expr; \ + if (res == FPGA_OK) \ + break; \ + printf("[VXDRV] Error: '%s' returned %d, %s!\n", \ + #_expr, (int)res, fpgaErrStr(res)); \ + return -1; \ } while (false) /////////////////////////////////////////////////////////////////////////////// @@ -130,39 +130,57 @@ extern int vx_dev_open(vx_device_h* hdevice) { if (nullptr == hdevice) return -1; - fpga_result res; fpga_handle accel_handle; vx_device_t* device; #ifndef USE_VLSIM + fpga_result res; fpga_token accel_token; fpga_properties filter = nullptr; fpga_guid guid; uint32_t num_matches; // Set up a filter that will search for an accelerator - fpgaGetProperties(nullptr, &filter); - fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); + CHECK_RES(fpgaGetProperties(nullptr, &filter)); + res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); + if (res != FPGA_OK) { + fprintf(stderr, "[VXDRV] Error: fpgaGetProperties() returned %d, %s!\n", (int)res, fpgaErrStr(res)); + fpgaDestroyProperties(&filter); + return -1; + } // Add the desired UUID to the filter uuid_parse(AFU_ACCEL_UUID, guid); - fpgaPropertiesSetGUID(filter, guid); + res = fpgaPropertiesSetGUID(filter, guid); + if (res != FPGA_OK) { + fprintf(stderr, "[VXDRV] Error: fpgaPropertiesSetGUID() returned %d, %s!\n", (int)res, fpgaErrStr(res)); + fpgaDestroyProperties(&filter); + return -1; + } // Do the search across the available FPGA contexts num_matches = 1; - fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); + res = fpgaEnumerate(&filter, 1, &accel_token, 1, &num_matches); + if (res != FPGA_OK) { + fprintf(stderr, "[VXDRV] Error: fpgaEnumerate() returned %d, %s!\n", (int)res, fpgaErrStr(res)); + fpgaDestroyProperties(&filter); + return -1; + } // Not needed anymore fpgaDestroyProperties(&filter); if (num_matches < 1) { fprintf(stderr, "[VXDRV] Error: accelerator %s not found!\n", AFU_ACCEL_UUID); + fpgaDestroyToken(&accel_token); return -1; } // Open accelerator res = fpgaOpen(accel_token, &accel_handle, 0); - if (FPGA_OK != res) { + if (res != FPGA_OK) { + fprintf(stderr, "[VXDRV] Error: fpgaOpen() returned %d, %s!\n", (int)res, fpgaErrStr(res)); + fpgaDestroyToken(&accel_token); return -1; } @@ -170,10 +188,7 @@ extern int vx_dev_open(vx_device_h* hdevice) { fpgaDestroyToken(&accel_token); #else // Open accelerator - res = fpgaOpen(NULL, &accel_handle, 0); - if (FPGA_OK != res) { - return -1; - } + CHECK_RES(fpgaOpen(NULL, &accel_handle, 0)); #endif // allocate device object @@ -193,7 +208,7 @@ extern int vx_dev_open(vx_device_h* hdevice) { ret |= vx_csr_get(device, 0, CSR_NC, &device->num_cores); ret |= vx_csr_get(device, 0, CSR_NW, &device->num_warps); ret |= vx_csr_get(device, 0, CSR_NT, &device->num_threads); - if (ret != 0) { + if (ret != FPGA_OK) { fpgaClose(accel_handle); return ret; } diff --git a/driver/opae/vx_scope.cpp b/driver/opae/vx_scope.cpp index 55cce38f..65320c0d 100644 --- a/driver/opae/vx_scope.cpp +++ b/driver/opae/vx_scope.cpp @@ -19,7 +19,7 @@ #include "vortex_afu.h" #include "scope-defs.h" -#define SCOPE_FRAME_WIDTH 1768 +#define FRAME_FLUSH_SIZE 100 #define CHECK_RES(_expr) \ do { \ @@ -233,7 +233,8 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta)); timestamp = print_clock(ofs, delta + 1, timestamp); signal_id = num_taps; - if (0 == (frame_no % 100)) { + if (0 == (frame_no % FRAME_FLUSH_SIZE)) { + ofs << std::flush; std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl; } } diff --git a/hw/opae/README b/hw/opae/README index e05b1df2..ca141072 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -82,6 +82,7 @@ tar -cvjf vortex.vcd.tar.bz2 build_ase_1c/work/vortex.vcd tar -zcvf vortex.vcd.tar.gz build_ase_1c/work/vortex.vcd tar -zcvf run.log.tar.gz build_ase_1c/work/run.log tar -zcvf vx_scope.vcd.tar.gz vx_scope.vcd +tar -cvjf vx_scope.vcd.tar.bz2 vx_scope.vcd # decompress VCD trace tar -zxvf /mnt/c/Users/Blaise/Downloads/vortex.vcd.tar.gz diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 3591b8c2..a8843bc1 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -696,7 +696,7 @@ always @(*) begin af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag); end -assign cci_rd_req_fire = af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull; +assign cci_rd_req_fire = af2cp_sTxPort.c0.valid; assign cci_rd_rsp_fire = (STATE_WRITE == state) && cp2af_sRxPort.c0.rspValid; assign cci_rd_req_tag = CCI_RD_RQ_TAGW'(cci_rd_req_ctr); @@ -738,7 +738,8 @@ always @(posedge clk) begin cci_rd_req_enable <= (STATE_WRITE == state) && (cci_rd_req_ctr_next < cmd_data_size) - && (cci_pending_reads_next < CCI_RD_QUEUE_SIZE); + && (cci_pending_reads_next < CCI_RD_QUEUE_SIZE) + && !cp2af_sRxPort.c0TxAlmFull; if (cci_rd_req_fire) begin cci_rd_req_addr <= cci_rd_req_addr + 1; @@ -822,7 +823,7 @@ always @(*) begin af2cp_sTxPort.c1.data = t_ccip_clData'(avs_rdq_dout); end -assign cci_wr_req_fire = af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull; +assign cci_wr_req_fire = af2cp_sTxPort.c1.valid; assign cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid; assign cci_pending_writes_next = cci_pending_writes @@ -852,7 +853,8 @@ begin end cci_wr_req_enable <= (STATE_READ == state) - && (cci_pending_writes_next < CCI_RW_QUEUE_SIZE); + && (cci_pending_writes_next < CCI_RW_QUEUE_SIZE) + && !cp2af_sRxPort.c1TxAlmFull; if (cci_wr_req_fire) begin assert(cci_wr_req_ctr != 0); @@ -1074,12 +1076,29 @@ end `SCOPE_ASSIGN (ccip_sRxPort_c0_hdr_mdata, cp2af_sRxPort.c0.hdr.mdata); `SCOPE_ASSIGN (ccip_sRxPort_c0_rspValid, cp2af_sRxPort.c0.rspValid); `SCOPE_ASSIGN (ccip_sRxPort_c1_rspValid, cp2af_sRxPort.c1.rspValid); -`SCOPE_ASSIGN (ccip_sTxPort_c0_fire, af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull); +`SCOPE_ASSIGN (ccip_sTxPort_c0_valid, af2cp_sTxPort.c0.valid); `SCOPE_ASSIGN (ccip_sTxPort_c0_hdr_address, af2cp_sTxPort.c0.hdr.address); `SCOPE_ASSIGN (ccip_sTxPort_c0_hdr_mdata, af2cp_sTxPort.c0.hdr.mdata); -`SCOPE_ASSIGN (ccip_sTxPort_c1_fire, af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull); +`SCOPE_ASSIGN (ccip_sTxPort_c1_valid, af2cp_sTxPort.c1.valid); `SCOPE_ASSIGN (ccip_sTxPort_c1_hdr_address, af2cp_sTxPort.c1.hdr.address); `SCOPE_ASSIGN (ccip_sTxPort_c2_mmioRdValid, af2cp_sTxPort.c2.mmioRdValid); +`SCOPE_ASSIGN (ccip_sRxPort_c0TxAlmFull, cp2af_sRxPort.c0TxAlmFull); +`SCOPE_ASSIGN (ccip_sRxPort_c1TxAlmFull, cp2af_sRxPort.c1TxAlmFull); +`SCOPE_ASSIGN (avs_address, avs_address); +`SCOPE_ASSIGN (avs_waitrequest, avs_waitrequest); +`SCOPE_ASSIGN (avs_write_fire, avs_write && !avs_waitrequest); +`SCOPE_ASSIGN (avs_read_fire, avs_read && !avs_waitrequest); +`SCOPE_ASSIGN (avs_byteenable, avs_byteenable); +`SCOPE_ASSIGN (avs_burstcount, avs_burstcount); +`SCOPE_ASSIGN (avs_readdatavalid, avs_readdatavalid); +`SCOPE_ASSIGN (mem_bank_select, mem_bank_select); +`SCOPE_ASSIGN (ccip_dram_rd_req_ctr, cci_dram_rd_req_ctr); +`SCOPE_ASSIGN (ccip_dram_wr_req_ctr, cci_dram_wr_req_ctr); +`SCOPE_ASSIGN (ccip_rd_req_ctr, cci_rd_req_ctr); +`SCOPE_ASSIGN (ccip_rd_rsp_ctr, cci_rd_rsp_ctr); +`SCOPE_ASSIGN (ccip_wr_req_ctr, cci_wr_req_ctr); +`SCOPE_ASSIGN (snp_req_ctr, snp_req_ctr); +`SCOPE_ASSIGN (snp_rsp_ctr, snp_rsp_ctr); wire scope_changed = `SCOPE_TRIGGER; diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 783743ee..e5db8d3c 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -52,7 +52,7 @@ /////////////////////////////////////////////////////////////////////////////// `define USE_FAST_BRAM (* ramstyle="mlab" *) -`define NO_RW_RAM_CHECK (* ramstyle="mlab, no_rw_check" *) +`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 7c32180b..f8de9cea 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -81,12 +81,29 @@ "ccip_sRxPort_c0_hdr_mdata":16, "?ccip_sRxPort_c0_rspValid":1, "?ccip_sRxPort_c1_rspValid":1, - "?ccip_sTxPort_c0_fire":1, + "?ccip_sTxPort_c0_valid":1, "ccip_sTxPort_c0_hdr_address":42, "ccip_sTxPort_c0_hdr_mdata":16, - "?ccip_sTxPort_c1_fire":1, + "?ccip_sTxPort_c1_valid":1, "ccip_sTxPort_c1_hdr_address":42, - "ccip_sTxPort_c2_mmioRdValid":1 + "ccip_sTxPort_c2_mmioRdValid":1, + "!ccip_sRxPort_c0TxAlmFull":1, + "!ccip_sRxPort_c1TxAlmFull":1, + "avs_address":26, + "!avs_waitrequest":1, + "?avs_write_fire":1, + "?avs_read_fire":1, + "avs_byteenable":64, + "avs_burstcount":4, + "avs_readdatavalid":1, + "mem_bank_select":1, + "ccip_dram_rd_req_ctr":26, + "ccip_dram_wr_req_ctr":26, + "ccip_rd_req_ctr":26, + "ccip_rd_rsp_ctr":3, + "ccip_wr_req_ctr":26, + "snp_req_ctr":"`VX_DRAM_ADDR_WIDTH", + "snp_rsp_ctr":"`VX_DRAM_ADDR_WIDTH" }, "afu/vortex": { "!reset": 1,