From 48468ed26a66a330c03c6704ecbc264ecf0bfc9d Mon Sep 17 00:00:00 2001
From: felsabbagh3 <felsabbagh3@gatech.edu>
Date: Fri, 10 May 2019 00:49:54 -0700
Subject: [PATCH] Proper SIMT with fine-grain scheduler implemented

---
 kernel/vortex_test.dump             | 3379 ++++++++++----------
 kernel/vortex_test.elf              |  Bin 15536 -> 15464 bytes
 kernel/vortex_test.hex              |  795 +++--
 kernel/vx_include/vx_front.c        |   16 +-
 kernel/vx_main.c                    |   40 +-
 kernel/vx_os/vx_back/vx_back.s      |   10 +-
 rtl/VX_context.v                    |   17 +-
 rtl/VX_context_slave.v              |  145 +
 rtl/VX_decode.v                     |  171 +-
 rtl/VX_execute.v                    |    7 +
 rtl/VX_fetch.v                      |  128 +-
 rtl/VX_memory.v                     |   14 +-
 rtl/VX_register_file.v              |    9 +-
 rtl/VX_register_file_master_slave.v |   72 +
 rtl/VX_register_file_slave.v        |   15 +-
 rtl/VX_warp.v                       |    8 +-
 rtl/Vortex.v                        |   30 +-
 rtl/obj_dir/VVortex                 |  Bin 411004 -> 431484 bytes
 rtl/obj_dir/VVortex.cpp             | 4435 ++++++++++++++++++++-------
 rtl/obj_dir/VVortex.h               |  107 +-
 rtl/obj_dir/VVortex__ALL.a          |  Bin 72904 -> 92480 bytes
 rtl/obj_dir/VVortex__ALLcls.o       |  Bin 69768 -> 89344 bytes
 rtl/obj_dir/VVortex__ver.d          |    2 +-
 rtl/obj_dir/VVortex__verFiles.dat   |   36 +-
 rtl/obj_dir/test_bench.o            |  Bin 66380 -> 66380 bytes
 rtl/results.txt                     |    8 +-
 rtl/test_bench.h                    |   11 +-
 27 files changed, 6080 insertions(+), 3375 deletions(-)
 create mode 100644 rtl/VX_context_slave.v
 create mode 100644 rtl/VX_register_file_master_slave.v

diff --git a/kernel/vortex_test.dump b/kernel/vortex_test.dump
index 0befe0cf..9e6b29f7 100644
--- a/kernel/vortex_test.dump
+++ b/kernel/vortex_test.dump
@@ -5,15 +5,15 @@ vortex_test.elf:     file format elf32-littleriscv
 Disassembly of section .text:
 
 80000000 <_start>:
-80000000:	00100513          	li	a0,1
+80000000:	00200513          	li	a0,2
 80000004:	02051073          	csrw	0x20,a0
 80000008:	00200513          	li	a0,2
 8000000c:	02151073          	csrw	0x21,a0
 80000010:	f1401073          	csrw	mhartid,zero
 80000014:	30101073          	csrw	misa,zero
 80000018:	7ffff137          	lui	sp,0x7ffff
-8000001c:	198000ef          	jal	ra,800001b4 <vx_before_main>
-80000020:	6dc010ef          	jal	ra,800016fc <main>
+8000001c:	1b0000ef          	jal	ra,800001cc <vx_before_main>
+80000020:	6a8010ef          	jal	ra,800016c8 <main>
 80000024:	00000073          	ecall
 
 80000028 <vx_createThreads>:
@@ -38,1621 +38,1548 @@ Disassembly of section .text:
 80000050:	fedff06f          	j	8000003c <loop_cond>
 
 80000054 <loop_done>:
-80000054:	000f0113          	mv	sp,t5
-80000058:	00000513          	li	a0,0
-8000005c:	00060f93          	mv	t6,a2
-80000060:	00038d93          	mv	s11,t2
-80000064:	01bfe0eb          	0x1bfe0eb
-80000068:	00000517          	auipc	a0,0x0
-8000006c:	1b050513          	addi	a0,a0,432 # 80000218 <vx_reschedule_warps>
-80000070:	0005406b          	0x5406b
+80000054:	00000013          	nop
+80000058:	00000013          	nop
+8000005c:	00000013          	nop
+80000060:	00000013          	nop
+80000064:	00000013          	nop
+80000068:	00000013          	nop
+8000006c:	000f0113          	mv	sp,t5
+80000070:	00000513          	li	a0,0
+80000074:	00060f93          	mv	t6,a2
+80000078:	00038d93          	mv	s11,t2
+8000007c:	01bfe0eb          	0x1bfe0eb
+80000080:	00000517          	auipc	a0,0x0
+80000084:	1b050513          	addi	a0,a0,432 # 80000230 <vx_reschedule_warps>
+80000088:	0005406b          	0x5406b
 
-80000074 <vx_wspawn>:
-80000074:	00000317          	auipc	t1,0x0
-80000078:	fb430313          	addi	t1,t1,-76 # 80000028 <vx_createThreads>
-8000007c:	0003006b          	0x3006b
-80000080:	00008067          	ret
+8000008c <vx_wspawn>:
+8000008c:	00000317          	auipc	t1,0x0
+80000090:	f9c30313          	addi	t1,t1,-100 # 80000028 <vx_createThreads>
+80000094:	0003006b          	0x3006b
+80000098:	00008067          	ret
 
-80000084 <vx_save_context>:
-80000084:	01000217          	auipc	tp,0x1000
-80000088:	26020213          	addi	tp,tp,608 # 810002e4 <context>
-8000008c:	00022023          	sw	zero,0(tp) # 0 <A_WARPS-0x7>
-80000090:	00122223          	sw	ra,4(tp) # 4 <A_WARPS-0x3>
-80000094:	00222423          	sw	sp,8(tp) # 8 <A_WARPS+0x1>
-80000098:	00322623          	sw	gp,12(tp) # c <A_WARPS+0x5>
-8000009c:	00422823          	sw	tp,16(tp) # 10 <A_WARPS+0x9>
-800000a0:	00522a23          	sw	t0,20(tp) # 14 <A_WARPS+0xd>
-800000a4:	00622c23          	sw	t1,24(tp) # 18 <A_WARPS+0x11>
-800000a8:	00722e23          	sw	t2,28(tp) # 1c <A_WARPS+0x15>
-800000ac:	02822023          	sw	s0,32(tp) # 20 <A_WARPS+0x19>
-800000b0:	02922223          	sw	s1,36(tp) # 24 <A_WARPS+0x1d>
-800000b4:	02a22423          	sw	a0,40(tp) # 28 <A_WARPS+0x21>
-800000b8:	02b22623          	sw	a1,44(tp) # 2c <A_WARPS+0x25>
-800000bc:	02c22823          	sw	a2,48(tp) # 30 <A_WARPS+0x29>
-800000c0:	02d22a23          	sw	a3,52(tp) # 34 <SIZE+0x2>
-800000c4:	02e22c23          	sw	a4,56(tp) # 38 <SIZE+0x6>
-800000c8:	02f22e23          	sw	a5,60(tp) # 3c <SIZE+0xa>
-800000cc:	05022023          	sw	a6,64(tp) # 40 <SIZE+0xe>
-800000d0:	05122223          	sw	a7,68(tp) # 44 <SIZE+0x12>
-800000d4:	05222423          	sw	s2,72(tp) # 48 <SIZE+0x16>
-800000d8:	05322623          	sw	s3,76(tp) # 4c <SIZE+0x1a>
-800000dc:	05422823          	sw	s4,80(tp) # 50 <SIZE+0x1e>
-800000e0:	05522a23          	sw	s5,84(tp) # 54 <SIZE+0x22>
-800000e4:	05622c23          	sw	s6,88(tp) # 58 <SIZE+0x26>
-800000e8:	05722e23          	sw	s7,92(tp) # 5c <SIZE+0x2a>
-800000ec:	07822023          	sw	s8,96(tp) # 60 <SIZE+0x2e>
-800000f0:	07922223          	sw	s9,100(tp) # 64 <SIZE+0x32>
-800000f4:	07a22423          	sw	s10,104(tp) # 68 <SIZE+0x36>
-800000f8:	07b22623          	sw	s11,108(tp) # 6c <SIZE+0x3a>
-800000fc:	07c22823          	sw	t3,112(tp) # 70 <SIZE+0x3e>
-80000100:	07d22a23          	sw	t4,116(tp) # 74 <SIZE+0x42>
-80000104:	07e22c23          	sw	t5,120(tp) # 78 <SIZE+0x46>
-80000108:	07f22e23          	sw	t6,124(tp) # 7c <SIZE+0x4a>
-8000010c:	00100213          	li	tp,1
-80000110:	00008067          	ret
+8000009c <vx_save_context>:
+8000009c:	01000217          	auipc	tp,0x1000
+800000a0:	20020213          	addi	tp,tp,512 # 8100029c <context>
+800000a4:	00022023          	sw	zero,0(tp) # 0 <A_WARPS-0x7>
+800000a8:	00122223          	sw	ra,4(tp) # 4 <A_WARPS-0x3>
+800000ac:	00222423          	sw	sp,8(tp) # 8 <A_WARPS+0x1>
+800000b0:	00322623          	sw	gp,12(tp) # c <A_WARPS+0x5>
+800000b4:	00422823          	sw	tp,16(tp) # 10 <A_WARPS+0x9>
+800000b8:	00522a23          	sw	t0,20(tp) # 14 <A_WARPS+0xd>
+800000bc:	00622c23          	sw	t1,24(tp) # 18 <A_WARPS+0x11>
+800000c0:	00722e23          	sw	t2,28(tp) # 1c <A_WARPS+0x15>
+800000c4:	02822023          	sw	s0,32(tp) # 20 <A_WARPS+0x19>
+800000c8:	02922223          	sw	s1,36(tp) # 24 <A_WARPS+0x1d>
+800000cc:	02a22423          	sw	a0,40(tp) # 28 <A_WARPS+0x21>
+800000d0:	02b22623          	sw	a1,44(tp) # 2c <A_WARPS+0x25>
+800000d4:	02c22823          	sw	a2,48(tp) # 30 <A_WARPS+0x29>
+800000d8:	02d22a23          	sw	a3,52(tp) # 34 <SIZE+0x2>
+800000dc:	02e22c23          	sw	a4,56(tp) # 38 <SIZE+0x6>
+800000e0:	02f22e23          	sw	a5,60(tp) # 3c <SIZE+0xa>
+800000e4:	05022023          	sw	a6,64(tp) # 40 <SIZE+0xe>
+800000e8:	05122223          	sw	a7,68(tp) # 44 <SIZE+0x12>
+800000ec:	05222423          	sw	s2,72(tp) # 48 <SIZE+0x16>
+800000f0:	05322623          	sw	s3,76(tp) # 4c <SIZE+0x1a>
+800000f4:	05422823          	sw	s4,80(tp) # 50 <SIZE+0x1e>
+800000f8:	05522a23          	sw	s5,84(tp) # 54 <SIZE+0x22>
+800000fc:	05622c23          	sw	s6,88(tp) # 58 <SIZE+0x26>
+80000100:	05722e23          	sw	s7,92(tp) # 5c <SIZE+0x2a>
+80000104:	07822023          	sw	s8,96(tp) # 60 <SIZE+0x2e>
+80000108:	07922223          	sw	s9,100(tp) # 64 <SIZE+0x32>
+8000010c:	07a22423          	sw	s10,104(tp) # 68 <SIZE+0x36>
+80000110:	07b22623          	sw	s11,108(tp) # 6c <SIZE+0x3a>
+80000114:	07c22823          	sw	t3,112(tp) # 70 <SIZE+0x3e>
+80000118:	07d22a23          	sw	t4,116(tp) # 74 <SIZE+0x42>
+8000011c:	07e22c23          	sw	t5,120(tp) # 78 <SIZE+0x46>
+80000120:	07f22e23          	sw	t6,124(tp) # 7c <SIZE+0x4a>
+80000124:	00100213          	li	tp,1
+80000128:	00008067          	ret
 
-80000114 <vx_load_context>:
-80000114:	01000217          	auipc	tp,0x1000
-80000118:	1d020213          	addi	tp,tp,464 # 810002e4 <context>
-8000011c:	00022003          	lw	zero,0(tp) # 0 <A_WARPS-0x7>
-80000120:	00422083          	lw	ra,4(tp) # 4 <A_WARPS-0x3>
-80000124:	00822103          	lw	sp,8(tp) # 8 <A_WARPS+0x1>
-80000128:	00c22183          	lw	gp,12(tp) # c <A_WARPS+0x5>
-8000012c:	01022203          	lw	tp,16(tp) # 10 <A_WARPS+0x9>
-80000130:	01422283          	lw	t0,20(tp) # 14 <A_WARPS+0xd>
-80000134:	01822303          	lw	t1,24(tp) # 18 <A_WARPS+0x11>
-80000138:	01c22383          	lw	t2,28(tp) # 1c <A_WARPS+0x15>
-8000013c:	02022403          	lw	s0,32(tp) # 20 <A_WARPS+0x19>
-80000140:	02422483          	lw	s1,36(tp) # 24 <A_WARPS+0x1d>
-80000144:	02822503          	lw	a0,40(tp) # 28 <A_WARPS+0x21>
-80000148:	02c22583          	lw	a1,44(tp) # 2c <A_WARPS+0x25>
-8000014c:	03022603          	lw	a2,48(tp) # 30 <A_WARPS+0x29>
-80000150:	03422683          	lw	a3,52(tp) # 34 <SIZE+0x2>
-80000154:	03822703          	lw	a4,56(tp) # 38 <SIZE+0x6>
-80000158:	03c22783          	lw	a5,60(tp) # 3c <SIZE+0xa>
-8000015c:	04022803          	lw	a6,64(tp) # 40 <SIZE+0xe>
-80000160:	04422883          	lw	a7,68(tp) # 44 <SIZE+0x12>
-80000164:	04822903          	lw	s2,72(tp) # 48 <SIZE+0x16>
-80000168:	04c22983          	lw	s3,76(tp) # 4c <SIZE+0x1a>
-8000016c:	05022a03          	lw	s4,80(tp) # 50 <SIZE+0x1e>
-80000170:	05422a83          	lw	s5,84(tp) # 54 <SIZE+0x22>
-80000174:	05822b03          	lw	s6,88(tp) # 58 <SIZE+0x26>
-80000178:	05c22b83          	lw	s7,92(tp) # 5c <SIZE+0x2a>
-8000017c:	06022c03          	lw	s8,96(tp) # 60 <SIZE+0x2e>
-80000180:	06422c83          	lw	s9,100(tp) # 64 <SIZE+0x32>
-80000184:	06822d03          	lw	s10,104(tp) # 68 <SIZE+0x36>
-80000188:	06c22d83          	lw	s11,108(tp) # 6c <SIZE+0x3a>
-8000018c:	07022e03          	lw	t3,112(tp) # 70 <SIZE+0x3e>
-80000190:	07422e83          	lw	t4,116(tp) # 74 <SIZE+0x42>
-80000194:	07822f03          	lw	t5,120(tp) # 78 <SIZE+0x46>
-80000198:	07c22f83          	lw	t6,124(tp) # 7c <SIZE+0x4a>
-8000019c:	00000213          	li	tp,0
-800001a0:	00008067          	ret
+8000012c <vx_load_context>:
+8000012c:	01000217          	auipc	tp,0x1000
+80000130:	17020213          	addi	tp,tp,368 # 8100029c <context>
+80000134:	00022003          	lw	zero,0(tp) # 0 <A_WARPS-0x7>
+80000138:	00422083          	lw	ra,4(tp) # 4 <A_WARPS-0x3>
+8000013c:	00822103          	lw	sp,8(tp) # 8 <A_WARPS+0x1>
+80000140:	00c22183          	lw	gp,12(tp) # c <A_WARPS+0x5>
+80000144:	01022203          	lw	tp,16(tp) # 10 <A_WARPS+0x9>
+80000148:	01422283          	lw	t0,20(tp) # 14 <A_WARPS+0xd>
+8000014c:	01822303          	lw	t1,24(tp) # 18 <A_WARPS+0x11>
+80000150:	01c22383          	lw	t2,28(tp) # 1c <A_WARPS+0x15>
+80000154:	02022403          	lw	s0,32(tp) # 20 <A_WARPS+0x19>
+80000158:	02422483          	lw	s1,36(tp) # 24 <A_WARPS+0x1d>
+8000015c:	02822503          	lw	a0,40(tp) # 28 <A_WARPS+0x21>
+80000160:	02c22583          	lw	a1,44(tp) # 2c <A_WARPS+0x25>
+80000164:	03022603          	lw	a2,48(tp) # 30 <A_WARPS+0x29>
+80000168:	03422683          	lw	a3,52(tp) # 34 <SIZE+0x2>
+8000016c:	03822703          	lw	a4,56(tp) # 38 <SIZE+0x6>
+80000170:	03c22783          	lw	a5,60(tp) # 3c <SIZE+0xa>
+80000174:	04022803          	lw	a6,64(tp) # 40 <SIZE+0xe>
+80000178:	04422883          	lw	a7,68(tp) # 44 <SIZE+0x12>
+8000017c:	04822903          	lw	s2,72(tp) # 48 <SIZE+0x16>
+80000180:	04c22983          	lw	s3,76(tp) # 4c <SIZE+0x1a>
+80000184:	05022a03          	lw	s4,80(tp) # 50 <SIZE+0x1e>
+80000188:	05422a83          	lw	s5,84(tp) # 54 <SIZE+0x22>
+8000018c:	05822b03          	lw	s6,88(tp) # 58 <SIZE+0x26>
+80000190:	05c22b83          	lw	s7,92(tp) # 5c <SIZE+0x2a>
+80000194:	06022c03          	lw	s8,96(tp) # 60 <SIZE+0x2e>
+80000198:	06422c83          	lw	s9,100(tp) # 64 <SIZE+0x32>
+8000019c:	06822d03          	lw	s10,104(tp) # 68 <SIZE+0x36>
+800001a0:	06c22d83          	lw	s11,108(tp) # 6c <SIZE+0x3a>
+800001a4:	07022e03          	lw	t3,112(tp) # 70 <SIZE+0x3e>
+800001a8:	07422e83          	lw	t4,116(tp) # 74 <SIZE+0x42>
+800001ac:	07822f03          	lw	t5,120(tp) # 78 <SIZE+0x46>
+800001b0:	07c22f83          	lw	t6,124(tp) # 7c <SIZE+0x4a>
+800001b4:	00000213          	li	tp,0
+800001b8:	00008067          	ret
 
-800001a4 <vx_available_warps>:
-800001a4:	02002573          	csrr	a0,0x20
-800001a8:	00008067          	ret
+800001bc <vx_available_warps>:
+800001bc:	02002573          	csrr	a0,0x20
+800001c0:	00008067          	ret
 
-800001ac <vx_available_threads>:
-800001ac:	02102573          	csrr	a0,0x21
-800001b0:	00008067          	ret
+800001c4 <vx_available_threads>:
+800001c4:	02102573          	csrr	a0,0x21
+800001c8:	00008067          	ret
 
-800001b4 <vx_before_main>:
-800001b4:	fe010113          	addi	sp,sp,-32
-800001b8:	00112e23          	sw	ra,28(sp)
-800001bc:	00812c23          	sw	s0,24(sp)
-800001c0:	02010413          	addi	s0,sp,32
-800001c4:	fe042623          	sw	zero,-20(s0)
-800001c8:	0300006f          	j	800001f8 <vx_before_main+0x44>
-800001cc:	fec42703          	lw	a4,-20(s0)
-800001d0:	4c400793          	li	a5,1220
-800001d4:	02f70733          	mul	a4,a4,a5
-800001d8:	810007b7          	lui	a5,0x81000
-800001dc:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-800001e0:	00f707b3          	add	a5,a4,a5
-800001e4:	00078513          	mv	a0,a5
-800001e8:	404000ef          	jal	ra,800005ec <queue_initialize>
-800001ec:	fec42783          	lw	a5,-20(s0)
-800001f0:	00178793          	addi	a5,a5,1
-800001f4:	fef42623          	sw	a5,-20(s0)
-800001f8:	fec42703          	lw	a4,-20(s0)
-800001fc:	00700793          	li	a5,7
-80000200:	fce7d6e3          	bge	a5,a4,800001cc <vx_before_main+0x18>
-80000204:	00000013          	nop
-80000208:	01c12083          	lw	ra,28(sp)
-8000020c:	01812403          	lw	s0,24(sp)
-80000210:	02010113          	addi	sp,sp,32
-80000214:	00008067          	ret
+800001cc <vx_before_main>:
+800001cc:	fe010113          	addi	sp,sp,-32
+800001d0:	00112e23          	sw	ra,28(sp)
+800001d4:	00812c23          	sw	s0,24(sp)
+800001d8:	02010413          	addi	s0,sp,32
+800001dc:	fe042623          	sw	zero,-20(s0)
+800001e0:	0300006f          	j	80000210 <vx_before_main+0x44>
+800001e4:	fec42703          	lw	a4,-20(s0)
+800001e8:	4c400793          	li	a5,1220
+800001ec:	02f70733          	mul	a4,a4,a5
+800001f0:	810007b7          	lui	a5,0x81000
+800001f4:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+800001f8:	00f707b3          	add	a5,a4,a5
+800001fc:	00078513          	mv	a0,a5
+80000200:	404000ef          	jal	ra,80000604 <queue_initialize>
+80000204:	fec42783          	lw	a5,-20(s0)
+80000208:	00178793          	addi	a5,a5,1
+8000020c:	fef42623          	sw	a5,-20(s0)
+80000210:	fec42703          	lw	a4,-20(s0)
+80000214:	00700793          	li	a5,7
+80000218:	fce7d6e3          	bge	a5,a4,800001e4 <vx_before_main+0x18>
+8000021c:	00000013          	nop
+80000220:	01c12083          	lw	ra,28(sp)
+80000224:	01812403          	lw	s0,24(sp)
+80000228:	02010113          	addi	sp,sp,32
+8000022c:	00008067          	ret
 
-80000218 <vx_reschedule_warps>:
-80000218:	fd010113          	addi	sp,sp,-48
-8000021c:	02112623          	sw	ra,44(sp)
-80000220:	02812423          	sw	s0,40(sp)
-80000224:	03a12223          	sw	s10,36(sp)
-80000228:	03010413          	addi	s0,sp,48
-8000022c:	000d0713          	mv	a4,s10
-80000230:	4c400793          	li	a5,1220
-80000234:	02f70733          	mul	a4,a4,a5
-80000238:	810007b7          	lui	a5,0x81000
-8000023c:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-80000240:	00f707b3          	add	a5,a4,a5
-80000244:	00078513          	mv	a0,a5
-80000248:	4b8000ef          	jal	ra,80000700 <queue_isEmpty>
-8000024c:	00050793          	mv	a5,a0
-80000250:	02078a63          	beqz	a5,80000284 <vx_reschedule_warps+0x6c>
-80000254:	000d0713          	mv	a4,s10
-80000258:	810007b7          	lui	a5,0x81000
-8000025c:	00271713          	slli	a4,a4,0x2
-80000260:	2c478793          	addi	a5,a5,708 # 810002c4 <main_sp+0xffffa8c0>
-80000264:	00f707b3          	add	a5,a4,a5
-80000268:	00100713          	li	a4,1
-8000026c:	00e7a023          	sw	a4,0(a5)
-80000270:	000d0793          	mv	a5,s10
-80000274:	00079663          	bnez	a5,80000280 <vx_reschedule_warps+0x68>
-80000278:	e9dff0ef          	jal	ra,80000114 <vx_load_context>
-8000027c:	0580006f          	j	800002d4 <vx_reschedule_warps+0xbc>
-80000280:	00000073          	ecall
-80000284:	000d0713          	mv	a4,s10
-80000288:	4c400793          	li	a5,1220
-8000028c:	02f70733          	mul	a4,a4,a5
-80000290:	810007b7          	lui	a5,0x81000
-80000294:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-80000298:	00f707b3          	add	a5,a4,a5
-8000029c:	fd840713          	addi	a4,s0,-40
-800002a0:	00070593          	mv	a1,a4
-800002a4:	00078513          	mv	a0,a5
-800002a8:	3d0000ef          	jal	ra,80000678 <queue_dequeue>
-800002ac:	fe042783          	lw	a5,-32(s0)
-800002b0:	00078113          	mv	sp,a5
-800002b4:	fdc42783          	lw	a5,-36(s0)
-800002b8:	fd842583          	lw	a1,-40(s0)
-800002bc:	fe442603          	lw	a2,-28(s0)
-800002c0:	fe842683          	lw	a3,-24(s0)
-800002c4:	fec42703          	lw	a4,-20(s0)
-800002c8:	00078513          	mv	a0,a5
-800002cc:	d5dff0ef          	jal	ra,80000028 <vx_createThreads>
-800002d0:	00000073          	ecall
-800002d4:	02c12083          	lw	ra,44(sp)
-800002d8:	02812403          	lw	s0,40(sp)
-800002dc:	02412d03          	lw	s10,36(sp)
-800002e0:	03010113          	addi	sp,sp,48
-800002e4:	00008067          	ret
+80000230 <vx_reschedule_warps>:
+80000230:	fd010113          	addi	sp,sp,-48
+80000234:	02112623          	sw	ra,44(sp)
+80000238:	02812423          	sw	s0,40(sp)
+8000023c:	03a12223          	sw	s10,36(sp)
+80000240:	03010413          	addi	s0,sp,48
+80000244:	000d0713          	mv	a4,s10
+80000248:	4c400793          	li	a5,1220
+8000024c:	02f70733          	mul	a4,a4,a5
+80000250:	810007b7          	lui	a5,0x81000
+80000254:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+80000258:	00f707b3          	add	a5,a4,a5
+8000025c:	00078513          	mv	a0,a5
+80000260:	4b8000ef          	jal	ra,80000718 <queue_isEmpty>
+80000264:	00050793          	mv	a5,a0
+80000268:	02078a63          	beqz	a5,8000029c <vx_reschedule_warps+0x6c>
+8000026c:	000d0713          	mv	a4,s10
+80000270:	810007b7          	lui	a5,0x81000
+80000274:	00271713          	slli	a4,a4,0x2
+80000278:	27c78793          	addi	a5,a5,636 # 8100027c <main_sp+0xffffa8c0>
+8000027c:	00f707b3          	add	a5,a4,a5
+80000280:	00100713          	li	a4,1
+80000284:	00e7a023          	sw	a4,0(a5)
+80000288:	000d0793          	mv	a5,s10
+8000028c:	00079663          	bnez	a5,80000298 <vx_reschedule_warps+0x68>
+80000290:	e9dff0ef          	jal	ra,8000012c <vx_load_context>
+80000294:	0580006f          	j	800002ec <vx_reschedule_warps+0xbc>
+80000298:	00000073          	ecall
+8000029c:	000d0713          	mv	a4,s10
+800002a0:	4c400793          	li	a5,1220
+800002a4:	02f70733          	mul	a4,a4,a5
+800002a8:	810007b7          	lui	a5,0x81000
+800002ac:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+800002b0:	00f707b3          	add	a5,a4,a5
+800002b4:	fd840713          	addi	a4,s0,-40
+800002b8:	00070593          	mv	a1,a4
+800002bc:	00078513          	mv	a0,a5
+800002c0:	3d0000ef          	jal	ra,80000690 <queue_dequeue>
+800002c4:	fe042783          	lw	a5,-32(s0)
+800002c8:	00078113          	mv	sp,a5
+800002cc:	fdc42783          	lw	a5,-36(s0)
+800002d0:	fd842583          	lw	a1,-40(s0)
+800002d4:	fe442603          	lw	a2,-28(s0)
+800002d8:	fe842683          	lw	a3,-24(s0)
+800002dc:	fec42703          	lw	a4,-20(s0)
+800002e0:	00078513          	mv	a0,a5
+800002e4:	d45ff0ef          	jal	ra,80000028 <vx_createThreads>
+800002e8:	00000073          	ecall
+800002ec:	02c12083          	lw	ra,44(sp)
+800002f0:	02812403          	lw	s0,40(sp)
+800002f4:	02412d03          	lw	s10,36(sp)
+800002f8:	03010113          	addi	sp,sp,48
+800002fc:	00008067          	ret
 
-800002e8 <vx_schedule_warps>:
-800002e8:	fb010113          	addi	sp,sp,-80
-800002ec:	04112623          	sw	ra,76(sp)
-800002f0:	04812423          	sw	s0,72(sp)
-800002f4:	05010413          	addi	s0,sp,80
-800002f8:	eadff0ef          	jal	ra,800001a4 <vx_available_warps>
-800002fc:	fea42423          	sw	a0,-24(s0)
-80000300:	00010993          	mv	s3,sp
-80000304:	00100793          	li	a5,1
-80000308:	fef42623          	sw	a5,-20(s0)
-8000030c:	0840006f          	j	80000390 <vx_schedule_warps+0xa8>
-80000310:	fec42703          	lw	a4,-20(s0)
-80000314:	4c400793          	li	a5,1220
-80000318:	02f70733          	mul	a4,a4,a5
-8000031c:	810007b7          	lui	a5,0x81000
-80000320:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-80000324:	00f707b3          	add	a5,a4,a5
-80000328:	00078513          	mv	a0,a5
-8000032c:	3d4000ef          	jal	ra,80000700 <queue_isEmpty>
-80000330:	00050793          	mv	a5,a0
-80000334:	04079863          	bnez	a5,80000384 <vx_schedule_warps+0x9c>
-80000338:	fec42703          	lw	a4,-20(s0)
-8000033c:	4c400793          	li	a5,1220
-80000340:	02f70733          	mul	a4,a4,a5
-80000344:	810007b7          	lui	a5,0x81000
-80000348:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-8000034c:	00f707b3          	add	a5,a4,a5
-80000350:	fd040713          	addi	a4,s0,-48
-80000354:	00070593          	mv	a1,a4
-80000358:	00078513          	mv	a0,a5
-8000035c:	31c000ef          	jal	ra,80000678 <queue_dequeue>
-80000360:	fd842783          	lw	a5,-40(s0)
-80000364:	00078113          	mv	sp,a5
-80000368:	fd442783          	lw	a5,-44(s0)
-8000036c:	fd042583          	lw	a1,-48(s0)
-80000370:	fdc42603          	lw	a2,-36(s0)
-80000374:	fe042683          	lw	a3,-32(s0)
-80000378:	fe442703          	lw	a4,-28(s0)
-8000037c:	00078513          	mv	a0,a5
-80000380:	cf5ff0ef          	jal	ra,80000074 <vx_wspawn>
-80000384:	fec42783          	lw	a5,-20(s0)
-80000388:	00178793          	addi	a5,a5,1
-8000038c:	fef42623          	sw	a5,-20(s0)
-80000390:	fec42783          	lw	a5,-20(s0)
-80000394:	fe842703          	lw	a4,-24(s0)
-80000398:	f6e7ece3          	bltu	a5,a4,80000310 <vx_schedule_warps+0x28>
-8000039c:	00098113          	mv	sp,s3
-800003a0:	ce5ff0ef          	jal	ra,80000084 <vx_save_context>
-800003a4:	00020793          	mv	a5,tp
-800003a8:	04078863          	beqz	a5,800003f8 <vx_schedule_warps+0x110>
-800003ac:	810007b7          	lui	a5,0x81000
-800003b0:	36478513          	addi	a0,a5,868 # 81000364 <main_sp+0xffffa960>
-800003b4:	34c000ef          	jal	ra,80000700 <queue_isEmpty>
-800003b8:	00050793          	mv	a5,a0
-800003bc:	02079e63          	bnez	a5,800003f8 <vx_schedule_warps+0x110>
-800003c0:	fb840793          	addi	a5,s0,-72
-800003c4:	00078593          	mv	a1,a5
-800003c8:	810007b7          	lui	a5,0x81000
-800003cc:	36478513          	addi	a0,a5,868 # 81000364 <main_sp+0xffffa960>
-800003d0:	2a8000ef          	jal	ra,80000678 <queue_dequeue>
-800003d4:	fc042783          	lw	a5,-64(s0)
-800003d8:	00078113          	mv	sp,a5
-800003dc:	fbc42783          	lw	a5,-68(s0)
-800003e0:	fb842583          	lw	a1,-72(s0)
-800003e4:	fc442603          	lw	a2,-60(s0)
-800003e8:	fc842683          	lw	a3,-56(s0)
-800003ec:	fcc42703          	lw	a4,-52(s0)
-800003f0:	00078513          	mv	a0,a5
-800003f4:	c35ff0ef          	jal	ra,80000028 <vx_createThreads>
-800003f8:	00000013          	nop
-800003fc:	04c12083          	lw	ra,76(sp)
-80000400:	04812403          	lw	s0,72(sp)
-80000404:	05010113          	addi	sp,sp,80
-80000408:	00008067          	ret
+80000300 <vx_schedule_warps>:
+80000300:	fb010113          	addi	sp,sp,-80
+80000304:	04112623          	sw	ra,76(sp)
+80000308:	04812423          	sw	s0,72(sp)
+8000030c:	05010413          	addi	s0,sp,80
+80000310:	eadff0ef          	jal	ra,800001bc <vx_available_warps>
+80000314:	fea42423          	sw	a0,-24(s0)
+80000318:	00010993          	mv	s3,sp
+8000031c:	00100793          	li	a5,1
+80000320:	fef42623          	sw	a5,-20(s0)
+80000324:	0840006f          	j	800003a8 <vx_schedule_warps+0xa8>
+80000328:	fec42703          	lw	a4,-20(s0)
+8000032c:	4c400793          	li	a5,1220
+80000330:	02f70733          	mul	a4,a4,a5
+80000334:	810007b7          	lui	a5,0x81000
+80000338:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+8000033c:	00f707b3          	add	a5,a4,a5
+80000340:	00078513          	mv	a0,a5
+80000344:	3d4000ef          	jal	ra,80000718 <queue_isEmpty>
+80000348:	00050793          	mv	a5,a0
+8000034c:	04079863          	bnez	a5,8000039c <vx_schedule_warps+0x9c>
+80000350:	fec42703          	lw	a4,-20(s0)
+80000354:	4c400793          	li	a5,1220
+80000358:	02f70733          	mul	a4,a4,a5
+8000035c:	810007b7          	lui	a5,0x81000
+80000360:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+80000364:	00f707b3          	add	a5,a4,a5
+80000368:	fd040713          	addi	a4,s0,-48
+8000036c:	00070593          	mv	a1,a4
+80000370:	00078513          	mv	a0,a5
+80000374:	31c000ef          	jal	ra,80000690 <queue_dequeue>
+80000378:	fd842783          	lw	a5,-40(s0)
+8000037c:	00078113          	mv	sp,a5
+80000380:	fd442783          	lw	a5,-44(s0)
+80000384:	fd042583          	lw	a1,-48(s0)
+80000388:	fdc42603          	lw	a2,-36(s0)
+8000038c:	fe042683          	lw	a3,-32(s0)
+80000390:	fe442703          	lw	a4,-28(s0)
+80000394:	00078513          	mv	a0,a5
+80000398:	cf5ff0ef          	jal	ra,8000008c <vx_wspawn>
+8000039c:	fec42783          	lw	a5,-20(s0)
+800003a0:	00178793          	addi	a5,a5,1
+800003a4:	fef42623          	sw	a5,-20(s0)
+800003a8:	fec42783          	lw	a5,-20(s0)
+800003ac:	fe842703          	lw	a4,-24(s0)
+800003b0:	f6e7ece3          	bltu	a5,a4,80000328 <vx_schedule_warps+0x28>
+800003b4:	00098113          	mv	sp,s3
+800003b8:	ce5ff0ef          	jal	ra,8000009c <vx_save_context>
+800003bc:	00020793          	mv	a5,tp
+800003c0:	04078863          	beqz	a5,80000410 <vx_schedule_warps+0x110>
+800003c4:	810007b7          	lui	a5,0x81000
+800003c8:	31c78513          	addi	a0,a5,796 # 8100031c <main_sp+0xffffa960>
+800003cc:	34c000ef          	jal	ra,80000718 <queue_isEmpty>
+800003d0:	00050793          	mv	a5,a0
+800003d4:	02079e63          	bnez	a5,80000410 <vx_schedule_warps+0x110>
+800003d8:	fb840793          	addi	a5,s0,-72
+800003dc:	00078593          	mv	a1,a5
+800003e0:	810007b7          	lui	a5,0x81000
+800003e4:	31c78513          	addi	a0,a5,796 # 8100031c <main_sp+0xffffa960>
+800003e8:	2a8000ef          	jal	ra,80000690 <queue_dequeue>
+800003ec:	fc042783          	lw	a5,-64(s0)
+800003f0:	00078113          	mv	sp,a5
+800003f4:	fbc42783          	lw	a5,-68(s0)
+800003f8:	fb842583          	lw	a1,-72(s0)
+800003fc:	fc442603          	lw	a2,-60(s0)
+80000400:	fc842683          	lw	a3,-56(s0)
+80000404:	fcc42703          	lw	a4,-52(s0)
+80000408:	00078513          	mv	a0,a5
+8000040c:	c1dff0ef          	jal	ra,80000028 <vx_createThreads>
+80000410:	00000013          	nop
+80000414:	04c12083          	lw	ra,76(sp)
+80000418:	04812403          	lw	s0,72(sp)
+8000041c:	05010113          	addi	sp,sp,80
+80000420:	00008067          	ret
 
-8000040c <vx_spawnWarps>:
-8000040c:	fb010113          	addi	sp,sp,-80
-80000410:	04112623          	sw	ra,76(sp)
-80000414:	04812423          	sw	s0,72(sp)
-80000418:	05010413          	addi	s0,sp,80
-8000041c:	faa42e23          	sw	a0,-68(s0)
-80000420:	fab42c23          	sw	a1,-72(s0)
-80000424:	fac42a23          	sw	a2,-76(s0)
-80000428:	fad42823          	sw	a3,-80(s0)
-8000042c:	d89ff0ef          	jal	ra,800001b4 <vx_before_main>
-80000430:	d75ff0ef          	jal	ra,800001a4 <vx_available_warps>
-80000434:	fea42223          	sw	a0,-28(s0)
-80000438:	00010913          	mv	s2,sp
-8000043c:	fe042623          	sw	zero,-20(s0)
-80000440:	fe042423          	sw	zero,-24(s0)
-80000444:	08c0006f          	j	800004d0 <vx_spawnWarps+0xc4>
-80000448:	ffff09b7          	lui	s3,0xffff0
-8000044c:	01310133          	add	sp,sp,s3
-80000450:	fe842783          	lw	a5,-24(s0)
-80000454:	fcf42623          	sw	a5,-52(s0)
-80000458:	fb842783          	lw	a5,-72(s0)
-8000045c:	fcf42823          	sw	a5,-48(s0)
-80000460:	00010793          	mv	a5,sp
-80000464:	fcf42a23          	sw	a5,-44(s0)
-80000468:	fb442783          	lw	a5,-76(s0)
-8000046c:	fcf42c23          	sw	a5,-40(s0)
-80000470:	fb042783          	lw	a5,-80(s0)
-80000474:	fcf42e23          	sw	a5,-36(s0)
-80000478:	fec42783          	lw	a5,-20(s0)
-8000047c:	fef42023          	sw	a5,-32(s0)
-80000480:	fec42703          	lw	a4,-20(s0)
-80000484:	4c400793          	li	a5,1220
-80000488:	02f70733          	mul	a4,a4,a5
-8000048c:	810007b7          	lui	a5,0x81000
-80000490:	36478793          	addi	a5,a5,868 # 81000364 <main_sp+0xffffa960>
-80000494:	00f707b3          	add	a5,a4,a5
-80000498:	fcc40713          	addi	a4,s0,-52
-8000049c:	00070593          	mv	a1,a4
-800004a0:	00078513          	mv	a0,a5
-800004a4:	16c000ef          	jal	ra,80000610 <queue_enqueue>
-800004a8:	fec42783          	lw	a5,-20(s0)
-800004ac:	00178793          	addi	a5,a5,1
-800004b0:	fef42623          	sw	a5,-20(s0)
-800004b4:	fec42783          	lw	a5,-20(s0)
-800004b8:	fe442703          	lw	a4,-28(s0)
-800004bc:	00e7e463          	bltu	a5,a4,800004c4 <vx_spawnWarps+0xb8>
-800004c0:	fe042623          	sw	zero,-20(s0)
-800004c4:	fe842783          	lw	a5,-24(s0)
-800004c8:	00178793          	addi	a5,a5,1
-800004cc:	fef42423          	sw	a5,-24(s0)
-800004d0:	fe842703          	lw	a4,-24(s0)
-800004d4:	fbc42783          	lw	a5,-68(s0)
-800004d8:	f6f768e3          	bltu	a4,a5,80000448 <vx_spawnWarps+0x3c>
-800004dc:	00090113          	mv	sp,s2
-800004e0:	e09ff0ef          	jal	ra,800002e8 <vx_schedule_warps>
-800004e4:	00000013          	nop
-800004e8:	04c12083          	lw	ra,76(sp)
-800004ec:	04812403          	lw	s0,72(sp)
-800004f0:	05010113          	addi	sp,sp,80
-800004f4:	00008067          	ret
+80000424 <vx_spawnWarps>:
+80000424:	fb010113          	addi	sp,sp,-80
+80000428:	04112623          	sw	ra,76(sp)
+8000042c:	04812423          	sw	s0,72(sp)
+80000430:	05010413          	addi	s0,sp,80
+80000434:	faa42e23          	sw	a0,-68(s0)
+80000438:	fab42c23          	sw	a1,-72(s0)
+8000043c:	fac42a23          	sw	a2,-76(s0)
+80000440:	fad42823          	sw	a3,-80(s0)
+80000444:	d89ff0ef          	jal	ra,800001cc <vx_before_main>
+80000448:	d75ff0ef          	jal	ra,800001bc <vx_available_warps>
+8000044c:	fea42223          	sw	a0,-28(s0)
+80000450:	00010913          	mv	s2,sp
+80000454:	fe042623          	sw	zero,-20(s0)
+80000458:	fe042423          	sw	zero,-24(s0)
+8000045c:	08c0006f          	j	800004e8 <vx_spawnWarps+0xc4>
+80000460:	ffff09b7          	lui	s3,0xffff0
+80000464:	01310133          	add	sp,sp,s3
+80000468:	fe842783          	lw	a5,-24(s0)
+8000046c:	fcf42623          	sw	a5,-52(s0)
+80000470:	fb842783          	lw	a5,-72(s0)
+80000474:	fcf42823          	sw	a5,-48(s0)
+80000478:	00010793          	mv	a5,sp
+8000047c:	fcf42a23          	sw	a5,-44(s0)
+80000480:	fb442783          	lw	a5,-76(s0)
+80000484:	fcf42c23          	sw	a5,-40(s0)
+80000488:	fb042783          	lw	a5,-80(s0)
+8000048c:	fcf42e23          	sw	a5,-36(s0)
+80000490:	fec42783          	lw	a5,-20(s0)
+80000494:	fef42023          	sw	a5,-32(s0)
+80000498:	fec42703          	lw	a4,-20(s0)
+8000049c:	4c400793          	li	a5,1220
+800004a0:	02f70733          	mul	a4,a4,a5
+800004a4:	810007b7          	lui	a5,0x81000
+800004a8:	31c78793          	addi	a5,a5,796 # 8100031c <main_sp+0xffffa960>
+800004ac:	00f707b3          	add	a5,a4,a5
+800004b0:	fcc40713          	addi	a4,s0,-52
+800004b4:	00070593          	mv	a1,a4
+800004b8:	00078513          	mv	a0,a5
+800004bc:	16c000ef          	jal	ra,80000628 <queue_enqueue>
+800004c0:	fec42783          	lw	a5,-20(s0)
+800004c4:	00178793          	addi	a5,a5,1
+800004c8:	fef42623          	sw	a5,-20(s0)
+800004cc:	fec42783          	lw	a5,-20(s0)
+800004d0:	fe442703          	lw	a4,-28(s0)
+800004d4:	00e7e463          	bltu	a5,a4,800004dc <vx_spawnWarps+0xb8>
+800004d8:	fe042623          	sw	zero,-20(s0)
+800004dc:	fe842783          	lw	a5,-24(s0)
+800004e0:	00178793          	addi	a5,a5,1
+800004e4:	fef42423          	sw	a5,-24(s0)
+800004e8:	fe842703          	lw	a4,-24(s0)
+800004ec:	fbc42783          	lw	a5,-68(s0)
+800004f0:	f6f768e3          	bltu	a4,a5,80000460 <vx_spawnWarps+0x3c>
+800004f4:	00090113          	mv	sp,s2
+800004f8:	e09ff0ef          	jal	ra,80000300 <vx_schedule_warps>
+800004fc:	00000013          	nop
+80000500:	04c12083          	lw	ra,76(sp)
+80000504:	04812403          	lw	s0,72(sp)
+80000508:	05010113          	addi	sp,sp,80
+8000050c:	00008067          	ret
 
-800004f8 <vx_wait_for_warps>:
-800004f8:	fd010113          	addi	sp,sp,-48
-800004fc:	02112623          	sw	ra,44(sp)
-80000500:	02812423          	sw	s0,40(sp)
-80000504:	03010413          	addi	s0,sp,48
-80000508:	fca42e23          	sw	a0,-36(s0)
-8000050c:	c99ff0ef          	jal	ra,800001a4 <vx_available_warps>
-80000510:	fea42023          	sw	a0,-32(s0)
-80000514:	fe042623          	sw	zero,-20(s0)
-80000518:	0540006f          	j	8000056c <vx_wait_for_warps+0x74>
-8000051c:	fe042623          	sw	zero,-20(s0)
-80000520:	fe042423          	sw	zero,-24(s0)
-80000524:	03c0006f          	j	80000560 <vx_wait_for_warps+0x68>
-80000528:	810007b7          	lui	a5,0x81000
-8000052c:	fe842703          	lw	a4,-24(s0)
-80000530:	00271713          	slli	a4,a4,0x2
-80000534:	2c478793          	addi	a5,a5,708 # 810002c4 <main_sp+0xffffa8c0>
-80000538:	00f707b3          	add	a5,a4,a5
-8000053c:	0007a703          	lw	a4,0(a5)
-80000540:	00100793          	li	a5,1
-80000544:	00f71863          	bne	a4,a5,80000554 <vx_wait_for_warps+0x5c>
-80000548:	fec42783          	lw	a5,-20(s0)
-8000054c:	00178793          	addi	a5,a5,1
-80000550:	fef42623          	sw	a5,-20(s0)
-80000554:	fe842783          	lw	a5,-24(s0)
-80000558:	00178793          	addi	a5,a5,1
-8000055c:	fef42423          	sw	a5,-24(s0)
-80000560:	fe842783          	lw	a5,-24(s0)
-80000564:	fe042703          	lw	a4,-32(s0)
-80000568:	fce7e0e3          	bltu	a5,a4,80000528 <vx_wait_for_warps+0x30>
-8000056c:	fec42703          	lw	a4,-20(s0)
-80000570:	fdc42783          	lw	a5,-36(s0)
-80000574:	faf714e3          	bne	a4,a5,8000051c <vx_wait_for_warps+0x24>
-80000578:	fe042223          	sw	zero,-28(s0)
-8000057c:	0280006f          	j	800005a4 <vx_wait_for_warps+0xac>
-80000580:	810007b7          	lui	a5,0x81000
-80000584:	fe442703          	lw	a4,-28(s0)
-80000588:	00271713          	slli	a4,a4,0x2
-8000058c:	2c478793          	addi	a5,a5,708 # 810002c4 <main_sp+0xffffa8c0>
-80000590:	00f707b3          	add	a5,a4,a5
-80000594:	0007a023          	sw	zero,0(a5)
-80000598:	fe442783          	lw	a5,-28(s0)
-8000059c:	00178793          	addi	a5,a5,1
-800005a0:	fef42223          	sw	a5,-28(s0)
-800005a4:	fe442783          	lw	a5,-28(s0)
-800005a8:	fe042703          	lw	a4,-32(s0)
-800005ac:	fce7eae3          	bltu	a5,a4,80000580 <vx_wait_for_warps+0x88>
-800005b0:	00000013          	nop
-800005b4:	02c12083          	lw	ra,44(sp)
-800005b8:	02812403          	lw	s0,40(sp)
-800005bc:	03010113          	addi	sp,sp,48
-800005c0:	00008067          	ret
+80000510 <vx_wait_for_warps>:
+80000510:	fd010113          	addi	sp,sp,-48
+80000514:	02112623          	sw	ra,44(sp)
+80000518:	02812423          	sw	s0,40(sp)
+8000051c:	03010413          	addi	s0,sp,48
+80000520:	fca42e23          	sw	a0,-36(s0)
+80000524:	c99ff0ef          	jal	ra,800001bc <vx_available_warps>
+80000528:	fea42023          	sw	a0,-32(s0)
+8000052c:	fe042623          	sw	zero,-20(s0)
+80000530:	0540006f          	j	80000584 <vx_wait_for_warps+0x74>
+80000534:	fe042623          	sw	zero,-20(s0)
+80000538:	fe042423          	sw	zero,-24(s0)
+8000053c:	03c0006f          	j	80000578 <vx_wait_for_warps+0x68>
+80000540:	810007b7          	lui	a5,0x81000
+80000544:	fe842703          	lw	a4,-24(s0)
+80000548:	00271713          	slli	a4,a4,0x2
+8000054c:	27c78793          	addi	a5,a5,636 # 8100027c <main_sp+0xffffa8c0>
+80000550:	00f707b3          	add	a5,a4,a5
+80000554:	0007a703          	lw	a4,0(a5)
+80000558:	00100793          	li	a5,1
+8000055c:	00f71863          	bne	a4,a5,8000056c <vx_wait_for_warps+0x5c>
+80000560:	fec42783          	lw	a5,-20(s0)
+80000564:	00178793          	addi	a5,a5,1
+80000568:	fef42623          	sw	a5,-20(s0)
+8000056c:	fe842783          	lw	a5,-24(s0)
+80000570:	00178793          	addi	a5,a5,1
+80000574:	fef42423          	sw	a5,-24(s0)
+80000578:	fe842783          	lw	a5,-24(s0)
+8000057c:	fe042703          	lw	a4,-32(s0)
+80000580:	fce7e0e3          	bltu	a5,a4,80000540 <vx_wait_for_warps+0x30>
+80000584:	fec42703          	lw	a4,-20(s0)
+80000588:	fdc42783          	lw	a5,-36(s0)
+8000058c:	faf714e3          	bne	a4,a5,80000534 <vx_wait_for_warps+0x24>
+80000590:	fe042223          	sw	zero,-28(s0)
+80000594:	0280006f          	j	800005bc <vx_wait_for_warps+0xac>
+80000598:	810007b7          	lui	a5,0x81000
+8000059c:	fe442703          	lw	a4,-28(s0)
+800005a0:	00271713          	slli	a4,a4,0x2
+800005a4:	27c78793          	addi	a5,a5,636 # 8100027c <main_sp+0xffffa8c0>
+800005a8:	00f707b3          	add	a5,a4,a5
+800005ac:	0007a023          	sw	zero,0(a5)
+800005b0:	fe442783          	lw	a5,-28(s0)
+800005b4:	00178793          	addi	a5,a5,1
+800005b8:	fef42223          	sw	a5,-28(s0)
+800005bc:	fe442783          	lw	a5,-28(s0)
+800005c0:	fe042703          	lw	a4,-32(s0)
+800005c4:	fce7eae3          	bltu	a5,a4,80000598 <vx_wait_for_warps+0x88>
+800005c8:	00000013          	nop
+800005cc:	02c12083          	lw	ra,44(sp)
+800005d0:	02812403          	lw	s0,40(sp)
+800005d4:	03010113          	addi	sp,sp,48
+800005d8:	00008067          	ret
 
-800005c4 <vx_get_arg_struct>:
-800005c4:	ff010113          	addi	sp,sp,-16
-800005c8:	00812623          	sw	s0,12(sp)
-800005cc:	01712423          	sw	s7,8(sp)
-800005d0:	01010413          	addi	s0,sp,16
-800005d4:	000b8793          	mv	a5,s7
-800005d8:	00078513          	mv	a0,a5
-800005dc:	00c12403          	lw	s0,12(sp)
-800005e0:	00812b83          	lw	s7,8(sp)
-800005e4:	01010113          	addi	sp,sp,16
-800005e8:	00008067          	ret
+800005dc <vx_get_arg_struct>:
+800005dc:	ff010113          	addi	sp,sp,-16
+800005e0:	00812623          	sw	s0,12(sp)
+800005e4:	01712423          	sw	s7,8(sp)
+800005e8:	01010413          	addi	s0,sp,16
+800005ec:	000b8793          	mv	a5,s7
+800005f0:	00078513          	mv	a0,a5
+800005f4:	00c12403          	lw	s0,12(sp)
+800005f8:	00812b83          	lw	s7,8(sp)
+800005fc:	01010113          	addi	sp,sp,16
+80000600:	00008067          	ret
 
-800005ec <queue_initialize>:
-800005ec:	00050293          	mv	t0,a0
-800005f0:	00000313          	li	t1,0
-800005f4:	00700393          	li	t2,7
-800005f8:	0062a023          	sw	t1,0(t0)
-800005fc:	0062a223          	sw	t1,4(t0)
-80000600:	0062a423          	sw	t1,8(t0)
-80000604:	0072a623          	sw	t2,12(t0)
-80000608:	0062a823          	sw	t1,16(t0)
-8000060c:	00008067          	ret
+80000604 <queue_initialize>:
+80000604:	00050293          	mv	t0,a0
+80000608:	00000313          	li	t1,0
+8000060c:	00700393          	li	t2,7
+80000610:	0062a023          	sw	t1,0(t0)
+80000614:	0062a223          	sw	t1,4(t0)
+80000618:	0062a423          	sw	t1,8(t0)
+8000061c:	0072a623          	sw	t2,12(t0)
+80000620:	0062a823          	sw	t1,16(t0)
+80000624:	00008067          	ret
 
-80000610 <queue_enqueue>:
-80000610:	00050293          	mv	t0,a0
-80000614:	0082a303          	lw	t1,8(t0)
-80000618:	00130313          	addi	t1,t1,1
-8000061c:	0062a423          	sw	t1,8(t0)
-80000620:	01428313          	addi	t1,t0,20
-80000624:	0042ae83          	lw	t4,4(t0)
-80000628:	005e9393          	slli	t2,t4,0x5
-8000062c:	00730333          	add	t1,t1,t2
-80000630:	0005ae03          	lw	t3,0(a1)
-80000634:	01c32023          	sw	t3,0(t1)
-80000638:	0045ae03          	lw	t3,4(a1)
-8000063c:	01c32223          	sw	t3,4(t1)
-80000640:	0085ae03          	lw	t3,8(a1)
-80000644:	01c32423          	sw	t3,8(t1)
-80000648:	00c5ae03          	lw	t3,12(a1)
-8000064c:	01c32623          	sw	t3,12(t1)
-80000650:	0105ae03          	lw	t3,16(a1)
-80000654:	01c32823          	sw	t3,16(t1)
-80000658:	0145ae03          	lw	t3,20(a1)
-8000065c:	01c32a23          	sw	t3,20(t1)
-80000660:	001e8e93          	addi	t4,t4,1
-80000664:	03200f13          	li	t5,50
-80000668:	01ee9463          	bne	t4,t5,80000670 <ec>
-8000066c:	00000e93          	li	t4,0
+80000628 <queue_enqueue>:
+80000628:	00050293          	mv	t0,a0
+8000062c:	0082a303          	lw	t1,8(t0)
+80000630:	00130313          	addi	t1,t1,1
+80000634:	0062a423          	sw	t1,8(t0)
+80000638:	01428313          	addi	t1,t0,20
+8000063c:	0042ae83          	lw	t4,4(t0)
+80000640:	005e9393          	slli	t2,t4,0x5
+80000644:	00730333          	add	t1,t1,t2
+80000648:	0005ae03          	lw	t3,0(a1)
+8000064c:	01c32023          	sw	t3,0(t1)
+80000650:	0045ae03          	lw	t3,4(a1)
+80000654:	01c32223          	sw	t3,4(t1)
+80000658:	0085ae03          	lw	t3,8(a1)
+8000065c:	01c32423          	sw	t3,8(t1)
+80000660:	00c5ae03          	lw	t3,12(a1)
+80000664:	01c32623          	sw	t3,12(t1)
+80000668:	0105ae03          	lw	t3,16(a1)
+8000066c:	01c32823          	sw	t3,16(t1)
+80000670:	0145ae03          	lw	t3,20(a1)
+80000674:	01c32a23          	sw	t3,20(t1)
+80000678:	001e8e93          	addi	t4,t4,1
+8000067c:	03200f13          	li	t5,50
+80000680:	01ee9463          	bne	t4,t5,80000688 <ec>
+80000684:	00000e93          	li	t4,0
 
-80000670 <ec>:
-80000670:	01d2a223          	sw	t4,4(t0)
-80000674:	00008067          	ret
+80000688 <ec>:
+80000688:	01d2a223          	sw	t4,4(t0)
+8000068c:	00008067          	ret
 
-80000678 <queue_dequeue>:
-80000678:	00050293          	mv	t0,a0
-8000067c:	0082a303          	lw	t1,8(t0)
-80000680:	fff30313          	addi	t1,t1,-1
-80000684:	0062a423          	sw	t1,8(t0)
-80000688:	01428313          	addi	t1,t0,20
-8000068c:	0002ae83          	lw	t4,0(t0)
-80000690:	03200f93          	li	t6,50
-80000694:	000e8f13          	mv	t5,t4
-80000698:	001f0f13          	addi	t5,t5,1
-8000069c:	01ff1463          	bne	t5,t6,800006a4 <dc>
-800006a0:	00000f13          	li	t5,0
+80000690 <queue_dequeue>:
+80000690:	00050293          	mv	t0,a0
+80000694:	0082a303          	lw	t1,8(t0)
+80000698:	fff30313          	addi	t1,t1,-1
+8000069c:	0062a423          	sw	t1,8(t0)
+800006a0:	01428313          	addi	t1,t0,20
+800006a4:	0002ae83          	lw	t4,0(t0)
+800006a8:	03200f93          	li	t6,50
+800006ac:	000e8f13          	mv	t5,t4
+800006b0:	001f0f13          	addi	t5,t5,1
+800006b4:	01ff1463          	bne	t5,t6,800006bc <dc>
+800006b8:	00000f13          	li	t5,0
 
-800006a4 <dc>:
-800006a4:	01e2a023          	sw	t5,0(t0)
-800006a8:	005e9393          	slli	t2,t4,0x5
-800006ac:	00730333          	add	t1,t1,t2
-800006b0:	00032e03          	lw	t3,0(t1)
-800006b4:	01c5a023          	sw	t3,0(a1)
-800006b8:	00432e03          	lw	t3,4(t1)
-800006bc:	01c5a223          	sw	t3,4(a1)
-800006c0:	00832e03          	lw	t3,8(t1)
-800006c4:	01c5a423          	sw	t3,8(a1)
-800006c8:	00c32e03          	lw	t3,12(t1)
-800006cc:	01c5a623          	sw	t3,12(a1)
-800006d0:	01032e03          	lw	t3,16(t1)
-800006d4:	01c5a823          	sw	t3,16(a1)
-800006d8:	01432e03          	lw	t3,20(t1)
-800006dc:	01c5aa23          	sw	t3,20(a1)
-800006e0:	00008067          	ret
+800006bc <dc>:
+800006bc:	01e2a023          	sw	t5,0(t0)
+800006c0:	005e9393          	slli	t2,t4,0x5
+800006c4:	00730333          	add	t1,t1,t2
+800006c8:	00032e03          	lw	t3,0(t1)
+800006cc:	01c5a023          	sw	t3,0(a1)
+800006d0:	00432e03          	lw	t3,4(t1)
+800006d4:	01c5a223          	sw	t3,4(a1)
+800006d8:	00832e03          	lw	t3,8(t1)
+800006dc:	01c5a423          	sw	t3,8(a1)
+800006e0:	00c32e03          	lw	t3,12(t1)
+800006e4:	01c5a623          	sw	t3,12(a1)
+800006e8:	01032e03          	lw	t3,16(t1)
+800006ec:	01c5a823          	sw	t3,16(a1)
+800006f0:	01432e03          	lw	t3,20(t1)
+800006f4:	01c5aa23          	sw	t3,20(a1)
+800006f8:	00008067          	ret
 
-800006e4 <queue_isFull>:
-800006e4:	00050293          	mv	t0,a0
-800006e8:	0082a303          	lw	t1,8(t0)
-800006ec:	00000513          	li	a0,0
-800006f0:	03200e13          	li	t3,50
-800006f4:	006e1463          	bne	t3,t1,800006fc <qf>
-800006f8:	00150513          	addi	a0,a0,1
+800006fc <queue_isFull>:
+800006fc:	00050293          	mv	t0,a0
+80000700:	0082a303          	lw	t1,8(t0)
+80000704:	00000513          	li	a0,0
+80000708:	03200e13          	li	t3,50
+8000070c:	006e1463          	bne	t3,t1,80000714 <qf>
+80000710:	00150513          	addi	a0,a0,1
 
-800006fc <qf>:
-800006fc:	00008067          	ret
+80000714 <qf>:
+80000714:	00008067          	ret
 
-80000700 <queue_isEmpty>:
-80000700:	00050293          	mv	t0,a0
-80000704:	0082a303          	lw	t1,8(t0)
-80000708:	00000513          	li	a0,0
-8000070c:	00000e13          	li	t3,0
-80000710:	006e1463          	bne	t3,t1,80000718 <qe>
-80000714:	00150513          	addi	a0,a0,1
+80000718 <queue_isEmpty>:
+80000718:	00050293          	mv	t0,a0
+8000071c:	0082a303          	lw	t1,8(t0)
+80000720:	00000513          	li	a0,0
+80000724:	00000e13          	li	t3,0
+80000728:	006e1463          	bne	t3,t1,80000730 <qe>
+8000072c:	00150513          	addi	a0,a0,1
 
-80000718 <qe>:
-80000718:	00008067          	ret
+80000730 <qe>:
+80000730:	00008067          	ret
 
-8000071c <queue_availableWarps>:
-8000071c:	00050293          	mv	t0,a0
-80000720:	00c2a303          	lw	t1,12(t0)
-80000724:	0102a383          	lw	t2,16(t0)
-80000728:	0063b533          	sltu	a0,t2,t1
-8000072c:	00008067          	ret
+80000734 <queue_availableWarps>:
+80000734:	00050293          	mv	t0,a0
+80000738:	00c2a303          	lw	t1,12(t0)
+8000073c:	0102a383          	lw	t2,16(t0)
+80000740:	0063b533          	sltu	a0,t2,t1
+80000744:	00008067          	ret
 
-80000730 <vx_print_str>:
-80000730:	ff410113          	addi	sp,sp,-12
-80000734:	00112023          	sw	ra,0(sp)
-80000738:	00b12223          	sw	a1,4(sp)
+80000748 <vx_print_str>:
+80000748:	ff410113          	addi	sp,sp,-12
+8000074c:	00112023          	sw	ra,0(sp)
+80000750:	00b12223          	sw	a1,4(sp)
 
-8000073c <bl>:
-8000073c:	00054583          	lbu	a1,0(a0)
-80000740:	00058863          	beqz	a1,80000750 <be>
-80000744:	01c000ef          	jal	ra,80000760 <vx_printc>
-80000748:	00150513          	addi	a0,a0,1
-8000074c:	ff1ff06f          	j	8000073c <bl>
+80000754 <bl>:
+80000754:	00054583          	lbu	a1,0(a0)
+80000758:	00058863          	beqz	a1,80000768 <be>
+8000075c:	01c000ef          	jal	ra,80000778 <vx_printc>
+80000760:	00150513          	addi	a0,a0,1
+80000764:	ff1ff06f          	j	80000754 <bl>
 
-80000750 <be>:
-80000750:	00012083          	lw	ra,0(sp)
-80000754:	00412583          	lw	a1,4(sp)
-80000758:	00c10113          	addi	sp,sp,12
-8000075c:	00008067          	ret
+80000768 <be>:
+80000768:	00012083          	lw	ra,0(sp)
+8000076c:	00412583          	lw	a1,4(sp)
+80000770:	00c10113          	addi	sp,sp,12
+80000774:	00008067          	ret
 
-80000760 <vx_printc>:
-80000760:	000108b7          	lui	a7,0x10
-80000764:	00b8a023          	sw	a1,0(a7) # 10000 <SIZE+0xffce>
-80000768:	00008067          	ret
+80000778 <vx_printc>:
+80000778:	000108b7          	lui	a7,0x10
+8000077c:	00b8a023          	sw	a1,0(a7) # 10000 <SIZE+0xffce>
+80000780:	00008067          	ret
 
-8000076c <vx_print_hex>:
-8000076c:	fd010113          	addi	sp,sp,-48
-80000770:	02112623          	sw	ra,44(sp)
-80000774:	02812423          	sw	s0,40(sp)
-80000778:	03010413          	addi	s0,sp,48
-8000077c:	fca42e23          	sw	a0,-36(s0)
-80000780:	fdc42703          	lw	a4,-36(s0)
-80000784:	00f00793          	li	a5,15
-80000788:	02e7e463          	bltu	a5,a4,800007b0 <vx_print_hex+0x44>
-8000078c:	810007b7          	lui	a5,0x81000
-80000790:	fdc42703          	lw	a4,-36(s0)
-80000794:	00271713          	slli	a4,a4,0x2
-80000798:	20478793          	addi	a5,a5,516 # 81000204 <main_sp+0xffffa800>
-8000079c:	00f707b3          	add	a5,a4,a5
-800007a0:	0007a783          	lw	a5,0(a5)
-800007a4:	00078513          	mv	a0,a5
-800007a8:	f89ff0ef          	jal	ra,80000730 <vx_print_str>
-800007ac:	0740006f          	j	80000820 <vx_print_hex+0xb4>
-800007b0:	02000793          	li	a5,32
-800007b4:	fef42623          	sw	a5,-20(s0)
-800007b8:	fe0405a3          	sb	zero,-21(s0)
-800007bc:	fec42783          	lw	a5,-20(s0)
-800007c0:	ffc78793          	addi	a5,a5,-4
-800007c4:	fdc42703          	lw	a4,-36(s0)
-800007c8:	00f757b3          	srl	a5,a4,a5
-800007cc:	00f7f793          	andi	a5,a5,15
-800007d0:	fef42223          	sw	a5,-28(s0)
-800007d4:	fe442783          	lw	a5,-28(s0)
-800007d8:	00078663          	beqz	a5,800007e4 <vx_print_hex+0x78>
-800007dc:	00100793          	li	a5,1
-800007e0:	fef405a3          	sb	a5,-21(s0)
-800007e4:	feb44783          	lbu	a5,-21(s0)
-800007e8:	02078263          	beqz	a5,8000080c <vx_print_hex+0xa0>
-800007ec:	810007b7          	lui	a5,0x81000
-800007f0:	fe442703          	lw	a4,-28(s0)
-800007f4:	00271713          	slli	a4,a4,0x2
-800007f8:	20478793          	addi	a5,a5,516 # 81000204 <main_sp+0xffffa800>
-800007fc:	00f707b3          	add	a5,a4,a5
-80000800:	0007a783          	lw	a5,0(a5)
-80000804:	00078513          	mv	a0,a5
-80000808:	f29ff0ef          	jal	ra,80000730 <vx_print_str>
-8000080c:	fec42783          	lw	a5,-20(s0)
-80000810:	ffc78793          	addi	a5,a5,-4
-80000814:	fef42623          	sw	a5,-20(s0)
-80000818:	fec42783          	lw	a5,-20(s0)
-8000081c:	faf040e3          	bgtz	a5,800007bc <vx_print_hex+0x50>
-80000820:	02c12083          	lw	ra,44(sp)
-80000824:	02812403          	lw	s0,40(sp)
-80000828:	03010113          	addi	sp,sp,48
-8000082c:	00008067          	ret
+80000784 <vx_print_hex>:
+80000784:	fd010113          	addi	sp,sp,-48
+80000788:	02112623          	sw	ra,44(sp)
+8000078c:	02812423          	sw	s0,40(sp)
+80000790:	03010413          	addi	s0,sp,48
+80000794:	fca42e23          	sw	a0,-36(s0)
+80000798:	fdc42703          	lw	a4,-36(s0)
+8000079c:	00f00793          	li	a5,15
+800007a0:	02e7e463          	bltu	a5,a4,800007c8 <vx_print_hex+0x44>
+800007a4:	810007b7          	lui	a5,0x81000
+800007a8:	fdc42703          	lw	a4,-36(s0)
+800007ac:	00271713          	slli	a4,a4,0x2
+800007b0:	1bc78793          	addi	a5,a5,444 # 810001bc <main_sp+0xffffa800>
+800007b4:	00f707b3          	add	a5,a4,a5
+800007b8:	0007a783          	lw	a5,0(a5)
+800007bc:	00078513          	mv	a0,a5
+800007c0:	f89ff0ef          	jal	ra,80000748 <vx_print_str>
+800007c4:	0740006f          	j	80000838 <vx_print_hex+0xb4>
+800007c8:	02000793          	li	a5,32
+800007cc:	fef42623          	sw	a5,-20(s0)
+800007d0:	fe0405a3          	sb	zero,-21(s0)
+800007d4:	fec42783          	lw	a5,-20(s0)
+800007d8:	ffc78793          	addi	a5,a5,-4
+800007dc:	fdc42703          	lw	a4,-36(s0)
+800007e0:	00f757b3          	srl	a5,a4,a5
+800007e4:	00f7f793          	andi	a5,a5,15
+800007e8:	fef42223          	sw	a5,-28(s0)
+800007ec:	fe442783          	lw	a5,-28(s0)
+800007f0:	00078663          	beqz	a5,800007fc <vx_print_hex+0x78>
+800007f4:	00100793          	li	a5,1
+800007f8:	fef405a3          	sb	a5,-21(s0)
+800007fc:	feb44783          	lbu	a5,-21(s0)
+80000800:	02078263          	beqz	a5,80000824 <vx_print_hex+0xa0>
+80000804:	810007b7          	lui	a5,0x81000
+80000808:	fe442703          	lw	a4,-28(s0)
+8000080c:	00271713          	slli	a4,a4,0x2
+80000810:	1bc78793          	addi	a5,a5,444 # 810001bc <main_sp+0xffffa800>
+80000814:	00f707b3          	add	a5,a4,a5
+80000818:	0007a783          	lw	a5,0(a5)
+8000081c:	00078513          	mv	a0,a5
+80000820:	f29ff0ef          	jal	ra,80000748 <vx_print_str>
+80000824:	fec42783          	lw	a5,-20(s0)
+80000828:	ffc78793          	addi	a5,a5,-4
+8000082c:	fef42623          	sw	a5,-20(s0)
+80000830:	fec42783          	lw	a5,-20(s0)
+80000834:	faf040e3          	bgtz	a5,800007d4 <vx_print_hex+0x50>
+80000838:	02c12083          	lw	ra,44(sp)
+8000083c:	02812403          	lw	s0,40(sp)
+80000840:	03010113          	addi	sp,sp,48
+80000844:	00008067          	ret
 
-80000830 <vx_printf>:
-80000830:	fe010113          	addi	sp,sp,-32
-80000834:	00112e23          	sw	ra,28(sp)
-80000838:	00812c23          	sw	s0,24(sp)
-8000083c:	02010413          	addi	s0,sp,32
-80000840:	fea42623          	sw	a0,-20(s0)
-80000844:	feb42423          	sw	a1,-24(s0)
-80000848:	fec42503          	lw	a0,-20(s0)
-8000084c:	ee5ff0ef          	jal	ra,80000730 <vx_print_str>
-80000850:	fe842503          	lw	a0,-24(s0)
-80000854:	f19ff0ef          	jal	ra,8000076c <vx_print_hex>
-80000858:	810007b7          	lui	a5,0x81000
-8000085c:	08078513          	addi	a0,a5,128 # 81000080 <main_sp+0xffffa67c>
-80000860:	ed1ff0ef          	jal	ra,80000730 <vx_print_str>
-80000864:	00000013          	nop
-80000868:	01c12083          	lw	ra,28(sp)
-8000086c:	01812403          	lw	s0,24(sp)
-80000870:	02010113          	addi	sp,sp,32
-80000874:	00008067          	ret
+80000848 <vx_printf>:
+80000848:	fe010113          	addi	sp,sp,-32
+8000084c:	00112e23          	sw	ra,28(sp)
+80000850:	00812c23          	sw	s0,24(sp)
+80000854:	02010413          	addi	s0,sp,32
+80000858:	fea42623          	sw	a0,-20(s0)
+8000085c:	feb42423          	sw	a1,-24(s0)
+80000860:	fec42503          	lw	a0,-20(s0)
+80000864:	ee5ff0ef          	jal	ra,80000748 <vx_print_str>
+80000868:	fe842503          	lw	a0,-24(s0)
+8000086c:	f19ff0ef          	jal	ra,80000784 <vx_print_hex>
+80000870:	810007b7          	lui	a5,0x81000
+80000874:	08078513          	addi	a0,a5,128 # 81000080 <main_sp+0xffffa6c4>
+80000878:	ed1ff0ef          	jal	ra,80000748 <vx_print_str>
+8000087c:	00000013          	nop
+80000880:	01c12083          	lw	ra,28(sp)
+80000884:	01812403          	lw	s0,24(sp)
+80000888:	02010113          	addi	sp,sp,32
+8000088c:	00008067          	ret
 
-80000878 <vx_sq_mat_mult>:
-80000878:	fd010113          	addi	sp,sp,-48
-8000087c:	02112623          	sw	ra,44(sp)
-80000880:	02812423          	sw	s0,40(sp)
-80000884:	03010413          	addi	s0,sp,48
-80000888:	fca42e23          	sw	a0,-36(s0)
-8000088c:	fcb42c23          	sw	a1,-40(s0)
-80000890:	fcc42a23          	sw	a2,-44(s0)
-80000894:	fcd42823          	sw	a3,-48(s0)
-80000898:	810037b7          	lui	a5,0x81003
-8000089c:	fdc42703          	lw	a4,-36(s0)
-800008a0:	9ae7a223          	sw	a4,-1628(a5) # 810029a4 <main_sp+0xffffcfa0>
-800008a4:	810037b7          	lui	a5,0x81003
-800008a8:	9a478793          	addi	a5,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-800008ac:	fd842703          	lw	a4,-40(s0)
-800008b0:	00e7a223          	sw	a4,4(a5)
-800008b4:	810037b7          	lui	a5,0x81003
-800008b8:	9a478793          	addi	a5,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-800008bc:	fd442703          	lw	a4,-44(s0)
-800008c0:	00e7a423          	sw	a4,8(a5)
-800008c4:	810037b7          	lui	a5,0x81003
-800008c8:	9a478793          	addi	a5,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-800008cc:	fd042703          	lw	a4,-48(s0)
-800008d0:	00e7a623          	sw	a4,12(a5)
-800008d4:	8d9ff0ef          	jal	ra,800001ac <vx_available_threads>
-800008d8:	fea42423          	sw	a0,-24(s0)
-800008dc:	fd042703          	lw	a4,-48(s0)
-800008e0:	fe842783          	lw	a5,-24(s0)
-800008e4:	02f757b3          	divu	a5,a4,a5
-800008e8:	fef42623          	sw	a5,-20(s0)
-800008ec:	fd042703          	lw	a4,-48(s0)
-800008f0:	fe842783          	lw	a5,-24(s0)
-800008f4:	02f777b3          	remu	a5,a4,a5
-800008f8:	00078863          	beqz	a5,80000908 <vx_sq_mat_mult+0x90>
-800008fc:	fec42783          	lw	a5,-20(s0)
-80000900:	00178793          	addi	a5,a5,1
-80000904:	fef42623          	sw	a5,-20(s0)
-80000908:	fec42583          	lw	a1,-20(s0)
-8000090c:	810007b7          	lui	a5,0x81000
-80000910:	0c478513          	addi	a0,a5,196 # 810000c4 <main_sp+0xffffa6c0>
-80000914:	f1dff0ef          	jal	ra,80000830 <vx_printf>
-80000918:	810037b7          	lui	a5,0x81003
-8000091c:	9a478793          	addi	a5,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-80000920:	fec42703          	lw	a4,-20(s0)
-80000924:	00e7a823          	sw	a4,16(a5)
-80000928:	fd042703          	lw	a4,-48(s0)
-8000092c:	fe842783          	lw	a5,-24(s0)
-80000930:	02f76263          	bltu	a4,a5,80000954 <vx_sq_mat_mult+0xdc>
-80000934:	810037b7          	lui	a5,0x81003
-80000938:	9a478693          	addi	a3,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-8000093c:	800017b7          	lui	a5,0x80001
-80000940:	9ac78613          	addi	a2,a5,-1620 # 800009ac <main_sp+0xfeffafa8>
-80000944:	fe842583          	lw	a1,-24(s0)
-80000948:	fd042503          	lw	a0,-48(s0)
-8000094c:	ac1ff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000950:	0200006f          	j	80000970 <vx_sq_mat_mult+0xf8>
-80000954:	810037b7          	lui	a5,0x81003
-80000958:	9a478693          	addi	a3,a5,-1628 # 810029a4 <main_sp+0xffffcfa0>
-8000095c:	800017b7          	lui	a5,0x80001
-80000960:	9ac78613          	addi	a2,a5,-1620 # 800009ac <main_sp+0xfeffafa8>
-80000964:	fd042583          	lw	a1,-48(s0)
-80000968:	fd042503          	lw	a0,-48(s0)
-8000096c:	aa1ff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000970:	835ff0ef          	jal	ra,800001a4 <vx_available_warps>
-80000974:	fea42223          	sw	a0,-28(s0)
-80000978:	fd042703          	lw	a4,-48(s0)
-8000097c:	fe442783          	lw	a5,-28(s0)
-80000980:	00e7f863          	bgeu	a5,a4,80000990 <vx_sq_mat_mult+0x118>
-80000984:	fe442503          	lw	a0,-28(s0)
-80000988:	b71ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-8000098c:	00c0006f          	j	80000998 <vx_sq_mat_mult+0x120>
-80000990:	fd042503          	lw	a0,-48(s0)
-80000994:	b65ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80000998:	00000013          	nop
-8000099c:	02c12083          	lw	ra,44(sp)
-800009a0:	02812403          	lw	s0,40(sp)
-800009a4:	03010113          	addi	sp,sp,48
-800009a8:	00008067          	ret
+80000890 <vx_sq_mat_mult>:
+80000890:	fd010113          	addi	sp,sp,-48
+80000894:	02112623          	sw	ra,44(sp)
+80000898:	02812423          	sw	s0,40(sp)
+8000089c:	03010413          	addi	s0,sp,48
+800008a0:	fca42e23          	sw	a0,-36(s0)
+800008a4:	fcb42c23          	sw	a1,-40(s0)
+800008a8:	fcc42a23          	sw	a2,-44(s0)
+800008ac:	fcd42823          	sw	a3,-48(s0)
+800008b0:	810037b7          	lui	a5,0x81003
+800008b4:	fdc42703          	lw	a4,-36(s0)
+800008b8:	94e7ae23          	sw	a4,-1700(a5) # 8100295c <main_sp+0xffffcfa0>
+800008bc:	810037b7          	lui	a5,0x81003
+800008c0:	95c78793          	addi	a5,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+800008c4:	fd842703          	lw	a4,-40(s0)
+800008c8:	00e7a223          	sw	a4,4(a5)
+800008cc:	810037b7          	lui	a5,0x81003
+800008d0:	95c78793          	addi	a5,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+800008d4:	fd442703          	lw	a4,-44(s0)
+800008d8:	00e7a423          	sw	a4,8(a5)
+800008dc:	810037b7          	lui	a5,0x81003
+800008e0:	95c78793          	addi	a5,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+800008e4:	fd042703          	lw	a4,-48(s0)
+800008e8:	00e7a623          	sw	a4,12(a5)
+800008ec:	8d9ff0ef          	jal	ra,800001c4 <vx_available_threads>
+800008f0:	fea42423          	sw	a0,-24(s0)
+800008f4:	fd042703          	lw	a4,-48(s0)
+800008f8:	fe842783          	lw	a5,-24(s0)
+800008fc:	02f757b3          	divu	a5,a4,a5
+80000900:	fef42623          	sw	a5,-20(s0)
+80000904:	fd042703          	lw	a4,-48(s0)
+80000908:	fe842783          	lw	a5,-24(s0)
+8000090c:	02f777b3          	remu	a5,a4,a5
+80000910:	00078863          	beqz	a5,80000920 <vx_sq_mat_mult+0x90>
+80000914:	fec42783          	lw	a5,-20(s0)
+80000918:	00178793          	addi	a5,a5,1
+8000091c:	fef42623          	sw	a5,-20(s0)
+80000920:	fec42583          	lw	a1,-20(s0)
+80000924:	810007b7          	lui	a5,0x81000
+80000928:	0c478513          	addi	a0,a5,196 # 810000c4 <main_sp+0xffffa708>
+8000092c:	f1dff0ef          	jal	ra,80000848 <vx_printf>
+80000930:	810037b7          	lui	a5,0x81003
+80000934:	95c78793          	addi	a5,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+80000938:	fec42703          	lw	a4,-20(s0)
+8000093c:	00e7a823          	sw	a4,16(a5)
+80000940:	fd042703          	lw	a4,-48(s0)
+80000944:	fe842783          	lw	a5,-24(s0)
+80000948:	02f76263          	bltu	a4,a5,8000096c <vx_sq_mat_mult+0xdc>
+8000094c:	810037b7          	lui	a5,0x81003
+80000950:	95c78693          	addi	a3,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+80000954:	800017b7          	lui	a5,0x80001
+80000958:	9c478613          	addi	a2,a5,-1596 # 800009c4 <main_sp+0xfeffb008>
+8000095c:	fe842583          	lw	a1,-24(s0)
+80000960:	fd042503          	lw	a0,-48(s0)
+80000964:	ac1ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000968:	0200006f          	j	80000988 <vx_sq_mat_mult+0xf8>
+8000096c:	810037b7          	lui	a5,0x81003
+80000970:	95c78693          	addi	a3,a5,-1700 # 8100295c <main_sp+0xffffcfa0>
+80000974:	800017b7          	lui	a5,0x80001
+80000978:	9c478613          	addi	a2,a5,-1596 # 800009c4 <main_sp+0xfeffb008>
+8000097c:	fd042583          	lw	a1,-48(s0)
+80000980:	fd042503          	lw	a0,-48(s0)
+80000984:	aa1ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000988:	835ff0ef          	jal	ra,800001bc <vx_available_warps>
+8000098c:	fea42223          	sw	a0,-28(s0)
+80000990:	fd042703          	lw	a4,-48(s0)
+80000994:	fe442783          	lw	a5,-28(s0)
+80000998:	00e7f863          	bgeu	a5,a4,800009a8 <vx_sq_mat_mult+0x118>
+8000099c:	fe442503          	lw	a0,-28(s0)
+800009a0:	b71ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+800009a4:	00c0006f          	j	800009b0 <vx_sq_mat_mult+0x120>
+800009a8:	fd042503          	lw	a0,-48(s0)
+800009ac:	b65ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+800009b0:	00000013          	nop
+800009b4:	02c12083          	lw	ra,44(sp)
+800009b8:	02812403          	lw	s0,40(sp)
+800009bc:	03010113          	addi	sp,sp,48
+800009c0:	00008067          	ret
 
-800009ac <_vx_mat_mult>:
-800009ac:	fa010113          	addi	sp,sp,-96
-800009b0:	04112e23          	sw	ra,92(sp)
-800009b4:	04812c23          	sw	s0,88(sp)
-800009b8:	06010413          	addi	s0,sp,96
-800009bc:	faa42623          	sw	a0,-84(s0)
-800009c0:	fab42423          	sw	a1,-88(s0)
-800009c4:	c01ff0ef          	jal	ra,800005c4 <vx_get_arg_struct>
-800009c8:	fca42c23          	sw	a0,-40(s0)
-800009cc:	fd842783          	lw	a5,-40(s0)
-800009d0:	0007a783          	lw	a5,0(a5)
-800009d4:	fcf42a23          	sw	a5,-44(s0)
-800009d8:	fd842783          	lw	a5,-40(s0)
-800009dc:	0047a783          	lw	a5,4(a5)
-800009e0:	fcf42823          	sw	a5,-48(s0)
+800009c4 <_vx_mat_mult>:
+800009c4:	fa010113          	addi	sp,sp,-96
+800009c8:	04112e23          	sw	ra,92(sp)
+800009cc:	04812c23          	sw	s0,88(sp)
+800009d0:	06010413          	addi	s0,sp,96
+800009d4:	faa42623          	sw	a0,-84(s0)
+800009d8:	fab42423          	sw	a1,-88(s0)
+800009dc:	c01ff0ef          	jal	ra,800005dc <vx_get_arg_struct>
+800009e0:	fca42c23          	sw	a0,-40(s0)
 800009e4:	fd842783          	lw	a5,-40(s0)
-800009e8:	0087a783          	lw	a5,8(a5)
-800009ec:	fcf42623          	sw	a5,-52(s0)
+800009e8:	0007a783          	lw	a5,0(a5)
+800009ec:	fcf42a23          	sw	a5,-44(s0)
 800009f0:	fd842783          	lw	a5,-40(s0)
-800009f4:	0107a783          	lw	a5,16(a5)
-800009f8:	fef42623          	sw	a5,-20(s0)
-800009fc:	fec42703          	lw	a4,-20(s0)
-80000a00:	fac42783          	lw	a5,-84(s0)
-80000a04:	02f707b3          	mul	a5,a4,a5
-80000a08:	fef42423          	sw	a5,-24(s0)
-80000a0c:	fec42783          	lw	a5,-20(s0)
-80000a10:	00079a63          	bnez	a5,80000a24 <_vx_mat_mult+0x78>
-80000a14:	00100793          	li	a5,1
-80000a18:	fef42623          	sw	a5,-20(s0)
-80000a1c:	fac42783          	lw	a5,-84(s0)
+800009f4:	0047a783          	lw	a5,4(a5)
+800009f8:	fcf42823          	sw	a5,-48(s0)
+800009fc:	fd842783          	lw	a5,-40(s0)
+80000a00:	0087a783          	lw	a5,8(a5)
+80000a04:	fcf42623          	sw	a5,-52(s0)
+80000a08:	fd842783          	lw	a5,-40(s0)
+80000a0c:	0107a783          	lw	a5,16(a5)
+80000a10:	fef42623          	sw	a5,-20(s0)
+80000a14:	fec42703          	lw	a4,-20(s0)
+80000a18:	fac42783          	lw	a5,-84(s0)
+80000a1c:	02f707b3          	mul	a5,a4,a5
 80000a20:	fef42423          	sw	a5,-24(s0)
-80000a24:	fd842783          	lw	a5,-40(s0)
-80000a28:	00c7a783          	lw	a5,12(a5)
-80000a2c:	fcf42423          	sw	a5,-56(s0)
-80000a30:	fe042223          	sw	zero,-28(s0)
-80000a34:	1240006f          	j	80000b58 <_vx_mat_mult+0x1ac>
-80000a38:	fe042023          	sw	zero,-32(s0)
-80000a3c:	fc042e23          	sw	zero,-36(s0)
-80000a40:	0780006f          	j	80000ab8 <_vx_mat_mult+0x10c>
-80000a44:	fa842703          	lw	a4,-88(s0)
-80000a48:	fc842783          	lw	a5,-56(s0)
-80000a4c:	02f707b3          	mul	a5,a4,a5
-80000a50:	fdc42703          	lw	a4,-36(s0)
-80000a54:	00f707b3          	add	a5,a4,a5
-80000a58:	fcf42223          	sw	a5,-60(s0)
-80000a5c:	fc842703          	lw	a4,-56(s0)
-80000a60:	fdc42783          	lw	a5,-36(s0)
+80000a24:	fec42783          	lw	a5,-20(s0)
+80000a28:	00079a63          	bnez	a5,80000a3c <_vx_mat_mult+0x78>
+80000a2c:	00100793          	li	a5,1
+80000a30:	fef42623          	sw	a5,-20(s0)
+80000a34:	fac42783          	lw	a5,-84(s0)
+80000a38:	fef42423          	sw	a5,-24(s0)
+80000a3c:	fd842783          	lw	a5,-40(s0)
+80000a40:	00c7a783          	lw	a5,12(a5)
+80000a44:	fcf42423          	sw	a5,-56(s0)
+80000a48:	fe042223          	sw	zero,-28(s0)
+80000a4c:	0d80006f          	j	80000b24 <_vx_mat_mult+0x160>
+80000a50:	fe042023          	sw	zero,-32(s0)
+80000a54:	fc042e23          	sw	zero,-36(s0)
+80000a58:	0780006f          	j	80000ad0 <_vx_mat_mult+0x10c>
+80000a5c:	fa842703          	lw	a4,-88(s0)
+80000a60:	fc842783          	lw	a5,-56(s0)
 80000a64:	02f707b3          	mul	a5,a4,a5
-80000a68:	fe842703          	lw	a4,-24(s0)
+80000a68:	fdc42703          	lw	a4,-36(s0)
 80000a6c:	00f707b3          	add	a5,a4,a5
-80000a70:	fcf42023          	sw	a5,-64(s0)
-80000a74:	fc442783          	lw	a5,-60(s0)
-80000a78:	00279793          	slli	a5,a5,0x2
-80000a7c:	fd442703          	lw	a4,-44(s0)
-80000a80:	00f707b3          	add	a5,a4,a5
-80000a84:	0007a703          	lw	a4,0(a5)
-80000a88:	fc042783          	lw	a5,-64(s0)
-80000a8c:	00279793          	slli	a5,a5,0x2
-80000a90:	fd042683          	lw	a3,-48(s0)
-80000a94:	00f687b3          	add	a5,a3,a5
-80000a98:	0007a783          	lw	a5,0(a5)
-80000a9c:	02f707b3          	mul	a5,a4,a5
-80000aa0:	fe042703          	lw	a4,-32(s0)
-80000aa4:	00f707b3          	add	a5,a4,a5
-80000aa8:	fef42023          	sw	a5,-32(s0)
-80000aac:	fdc42783          	lw	a5,-36(s0)
-80000ab0:	00178793          	addi	a5,a5,1
-80000ab4:	fcf42e23          	sw	a5,-36(s0)
-80000ab8:	fdc42703          	lw	a4,-36(s0)
-80000abc:	fc842783          	lw	a5,-56(s0)
-80000ac0:	f8f762e3          	bltu	a4,a5,80000a44 <_vx_mat_mult+0x98>
-80000ac4:	fa842703          	lw	a4,-88(s0)
-80000ac8:	fc842783          	lw	a5,-56(s0)
-80000acc:	02f70733          	mul	a4,a4,a5
-80000ad0:	fe842783          	lw	a5,-24(s0)
-80000ad4:	00f707b3          	add	a5,a4,a5
-80000ad8:	faf42e23          	sw	a5,-68(s0)
-80000adc:	fe842703          	lw	a4,-24(s0)
+80000a70:	fcf42223          	sw	a5,-60(s0)
+80000a74:	fc842703          	lw	a4,-56(s0)
+80000a78:	fdc42783          	lw	a5,-36(s0)
+80000a7c:	02f707b3          	mul	a5,a4,a5
+80000a80:	fe842703          	lw	a4,-24(s0)
+80000a84:	00f707b3          	add	a5,a4,a5
+80000a88:	fcf42023          	sw	a5,-64(s0)
+80000a8c:	fc442783          	lw	a5,-60(s0)
+80000a90:	00279793          	slli	a5,a5,0x2
+80000a94:	fd442703          	lw	a4,-44(s0)
+80000a98:	00f707b3          	add	a5,a4,a5
+80000a9c:	0007a703          	lw	a4,0(a5)
+80000aa0:	fc042783          	lw	a5,-64(s0)
+80000aa4:	00279793          	slli	a5,a5,0x2
+80000aa8:	fd042683          	lw	a3,-48(s0)
+80000aac:	00f687b3          	add	a5,a3,a5
+80000ab0:	0007a783          	lw	a5,0(a5)
+80000ab4:	02f707b3          	mul	a5,a4,a5
+80000ab8:	fe042703          	lw	a4,-32(s0)
+80000abc:	00f707b3          	add	a5,a4,a5
+80000ac0:	fef42023          	sw	a5,-32(s0)
+80000ac4:	fdc42783          	lw	a5,-36(s0)
+80000ac8:	00178793          	addi	a5,a5,1
+80000acc:	fcf42e23          	sw	a5,-36(s0)
+80000ad0:	fdc42703          	lw	a4,-36(s0)
+80000ad4:	fc842783          	lw	a5,-56(s0)
+80000ad8:	f8f762e3          	bltu	a4,a5,80000a5c <_vx_mat_mult+0x98>
+80000adc:	fa842703          	lw	a4,-88(s0)
 80000ae0:	fc842783          	lw	a5,-56(s0)
-80000ae4:	00f737b3          	sltu	a5,a4,a5
-80000ae8:	0ff7f793          	andi	a5,a5,255
-80000aec:	faf42c23          	sw	a5,-72(s0)
-80000af0:	fb842783          	lw	a5,-72(s0)
-80000af4:	0017b793          	seqz	a5,a5
-80000af8:	faf40ba3          	sb	a5,-73(s0)
-80000afc:	fb744783          	lbu	a5,-73(s0)
-80000b00:	00078f13          	mv	t5,a5
-80000b04:	800017b7          	lui	a5,0x80001
-80000b08:	b4478f93          	addi	t6,a5,-1212 # 80000b44 <main_sp+0xfeffb140>
-80000b0c:	000f206b          	0xf206b
-80000b10:	01ff707b          	0x1ff707b
-80000b14:	fbc42783          	lw	a5,-68(s0)
-80000b18:	00279793          	slli	a5,a5,0x2
-80000b1c:	fcc42703          	lw	a4,-52(s0)
-80000b20:	00f707b3          	add	a5,a4,a5
-80000b24:	fe042703          	lw	a4,-32(s0)
-80000b28:	00e7a023          	sw	a4,0(a5)
-80000b2c:	fe842783          	lw	a5,-24(s0)
-80000b30:	00178793          	addi	a5,a5,1
-80000b34:	fef42423          	sw	a5,-24(s0)
-80000b38:	800017b7          	lui	a5,0x80001
-80000b3c:	b4878e13          	addi	t3,a5,-1208 # 80000b48 <main_sp+0xfeffb144>
-80000b40:	000e0067          	jr	t3
-80000b44:	00000013          	nop
-80000b48:	0000306b          	0x306b
-80000b4c:	fe442783          	lw	a5,-28(s0)
-80000b50:	00178793          	addi	a5,a5,1
-80000b54:	fef42223          	sw	a5,-28(s0)
-80000b58:	fe442783          	lw	a5,-28(s0)
-80000b5c:	fec42703          	lw	a4,-20(s0)
-80000b60:	ece7ece3          	bltu	a5,a4,80000a38 <_vx_mat_mult+0x8c>
-80000b64:	00000013          	nop
-80000b68:	05c12083          	lw	ra,92(sp)
-80000b6c:	05812403          	lw	s0,88(sp)
-80000b70:	06010113          	addi	sp,sp,96
-80000b74:	00008067          	ret
+80000ae4:	02f70733          	mul	a4,a4,a5
+80000ae8:	fe842783          	lw	a5,-24(s0)
+80000aec:	00f707b3          	add	a5,a4,a5
+80000af0:	faf42e23          	sw	a5,-68(s0)
+80000af4:	fbc42783          	lw	a5,-68(s0)
+80000af8:	00279793          	slli	a5,a5,0x2
+80000afc:	fcc42703          	lw	a4,-52(s0)
+80000b00:	00f707b3          	add	a5,a4,a5
+80000b04:	fe042703          	lw	a4,-32(s0)
+80000b08:	00e7a023          	sw	a4,0(a5)
+80000b0c:	fe842783          	lw	a5,-24(s0)
+80000b10:	00178793          	addi	a5,a5,1
+80000b14:	fef42423          	sw	a5,-24(s0)
+80000b18:	fe442783          	lw	a5,-28(s0)
+80000b1c:	00178793          	addi	a5,a5,1
+80000b20:	fef42223          	sw	a5,-28(s0)
+80000b24:	fe442783          	lw	a5,-28(s0)
+80000b28:	fec42703          	lw	a4,-20(s0)
+80000b2c:	f2e7e2e3          	bltu	a5,a4,80000a50 <_vx_mat_mult+0x8c>
+80000b30:	00000013          	nop
+80000b34:	05c12083          	lw	ra,92(sp)
+80000b38:	05812403          	lw	s0,88(sp)
+80000b3c:	06010113          	addi	sp,sp,96
+80000b40:	00008067          	ret
 
-80000b78 <vx_mat_add>:
-80000b78:	fc010113          	addi	sp,sp,-64
-80000b7c:	02112e23          	sw	ra,60(sp)
-80000b80:	02812c23          	sw	s0,56(sp)
-80000b84:	04010413          	addi	s0,sp,64
-80000b88:	fca42e23          	sw	a0,-36(s0)
-80000b8c:	fcb42c23          	sw	a1,-40(s0)
-80000b90:	fcc42a23          	sw	a2,-44(s0)
-80000b94:	fcd42823          	sw	a3,-48(s0)
-80000b98:	fce42623          	sw	a4,-52(s0)
-80000b9c:	810037b7          	lui	a5,0x81003
-80000ba0:	fdc42703          	lw	a4,-36(s0)
-80000ba4:	9ae7ac23          	sw	a4,-1608(a5) # 810029b8 <main_sp+0xffffcfb4>
-80000ba8:	810037b7          	lui	a5,0x81003
-80000bac:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000bb0:	fd842703          	lw	a4,-40(s0)
-80000bb4:	00e7a223          	sw	a4,4(a5)
-80000bb8:	810037b7          	lui	a5,0x81003
-80000bbc:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000bc0:	fd442703          	lw	a4,-44(s0)
-80000bc4:	00e7a423          	sw	a4,8(a5)
-80000bc8:	810037b7          	lui	a5,0x81003
-80000bcc:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000bd0:	fcc42703          	lw	a4,-52(s0)
-80000bd4:	00e7a623          	sw	a4,12(a5)
-80000bd8:	810037b7          	lui	a5,0x81003
-80000bdc:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000be0:	fd042703          	lw	a4,-48(s0)
-80000be4:	00e7a823          	sw	a4,16(a5)
-80000be8:	dc4ff0ef          	jal	ra,800001ac <vx_available_threads>
-80000bec:	fea42423          	sw	a0,-24(s0)
-80000bf0:	fcc42703          	lw	a4,-52(s0)
-80000bf4:	fe842783          	lw	a5,-24(s0)
-80000bf8:	02f757b3          	divu	a5,a4,a5
-80000bfc:	fef42623          	sw	a5,-20(s0)
-80000c00:	fcc42703          	lw	a4,-52(s0)
-80000c04:	fe842783          	lw	a5,-24(s0)
-80000c08:	02f777b3          	remu	a5,a4,a5
-80000c0c:	00078863          	beqz	a5,80000c1c <vx_mat_add+0xa4>
-80000c10:	fec42783          	lw	a5,-20(s0)
-80000c14:	00178793          	addi	a5,a5,1
-80000c18:	fef42623          	sw	a5,-20(s0)
-80000c1c:	810037b7          	lui	a5,0x81003
-80000c20:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000c24:	fec42703          	lw	a4,-20(s0)
-80000c28:	00e7aa23          	sw	a4,20(a5)
-80000c2c:	fcc42703          	lw	a4,-52(s0)
-80000c30:	fe842783          	lw	a5,-24(s0)
-80000c34:	02f76263          	bltu	a4,a5,80000c58 <vx_mat_add+0xe0>
-80000c38:	810037b7          	lui	a5,0x81003
-80000c3c:	9b878693          	addi	a3,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000c40:	800017b7          	lui	a5,0x80001
-80000c44:	cb078613          	addi	a2,a5,-848 # 80000cb0 <main_sp+0xfeffb2ac>
-80000c48:	fe842583          	lw	a1,-24(s0)
-80000c4c:	fd042503          	lw	a0,-48(s0)
-80000c50:	fbcff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000c54:	0200006f          	j	80000c74 <vx_mat_add+0xfc>
-80000c58:	810037b7          	lui	a5,0x81003
-80000c5c:	9b878693          	addi	a3,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000c60:	800017b7          	lui	a5,0x80001
-80000c64:	cb078613          	addi	a2,a5,-848 # 80000cb0 <main_sp+0xfeffb2ac>
-80000c68:	fcc42583          	lw	a1,-52(s0)
-80000c6c:	fd042503          	lw	a0,-48(s0)
-80000c70:	f9cff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000c74:	d30ff0ef          	jal	ra,800001a4 <vx_available_warps>
-80000c78:	fea42223          	sw	a0,-28(s0)
-80000c7c:	fd042703          	lw	a4,-48(s0)
-80000c80:	fe442783          	lw	a5,-28(s0)
-80000c84:	00e7f863          	bgeu	a5,a4,80000c94 <vx_mat_add+0x11c>
-80000c88:	fe442503          	lw	a0,-28(s0)
-80000c8c:	86dff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80000c90:	00c0006f          	j	80000c9c <vx_mat_add+0x124>
-80000c94:	fd042503          	lw	a0,-48(s0)
-80000c98:	861ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80000c9c:	00000013          	nop
-80000ca0:	03c12083          	lw	ra,60(sp)
-80000ca4:	03812403          	lw	s0,56(sp)
-80000ca8:	04010113          	addi	sp,sp,64
-80000cac:	00008067          	ret
+80000b44 <vx_mat_add>:
+80000b44:	fc010113          	addi	sp,sp,-64
+80000b48:	02112e23          	sw	ra,60(sp)
+80000b4c:	02812c23          	sw	s0,56(sp)
+80000b50:	04010413          	addi	s0,sp,64
+80000b54:	fca42e23          	sw	a0,-36(s0)
+80000b58:	fcb42c23          	sw	a1,-40(s0)
+80000b5c:	fcc42a23          	sw	a2,-44(s0)
+80000b60:	fcd42823          	sw	a3,-48(s0)
+80000b64:	fce42623          	sw	a4,-52(s0)
+80000b68:	810037b7          	lui	a5,0x81003
+80000b6c:	fdc42703          	lw	a4,-36(s0)
+80000b70:	96e7a823          	sw	a4,-1680(a5) # 81002970 <main_sp+0xffffcfb4>
+80000b74:	810037b7          	lui	a5,0x81003
+80000b78:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000b7c:	fd842703          	lw	a4,-40(s0)
+80000b80:	00e7a223          	sw	a4,4(a5)
+80000b84:	810037b7          	lui	a5,0x81003
+80000b88:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000b8c:	fd442703          	lw	a4,-44(s0)
+80000b90:	00e7a423          	sw	a4,8(a5)
+80000b94:	810037b7          	lui	a5,0x81003
+80000b98:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000b9c:	fcc42703          	lw	a4,-52(s0)
+80000ba0:	00e7a623          	sw	a4,12(a5)
+80000ba4:	810037b7          	lui	a5,0x81003
+80000ba8:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000bac:	fd042703          	lw	a4,-48(s0)
+80000bb0:	00e7a823          	sw	a4,16(a5)
+80000bb4:	e10ff0ef          	jal	ra,800001c4 <vx_available_threads>
+80000bb8:	fea42423          	sw	a0,-24(s0)
+80000bbc:	fcc42703          	lw	a4,-52(s0)
+80000bc0:	fe842783          	lw	a5,-24(s0)
+80000bc4:	02f757b3          	divu	a5,a4,a5
+80000bc8:	fef42623          	sw	a5,-20(s0)
+80000bcc:	fcc42703          	lw	a4,-52(s0)
+80000bd0:	fe842783          	lw	a5,-24(s0)
+80000bd4:	02f777b3          	remu	a5,a4,a5
+80000bd8:	00078863          	beqz	a5,80000be8 <vx_mat_add+0xa4>
+80000bdc:	fec42783          	lw	a5,-20(s0)
+80000be0:	00178793          	addi	a5,a5,1
+80000be4:	fef42623          	sw	a5,-20(s0)
+80000be8:	810037b7          	lui	a5,0x81003
+80000bec:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000bf0:	fec42703          	lw	a4,-20(s0)
+80000bf4:	00e7aa23          	sw	a4,20(a5)
+80000bf8:	fcc42703          	lw	a4,-52(s0)
+80000bfc:	fe842783          	lw	a5,-24(s0)
+80000c00:	02f76263          	bltu	a4,a5,80000c24 <vx_mat_add+0xe0>
+80000c04:	810037b7          	lui	a5,0x81003
+80000c08:	97078693          	addi	a3,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000c0c:	800017b7          	lui	a5,0x80001
+80000c10:	c7c78613          	addi	a2,a5,-900 # 80000c7c <main_sp+0xfeffb2c0>
+80000c14:	fe842583          	lw	a1,-24(s0)
+80000c18:	fd042503          	lw	a0,-48(s0)
+80000c1c:	809ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000c20:	0200006f          	j	80000c40 <vx_mat_add+0xfc>
+80000c24:	810037b7          	lui	a5,0x81003
+80000c28:	97078693          	addi	a3,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000c2c:	800017b7          	lui	a5,0x80001
+80000c30:	c7c78613          	addi	a2,a5,-900 # 80000c7c <main_sp+0xfeffb2c0>
+80000c34:	fcc42583          	lw	a1,-52(s0)
+80000c38:	fd042503          	lw	a0,-48(s0)
+80000c3c:	fe8ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000c40:	d7cff0ef          	jal	ra,800001bc <vx_available_warps>
+80000c44:	fea42223          	sw	a0,-28(s0)
+80000c48:	fd042703          	lw	a4,-48(s0)
+80000c4c:	fe442783          	lw	a5,-28(s0)
+80000c50:	00e7f863          	bgeu	a5,a4,80000c60 <vx_mat_add+0x11c>
+80000c54:	fe442503          	lw	a0,-28(s0)
+80000c58:	8b9ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+80000c5c:	00c0006f          	j	80000c68 <vx_mat_add+0x124>
+80000c60:	fd042503          	lw	a0,-48(s0)
+80000c64:	8adff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+80000c68:	00000013          	nop
+80000c6c:	03c12083          	lw	ra,60(sp)
+80000c70:	03812403          	lw	s0,56(sp)
+80000c74:	04010113          	addi	sp,sp,64
+80000c78:	00008067          	ret
 
-80000cb0 <_vx_mat_add>:
-80000cb0:	fb010113          	addi	sp,sp,-80
-80000cb4:	04112623          	sw	ra,76(sp)
-80000cb8:	04812423          	sw	s0,72(sp)
-80000cbc:	05010413          	addi	s0,sp,80
-80000cc0:	faa42e23          	sw	a0,-68(s0)
-80000cc4:	fab42c23          	sw	a1,-72(s0)
-80000cc8:	8fdff0ef          	jal	ra,800005c4 <vx_get_arg_struct>
-80000ccc:	fea42023          	sw	a0,-32(s0)
-80000cd0:	fe042783          	lw	a5,-32(s0)
-80000cd4:	0007a783          	lw	a5,0(a5)
-80000cd8:	fcf42e23          	sw	a5,-36(s0)
-80000cdc:	fe042783          	lw	a5,-32(s0)
-80000ce0:	0047a783          	lw	a5,4(a5)
-80000ce4:	fcf42c23          	sw	a5,-40(s0)
-80000ce8:	fe042783          	lw	a5,-32(s0)
-80000cec:	0087a783          	lw	a5,8(a5)
-80000cf0:	fcf42a23          	sw	a5,-44(s0)
+80000c7c <_vx_mat_add>:
+80000c7c:	fb010113          	addi	sp,sp,-80
+80000c80:	04112623          	sw	ra,76(sp)
+80000c84:	04812423          	sw	s0,72(sp)
+80000c88:	05010413          	addi	s0,sp,80
+80000c8c:	faa42e23          	sw	a0,-68(s0)
+80000c90:	fab42c23          	sw	a1,-72(s0)
+80000c94:	949ff0ef          	jal	ra,800005dc <vx_get_arg_struct>
+80000c98:	fea42023          	sw	a0,-32(s0)
+80000c9c:	fe042783          	lw	a5,-32(s0)
+80000ca0:	0007a783          	lw	a5,0(a5)
+80000ca4:	fcf42e23          	sw	a5,-36(s0)
+80000ca8:	fe042783          	lw	a5,-32(s0)
+80000cac:	0047a783          	lw	a5,4(a5)
+80000cb0:	fcf42c23          	sw	a5,-40(s0)
+80000cb4:	fe042783          	lw	a5,-32(s0)
+80000cb8:	0087a783          	lw	a5,8(a5)
+80000cbc:	fcf42a23          	sw	a5,-44(s0)
+80000cc0:	fe042783          	lw	a5,-32(s0)
+80000cc4:	0147a783          	lw	a5,20(a5)
+80000cc8:	fef42623          	sw	a5,-20(s0)
+80000ccc:	fec42703          	lw	a4,-20(s0)
+80000cd0:	fbc42783          	lw	a5,-68(s0)
+80000cd4:	02f707b3          	mul	a5,a4,a5
+80000cd8:	fef42423          	sw	a5,-24(s0)
+80000cdc:	fec42783          	lw	a5,-20(s0)
+80000ce0:	00079a63          	bnez	a5,80000cf4 <_vx_mat_add+0x78>
+80000ce4:	00100793          	li	a5,1
+80000ce8:	fef42623          	sw	a5,-20(s0)
+80000cec:	fbc42783          	lw	a5,-68(s0)
+80000cf0:	fef42423          	sw	a5,-24(s0)
 80000cf4:	fe042783          	lw	a5,-32(s0)
-80000cf8:	0147a783          	lw	a5,20(a5)
-80000cfc:	fef42623          	sw	a5,-20(s0)
-80000d00:	fec42703          	lw	a4,-20(s0)
-80000d04:	fbc42783          	lw	a5,-68(s0)
-80000d08:	02f707b3          	mul	a5,a4,a5
-80000d0c:	fef42423          	sw	a5,-24(s0)
-80000d10:	fec42783          	lw	a5,-20(s0)
-80000d14:	00079a63          	bnez	a5,80000d28 <_vx_mat_add+0x78>
-80000d18:	00100793          	li	a5,1
-80000d1c:	fef42623          	sw	a5,-20(s0)
-80000d20:	fbc42783          	lw	a5,-68(s0)
-80000d24:	fef42423          	sw	a5,-24(s0)
-80000d28:	fe042783          	lw	a5,-32(s0)
-80000d2c:	00c7a783          	lw	a5,12(a5)
-80000d30:	fcf42823          	sw	a5,-48(s0)
-80000d34:	fe042223          	sw	zero,-28(s0)
-80000d38:	0c00006f          	j	80000df8 <_vx_mat_add+0x148>
-80000d3c:	fb842703          	lw	a4,-72(s0)
-80000d40:	fd042783          	lw	a5,-48(s0)
-80000d44:	02f70733          	mul	a4,a4,a5
-80000d48:	fe842783          	lw	a5,-24(s0)
-80000d4c:	00f707b3          	add	a5,a4,a5
-80000d50:	fcf42623          	sw	a5,-52(s0)
-80000d54:	fe842703          	lw	a4,-24(s0)
-80000d58:	fd042783          	lw	a5,-48(s0)
-80000d5c:	00f737b3          	sltu	a5,a4,a5
-80000d60:	0ff7f793          	andi	a5,a5,255
-80000d64:	fcf42423          	sw	a5,-56(s0)
-80000d68:	fc842783          	lw	a5,-56(s0)
-80000d6c:	0017b793          	seqz	a5,a5
-80000d70:	fcf403a3          	sb	a5,-57(s0)
-80000d74:	fc744783          	lbu	a5,-57(s0)
-80000d78:	00078f13          	mv	t5,a5
-80000d7c:	800017b7          	lui	a5,0x80001
-80000d80:	de478f93          	addi	t6,a5,-540 # 80000de4 <main_sp+0xfeffb3e0>
-80000d84:	000f206b          	0xf206b
-80000d88:	01ff707b          	0x1ff707b
-80000d8c:	fcc42783          	lw	a5,-52(s0)
-80000d90:	00279793          	slli	a5,a5,0x2
-80000d94:	fdc42703          	lw	a4,-36(s0)
-80000d98:	00f707b3          	add	a5,a4,a5
-80000d9c:	0007a683          	lw	a3,0(a5)
-80000da0:	fcc42783          	lw	a5,-52(s0)
-80000da4:	00279793          	slli	a5,a5,0x2
-80000da8:	fd842703          	lw	a4,-40(s0)
-80000dac:	00f707b3          	add	a5,a4,a5
-80000db0:	0007a703          	lw	a4,0(a5)
-80000db4:	fcc42783          	lw	a5,-52(s0)
-80000db8:	00279793          	slli	a5,a5,0x2
-80000dbc:	fd442603          	lw	a2,-44(s0)
-80000dc0:	00f607b3          	add	a5,a2,a5
-80000dc4:	00e68733          	add	a4,a3,a4
-80000dc8:	00e7a023          	sw	a4,0(a5)
-80000dcc:	fe842783          	lw	a5,-24(s0)
-80000dd0:	00178793          	addi	a5,a5,1
-80000dd4:	fef42423          	sw	a5,-24(s0)
-80000dd8:	800017b7          	lui	a5,0x80001
-80000ddc:	de878e13          	addi	t3,a5,-536 # 80000de8 <main_sp+0xfeffb3e4>
-80000de0:	000e0067          	jr	t3
-80000de4:	00000013          	nop
-80000de8:	0000306b          	0x306b
-80000dec:	fe442783          	lw	a5,-28(s0)
-80000df0:	00178793          	addi	a5,a5,1
-80000df4:	fef42223          	sw	a5,-28(s0)
-80000df8:	fe442783          	lw	a5,-28(s0)
-80000dfc:	fec42703          	lw	a4,-20(s0)
-80000e00:	f2e7eee3          	bltu	a5,a4,80000d3c <_vx_mat_add+0x8c>
-80000e04:	00000013          	nop
-80000e08:	04c12083          	lw	ra,76(sp)
-80000e0c:	04812403          	lw	s0,72(sp)
-80000e10:	05010113          	addi	sp,sp,80
-80000e14:	00008067          	ret
+80000cf8:	00c7a783          	lw	a5,12(a5)
+80000cfc:	fcf42823          	sw	a5,-48(s0)
+80000d00:	fe042223          	sw	zero,-28(s0)
+80000d04:	0c00006f          	j	80000dc4 <_vx_mat_add+0x148>
+80000d08:	fb842703          	lw	a4,-72(s0)
+80000d0c:	fd042783          	lw	a5,-48(s0)
+80000d10:	02f70733          	mul	a4,a4,a5
+80000d14:	fe842783          	lw	a5,-24(s0)
+80000d18:	00f707b3          	add	a5,a4,a5
+80000d1c:	fcf42623          	sw	a5,-52(s0)
+80000d20:	fe842703          	lw	a4,-24(s0)
+80000d24:	fd042783          	lw	a5,-48(s0)
+80000d28:	00f737b3          	sltu	a5,a4,a5
+80000d2c:	0ff7f793          	andi	a5,a5,255
+80000d30:	fcf42423          	sw	a5,-56(s0)
+80000d34:	fc842783          	lw	a5,-56(s0)
+80000d38:	0017b793          	seqz	a5,a5
+80000d3c:	fcf403a3          	sb	a5,-57(s0)
+80000d40:	fc744783          	lbu	a5,-57(s0)
+80000d44:	00078f13          	mv	t5,a5
+80000d48:	800017b7          	lui	a5,0x80001
+80000d4c:	db078f93          	addi	t6,a5,-592 # 80000db0 <main_sp+0xfeffb3f4>
+80000d50:	000f206b          	0xf206b
+80000d54:	01ff707b          	0x1ff707b
+80000d58:	fcc42783          	lw	a5,-52(s0)
+80000d5c:	00279793          	slli	a5,a5,0x2
+80000d60:	fdc42703          	lw	a4,-36(s0)
+80000d64:	00f707b3          	add	a5,a4,a5
+80000d68:	0007a683          	lw	a3,0(a5)
+80000d6c:	fcc42783          	lw	a5,-52(s0)
+80000d70:	00279793          	slli	a5,a5,0x2
+80000d74:	fd842703          	lw	a4,-40(s0)
+80000d78:	00f707b3          	add	a5,a4,a5
+80000d7c:	0007a703          	lw	a4,0(a5)
+80000d80:	fcc42783          	lw	a5,-52(s0)
+80000d84:	00279793          	slli	a5,a5,0x2
+80000d88:	fd442603          	lw	a2,-44(s0)
+80000d8c:	00f607b3          	add	a5,a2,a5
+80000d90:	00e68733          	add	a4,a3,a4
+80000d94:	00e7a023          	sw	a4,0(a5)
+80000d98:	fe842783          	lw	a5,-24(s0)
+80000d9c:	00178793          	addi	a5,a5,1
+80000da0:	fef42423          	sw	a5,-24(s0)
+80000da4:	800017b7          	lui	a5,0x80001
+80000da8:	db478e13          	addi	t3,a5,-588 # 80000db4 <main_sp+0xfeffb3f8>
+80000dac:	000e0067          	jr	t3
+80000db0:	00000013          	nop
+80000db4:	0000306b          	0x306b
+80000db8:	fe442783          	lw	a5,-28(s0)
+80000dbc:	00178793          	addi	a5,a5,1
+80000dc0:	fef42223          	sw	a5,-28(s0)
+80000dc4:	fe442783          	lw	a5,-28(s0)
+80000dc8:	fec42703          	lw	a4,-20(s0)
+80000dcc:	f2e7eee3          	bltu	a5,a4,80000d08 <_vx_mat_add+0x8c>
+80000dd0:	00000013          	nop
+80000dd4:	04c12083          	lw	ra,76(sp)
+80000dd8:	04812403          	lw	s0,72(sp)
+80000ddc:	05010113          	addi	sp,sp,80
+80000de0:	00008067          	ret
 
-80000e18 <vx_mat_sub>:
-80000e18:	fc010113          	addi	sp,sp,-64
-80000e1c:	02112e23          	sw	ra,60(sp)
-80000e20:	02812c23          	sw	s0,56(sp)
-80000e24:	04010413          	addi	s0,sp,64
-80000e28:	fca42e23          	sw	a0,-36(s0)
-80000e2c:	fcb42c23          	sw	a1,-40(s0)
-80000e30:	fcc42a23          	sw	a2,-44(s0)
-80000e34:	fcd42823          	sw	a3,-48(s0)
-80000e38:	fce42623          	sw	a4,-52(s0)
-80000e3c:	810037b7          	lui	a5,0x81003
-80000e40:	fdc42703          	lw	a4,-36(s0)
-80000e44:	9ae7ac23          	sw	a4,-1608(a5) # 810029b8 <main_sp+0xffffcfb4>
-80000e48:	810037b7          	lui	a5,0x81003
-80000e4c:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000e50:	fd842703          	lw	a4,-40(s0)
-80000e54:	00e7a223          	sw	a4,4(a5)
-80000e58:	810037b7          	lui	a5,0x81003
-80000e5c:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000e60:	fd442703          	lw	a4,-44(s0)
-80000e64:	00e7a423          	sw	a4,8(a5)
-80000e68:	810037b7          	lui	a5,0x81003
-80000e6c:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000e70:	fcc42703          	lw	a4,-52(s0)
-80000e74:	00e7a623          	sw	a4,12(a5)
-80000e78:	810037b7          	lui	a5,0x81003
-80000e7c:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000e80:	fd042703          	lw	a4,-48(s0)
-80000e84:	00e7a823          	sw	a4,16(a5)
-80000e88:	b24ff0ef          	jal	ra,800001ac <vx_available_threads>
-80000e8c:	fea42423          	sw	a0,-24(s0)
-80000e90:	fcc42703          	lw	a4,-52(s0)
-80000e94:	fe842783          	lw	a5,-24(s0)
-80000e98:	02f757b3          	divu	a5,a4,a5
-80000e9c:	fef42623          	sw	a5,-20(s0)
-80000ea0:	fcc42703          	lw	a4,-52(s0)
-80000ea4:	fe842783          	lw	a5,-24(s0)
-80000ea8:	02f777b3          	remu	a5,a4,a5
-80000eac:	00078863          	beqz	a5,80000ebc <vx_mat_sub+0xa4>
-80000eb0:	fec42783          	lw	a5,-20(s0)
-80000eb4:	00178793          	addi	a5,a5,1
-80000eb8:	fef42623          	sw	a5,-20(s0)
-80000ebc:	810037b7          	lui	a5,0x81003
-80000ec0:	9b878793          	addi	a5,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000ec4:	fec42703          	lw	a4,-20(s0)
-80000ec8:	00e7aa23          	sw	a4,20(a5)
-80000ecc:	fcc42703          	lw	a4,-52(s0)
-80000ed0:	fe842783          	lw	a5,-24(s0)
-80000ed4:	02f76263          	bltu	a4,a5,80000ef8 <vx_mat_sub+0xe0>
-80000ed8:	810037b7          	lui	a5,0x81003
-80000edc:	9b878693          	addi	a3,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000ee0:	800017b7          	lui	a5,0x80001
-80000ee4:	f5078613          	addi	a2,a5,-176 # 80000f50 <main_sp+0xfeffb54c>
-80000ee8:	fe842583          	lw	a1,-24(s0)
-80000eec:	fd042503          	lw	a0,-48(s0)
-80000ef0:	d1cff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000ef4:	0200006f          	j	80000f14 <vx_mat_sub+0xfc>
-80000ef8:	810037b7          	lui	a5,0x81003
-80000efc:	9b878693          	addi	a3,a5,-1608 # 810029b8 <main_sp+0xffffcfb4>
-80000f00:	800017b7          	lui	a5,0x80001
-80000f04:	f5078613          	addi	a2,a5,-176 # 80000f50 <main_sp+0xfeffb54c>
-80000f08:	fcc42583          	lw	a1,-52(s0)
-80000f0c:	fd042503          	lw	a0,-48(s0)
-80000f10:	cfcff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80000f14:	a90ff0ef          	jal	ra,800001a4 <vx_available_warps>
-80000f18:	fea42223          	sw	a0,-28(s0)
-80000f1c:	fd042703          	lw	a4,-48(s0)
-80000f20:	fe442783          	lw	a5,-28(s0)
-80000f24:	00e7f863          	bgeu	a5,a4,80000f34 <vx_mat_sub+0x11c>
-80000f28:	fe442503          	lw	a0,-28(s0)
-80000f2c:	dccff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80000f30:	00c0006f          	j	80000f3c <vx_mat_sub+0x124>
-80000f34:	fd042503          	lw	a0,-48(s0)
-80000f38:	dc0ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80000f3c:	00000013          	nop
-80000f40:	03c12083          	lw	ra,60(sp)
-80000f44:	03812403          	lw	s0,56(sp)
-80000f48:	04010113          	addi	sp,sp,64
-80000f4c:	00008067          	ret
+80000de4 <vx_mat_sub>:
+80000de4:	fc010113          	addi	sp,sp,-64
+80000de8:	02112e23          	sw	ra,60(sp)
+80000dec:	02812c23          	sw	s0,56(sp)
+80000df0:	04010413          	addi	s0,sp,64
+80000df4:	fca42e23          	sw	a0,-36(s0)
+80000df8:	fcb42c23          	sw	a1,-40(s0)
+80000dfc:	fcc42a23          	sw	a2,-44(s0)
+80000e00:	fcd42823          	sw	a3,-48(s0)
+80000e04:	fce42623          	sw	a4,-52(s0)
+80000e08:	810037b7          	lui	a5,0x81003
+80000e0c:	fdc42703          	lw	a4,-36(s0)
+80000e10:	96e7a823          	sw	a4,-1680(a5) # 81002970 <main_sp+0xffffcfb4>
+80000e14:	810037b7          	lui	a5,0x81003
+80000e18:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000e1c:	fd842703          	lw	a4,-40(s0)
+80000e20:	00e7a223          	sw	a4,4(a5)
+80000e24:	810037b7          	lui	a5,0x81003
+80000e28:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000e2c:	fd442703          	lw	a4,-44(s0)
+80000e30:	00e7a423          	sw	a4,8(a5)
+80000e34:	810037b7          	lui	a5,0x81003
+80000e38:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000e3c:	fcc42703          	lw	a4,-52(s0)
+80000e40:	00e7a623          	sw	a4,12(a5)
+80000e44:	810037b7          	lui	a5,0x81003
+80000e48:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000e4c:	fd042703          	lw	a4,-48(s0)
+80000e50:	00e7a823          	sw	a4,16(a5)
+80000e54:	b70ff0ef          	jal	ra,800001c4 <vx_available_threads>
+80000e58:	fea42423          	sw	a0,-24(s0)
+80000e5c:	fcc42703          	lw	a4,-52(s0)
+80000e60:	fe842783          	lw	a5,-24(s0)
+80000e64:	02f757b3          	divu	a5,a4,a5
+80000e68:	fef42623          	sw	a5,-20(s0)
+80000e6c:	fcc42703          	lw	a4,-52(s0)
+80000e70:	fe842783          	lw	a5,-24(s0)
+80000e74:	02f777b3          	remu	a5,a4,a5
+80000e78:	00078863          	beqz	a5,80000e88 <vx_mat_sub+0xa4>
+80000e7c:	fec42783          	lw	a5,-20(s0)
+80000e80:	00178793          	addi	a5,a5,1
+80000e84:	fef42623          	sw	a5,-20(s0)
+80000e88:	810037b7          	lui	a5,0x81003
+80000e8c:	97078793          	addi	a5,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000e90:	fec42703          	lw	a4,-20(s0)
+80000e94:	00e7aa23          	sw	a4,20(a5)
+80000e98:	fcc42703          	lw	a4,-52(s0)
+80000e9c:	fe842783          	lw	a5,-24(s0)
+80000ea0:	02f76263          	bltu	a4,a5,80000ec4 <vx_mat_sub+0xe0>
+80000ea4:	810037b7          	lui	a5,0x81003
+80000ea8:	97078693          	addi	a3,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000eac:	800017b7          	lui	a5,0x80001
+80000eb0:	f1c78613          	addi	a2,a5,-228 # 80000f1c <main_sp+0xfeffb560>
+80000eb4:	fe842583          	lw	a1,-24(s0)
+80000eb8:	fd042503          	lw	a0,-48(s0)
+80000ebc:	d68ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000ec0:	0200006f          	j	80000ee0 <vx_mat_sub+0xfc>
+80000ec4:	810037b7          	lui	a5,0x81003
+80000ec8:	97078693          	addi	a3,a5,-1680 # 81002970 <main_sp+0xffffcfb4>
+80000ecc:	800017b7          	lui	a5,0x80001
+80000ed0:	f1c78613          	addi	a2,a5,-228 # 80000f1c <main_sp+0xfeffb560>
+80000ed4:	fcc42583          	lw	a1,-52(s0)
+80000ed8:	fd042503          	lw	a0,-48(s0)
+80000edc:	d48ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80000ee0:	adcff0ef          	jal	ra,800001bc <vx_available_warps>
+80000ee4:	fea42223          	sw	a0,-28(s0)
+80000ee8:	fd042703          	lw	a4,-48(s0)
+80000eec:	fe442783          	lw	a5,-28(s0)
+80000ef0:	00e7f863          	bgeu	a5,a4,80000f00 <vx_mat_sub+0x11c>
+80000ef4:	fe442503          	lw	a0,-28(s0)
+80000ef8:	e18ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+80000efc:	00c0006f          	j	80000f08 <vx_mat_sub+0x124>
+80000f00:	fd042503          	lw	a0,-48(s0)
+80000f04:	e0cff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+80000f08:	00000013          	nop
+80000f0c:	03c12083          	lw	ra,60(sp)
+80000f10:	03812403          	lw	s0,56(sp)
+80000f14:	04010113          	addi	sp,sp,64
+80000f18:	00008067          	ret
 
-80000f50 <_vx_mat_sub>:
-80000f50:	fb010113          	addi	sp,sp,-80
-80000f54:	04112623          	sw	ra,76(sp)
-80000f58:	04812423          	sw	s0,72(sp)
-80000f5c:	05010413          	addi	s0,sp,80
-80000f60:	faa42e23          	sw	a0,-68(s0)
-80000f64:	fab42c23          	sw	a1,-72(s0)
-80000f68:	e5cff0ef          	jal	ra,800005c4 <vx_get_arg_struct>
-80000f6c:	fea42023          	sw	a0,-32(s0)
-80000f70:	fe042783          	lw	a5,-32(s0)
-80000f74:	0007a783          	lw	a5,0(a5)
-80000f78:	fcf42e23          	sw	a5,-36(s0)
-80000f7c:	fe042783          	lw	a5,-32(s0)
-80000f80:	0047a783          	lw	a5,4(a5)
-80000f84:	fcf42c23          	sw	a5,-40(s0)
-80000f88:	fe042783          	lw	a5,-32(s0)
-80000f8c:	0087a783          	lw	a5,8(a5)
-80000f90:	fcf42a23          	sw	a5,-44(s0)
+80000f1c <_vx_mat_sub>:
+80000f1c:	fb010113          	addi	sp,sp,-80
+80000f20:	04112623          	sw	ra,76(sp)
+80000f24:	04812423          	sw	s0,72(sp)
+80000f28:	05010413          	addi	s0,sp,80
+80000f2c:	faa42e23          	sw	a0,-68(s0)
+80000f30:	fab42c23          	sw	a1,-72(s0)
+80000f34:	ea8ff0ef          	jal	ra,800005dc <vx_get_arg_struct>
+80000f38:	fea42023          	sw	a0,-32(s0)
+80000f3c:	fe042783          	lw	a5,-32(s0)
+80000f40:	0007a783          	lw	a5,0(a5)
+80000f44:	fcf42e23          	sw	a5,-36(s0)
+80000f48:	fe042783          	lw	a5,-32(s0)
+80000f4c:	0047a783          	lw	a5,4(a5)
+80000f50:	fcf42c23          	sw	a5,-40(s0)
+80000f54:	fe042783          	lw	a5,-32(s0)
+80000f58:	0087a783          	lw	a5,8(a5)
+80000f5c:	fcf42a23          	sw	a5,-44(s0)
+80000f60:	fe042783          	lw	a5,-32(s0)
+80000f64:	0147a783          	lw	a5,20(a5)
+80000f68:	fef42623          	sw	a5,-20(s0)
+80000f6c:	fec42703          	lw	a4,-20(s0)
+80000f70:	fbc42783          	lw	a5,-68(s0)
+80000f74:	02f707b3          	mul	a5,a4,a5
+80000f78:	fef42423          	sw	a5,-24(s0)
+80000f7c:	fec42783          	lw	a5,-20(s0)
+80000f80:	00079a63          	bnez	a5,80000f94 <_vx_mat_sub+0x78>
+80000f84:	00100793          	li	a5,1
+80000f88:	fef42623          	sw	a5,-20(s0)
+80000f8c:	fbc42783          	lw	a5,-68(s0)
+80000f90:	fef42423          	sw	a5,-24(s0)
 80000f94:	fe042783          	lw	a5,-32(s0)
-80000f98:	0147a783          	lw	a5,20(a5)
-80000f9c:	fef42623          	sw	a5,-20(s0)
-80000fa0:	fec42703          	lw	a4,-20(s0)
-80000fa4:	fbc42783          	lw	a5,-68(s0)
-80000fa8:	02f707b3          	mul	a5,a4,a5
-80000fac:	fef42423          	sw	a5,-24(s0)
-80000fb0:	fec42783          	lw	a5,-20(s0)
-80000fb4:	00079a63          	bnez	a5,80000fc8 <_vx_mat_sub+0x78>
-80000fb8:	00100793          	li	a5,1
-80000fbc:	fef42623          	sw	a5,-20(s0)
-80000fc0:	fbc42783          	lw	a5,-68(s0)
-80000fc4:	fef42423          	sw	a5,-24(s0)
-80000fc8:	fe042783          	lw	a5,-32(s0)
-80000fcc:	00c7a783          	lw	a5,12(a5)
-80000fd0:	fcf42823          	sw	a5,-48(s0)
-80000fd4:	fe042223          	sw	zero,-28(s0)
-80000fd8:	0c00006f          	j	80001098 <_vx_mat_sub+0x148>
-80000fdc:	fb842703          	lw	a4,-72(s0)
-80000fe0:	fd042783          	lw	a5,-48(s0)
-80000fe4:	02f70733          	mul	a4,a4,a5
-80000fe8:	fe842783          	lw	a5,-24(s0)
-80000fec:	00f707b3          	add	a5,a4,a5
-80000ff0:	fcf42623          	sw	a5,-52(s0)
-80000ff4:	fe842703          	lw	a4,-24(s0)
-80000ff8:	fd042783          	lw	a5,-48(s0)
-80000ffc:	00f737b3          	sltu	a5,a4,a5
-80001000:	0ff7f793          	andi	a5,a5,255
-80001004:	fcf42423          	sw	a5,-56(s0)
-80001008:	fc842783          	lw	a5,-56(s0)
-8000100c:	0017b793          	seqz	a5,a5
-80001010:	fcf403a3          	sb	a5,-57(s0)
-80001014:	fc744783          	lbu	a5,-57(s0)
-80001018:	00078f13          	mv	t5,a5
-8000101c:	800017b7          	lui	a5,0x80001
-80001020:	08478f93          	addi	t6,a5,132 # 80001084 <main_sp+0xfeffb680>
-80001024:	000f206b          	0xf206b
-80001028:	01ff707b          	0x1ff707b
-8000102c:	fcc42783          	lw	a5,-52(s0)
-80001030:	00279793          	slli	a5,a5,0x2
-80001034:	fdc42703          	lw	a4,-36(s0)
-80001038:	00f707b3          	add	a5,a4,a5
-8000103c:	0007a683          	lw	a3,0(a5)
-80001040:	fcc42783          	lw	a5,-52(s0)
-80001044:	00279793          	slli	a5,a5,0x2
-80001048:	fd842703          	lw	a4,-40(s0)
-8000104c:	00f707b3          	add	a5,a4,a5
-80001050:	0007a703          	lw	a4,0(a5)
-80001054:	fcc42783          	lw	a5,-52(s0)
-80001058:	00279793          	slli	a5,a5,0x2
-8000105c:	fd442603          	lw	a2,-44(s0)
-80001060:	00f607b3          	add	a5,a2,a5
-80001064:	40e68733          	sub	a4,a3,a4
-80001068:	00e7a023          	sw	a4,0(a5)
-8000106c:	fe842783          	lw	a5,-24(s0)
-80001070:	00178793          	addi	a5,a5,1
-80001074:	fef42423          	sw	a5,-24(s0)
-80001078:	800017b7          	lui	a5,0x80001
-8000107c:	08878e13          	addi	t3,a5,136 # 80001088 <main_sp+0xfeffb684>
-80001080:	000e0067          	jr	t3
-80001084:	00000013          	nop
-80001088:	0000306b          	0x306b
-8000108c:	fe442783          	lw	a5,-28(s0)
-80001090:	00178793          	addi	a5,a5,1
-80001094:	fef42223          	sw	a5,-28(s0)
-80001098:	fe442783          	lw	a5,-28(s0)
-8000109c:	fec42703          	lw	a4,-20(s0)
-800010a0:	f2e7eee3          	bltu	a5,a4,80000fdc <_vx_mat_sub+0x8c>
-800010a4:	00000013          	nop
-800010a8:	04c12083          	lw	ra,76(sp)
-800010ac:	04812403          	lw	s0,72(sp)
-800010b0:	05010113          	addi	sp,sp,80
-800010b4:	00008067          	ret
+80000f98:	00c7a783          	lw	a5,12(a5)
+80000f9c:	fcf42823          	sw	a5,-48(s0)
+80000fa0:	fe042223          	sw	zero,-28(s0)
+80000fa4:	0c00006f          	j	80001064 <_vx_mat_sub+0x148>
+80000fa8:	fb842703          	lw	a4,-72(s0)
+80000fac:	fd042783          	lw	a5,-48(s0)
+80000fb0:	02f70733          	mul	a4,a4,a5
+80000fb4:	fe842783          	lw	a5,-24(s0)
+80000fb8:	00f707b3          	add	a5,a4,a5
+80000fbc:	fcf42623          	sw	a5,-52(s0)
+80000fc0:	fe842703          	lw	a4,-24(s0)
+80000fc4:	fd042783          	lw	a5,-48(s0)
+80000fc8:	00f737b3          	sltu	a5,a4,a5
+80000fcc:	0ff7f793          	andi	a5,a5,255
+80000fd0:	fcf42423          	sw	a5,-56(s0)
+80000fd4:	fc842783          	lw	a5,-56(s0)
+80000fd8:	0017b793          	seqz	a5,a5
+80000fdc:	fcf403a3          	sb	a5,-57(s0)
+80000fe0:	fc744783          	lbu	a5,-57(s0)
+80000fe4:	00078f13          	mv	t5,a5
+80000fe8:	800017b7          	lui	a5,0x80001
+80000fec:	05078f93          	addi	t6,a5,80 # 80001050 <main_sp+0xfeffb694>
+80000ff0:	000f206b          	0xf206b
+80000ff4:	01ff707b          	0x1ff707b
+80000ff8:	fcc42783          	lw	a5,-52(s0)
+80000ffc:	00279793          	slli	a5,a5,0x2
+80001000:	fdc42703          	lw	a4,-36(s0)
+80001004:	00f707b3          	add	a5,a4,a5
+80001008:	0007a683          	lw	a3,0(a5)
+8000100c:	fcc42783          	lw	a5,-52(s0)
+80001010:	00279793          	slli	a5,a5,0x2
+80001014:	fd842703          	lw	a4,-40(s0)
+80001018:	00f707b3          	add	a5,a4,a5
+8000101c:	0007a703          	lw	a4,0(a5)
+80001020:	fcc42783          	lw	a5,-52(s0)
+80001024:	00279793          	slli	a5,a5,0x2
+80001028:	fd442603          	lw	a2,-44(s0)
+8000102c:	00f607b3          	add	a5,a2,a5
+80001030:	40e68733          	sub	a4,a3,a4
+80001034:	00e7a023          	sw	a4,0(a5)
+80001038:	fe842783          	lw	a5,-24(s0)
+8000103c:	00178793          	addi	a5,a5,1
+80001040:	fef42423          	sw	a5,-24(s0)
+80001044:	800017b7          	lui	a5,0x80001
+80001048:	05478e13          	addi	t3,a5,84 # 80001054 <main_sp+0xfeffb698>
+8000104c:	000e0067          	jr	t3
+80001050:	00000013          	nop
+80001054:	0000306b          	0x306b
+80001058:	fe442783          	lw	a5,-28(s0)
+8000105c:	00178793          	addi	a5,a5,1
+80001060:	fef42223          	sw	a5,-28(s0)
+80001064:	fe442783          	lw	a5,-28(s0)
+80001068:	fec42703          	lw	a4,-20(s0)
+8000106c:	f2e7eee3          	bltu	a5,a4,80000fa8 <_vx_mat_sub+0x8c>
+80001070:	00000013          	nop
+80001074:	04c12083          	lw	ra,76(sp)
+80001078:	04812403          	lw	s0,72(sp)
+8000107c:	05010113          	addi	sp,sp,80
+80001080:	00008067          	ret
 
-800010b8 <vx_e_mat_add>:
-800010b8:	fc010113          	addi	sp,sp,-64
-800010bc:	02112e23          	sw	ra,60(sp)
-800010c0:	02812c23          	sw	s0,56(sp)
-800010c4:	04010413          	addi	s0,sp,64
-800010c8:	fca42e23          	sw	a0,-36(s0)
-800010cc:	fcb42c23          	sw	a1,-40(s0)
-800010d0:	fcc42a23          	sw	a2,-44(s0)
-800010d4:	fcd42823          	sw	a3,-48(s0)
-800010d8:	fce42623          	sw	a4,-52(s0)
-800010dc:	810037b7          	lui	a5,0x81003
-800010e0:	fdc42703          	lw	a4,-36(s0)
-800010e4:	9ce7a823          	sw	a4,-1584(a5) # 810029d0 <main_sp+0xffffcfcc>
-800010e8:	810037b7          	lui	a5,0x81003
-800010ec:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-800010f0:	fd842703          	lw	a4,-40(s0)
-800010f4:	00e7a223          	sw	a4,4(a5)
-800010f8:	810037b7          	lui	a5,0x81003
-800010fc:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001100:	fd442703          	lw	a4,-44(s0)
-80001104:	00e7a423          	sw	a4,8(a5)
-80001108:	810037b7          	lui	a5,0x81003
-8000110c:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001110:	fcc42703          	lw	a4,-52(s0)
-80001114:	00e7a623          	sw	a4,12(a5)
-80001118:	810037b7          	lui	a5,0x81003
-8000111c:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001120:	fd042703          	lw	a4,-48(s0)
-80001124:	00e7a823          	sw	a4,16(a5)
-80001128:	884ff0ef          	jal	ra,800001ac <vx_available_threads>
-8000112c:	fea42423          	sw	a0,-24(s0)
-80001130:	fcc42703          	lw	a4,-52(s0)
-80001134:	fe842783          	lw	a5,-24(s0)
-80001138:	02f757b3          	divu	a5,a4,a5
-8000113c:	fef42623          	sw	a5,-20(s0)
-80001140:	fcc42703          	lw	a4,-52(s0)
-80001144:	fe842783          	lw	a5,-24(s0)
-80001148:	02f777b3          	remu	a5,a4,a5
-8000114c:	00078863          	beqz	a5,8000115c <vx_e_mat_add+0xa4>
-80001150:	fec42783          	lw	a5,-20(s0)
-80001154:	00178793          	addi	a5,a5,1
-80001158:	fef42623          	sw	a5,-20(s0)
-8000115c:	810037b7          	lui	a5,0x81003
-80001160:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001164:	fec42703          	lw	a4,-20(s0)
-80001168:	00e7aa23          	sw	a4,20(a5)
-8000116c:	fcc42703          	lw	a4,-52(s0)
-80001170:	fe842783          	lw	a5,-24(s0)
-80001174:	02f76263          	bltu	a4,a5,80001198 <vx_e_mat_add+0xe0>
-80001178:	810037b7          	lui	a5,0x81003
-8000117c:	9d078693          	addi	a3,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001180:	800017b7          	lui	a5,0x80001
-80001184:	1f078613          	addi	a2,a5,496 # 800011f0 <main_sp+0xfeffb7ec>
-80001188:	fe842583          	lw	a1,-24(s0)
-8000118c:	fd042503          	lw	a0,-48(s0)
-80001190:	a7cff0ef          	jal	ra,8000040c <vx_spawnWarps>
-80001194:	0200006f          	j	800011b4 <vx_e_mat_add+0xfc>
-80001198:	810037b7          	lui	a5,0x81003
-8000119c:	9d078693          	addi	a3,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-800011a0:	800017b7          	lui	a5,0x80001
-800011a4:	1f078613          	addi	a2,a5,496 # 800011f0 <main_sp+0xfeffb7ec>
-800011a8:	fcc42583          	lw	a1,-52(s0)
-800011ac:	fd042503          	lw	a0,-48(s0)
-800011b0:	a5cff0ef          	jal	ra,8000040c <vx_spawnWarps>
-800011b4:	ff1fe0ef          	jal	ra,800001a4 <vx_available_warps>
-800011b8:	fea42223          	sw	a0,-28(s0)
-800011bc:	fd042703          	lw	a4,-48(s0)
-800011c0:	fe442783          	lw	a5,-28(s0)
-800011c4:	00e7f863          	bgeu	a5,a4,800011d4 <vx_e_mat_add+0x11c>
-800011c8:	fe442503          	lw	a0,-28(s0)
-800011cc:	b2cff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-800011d0:	00c0006f          	j	800011dc <vx_e_mat_add+0x124>
-800011d4:	fd042503          	lw	a0,-48(s0)
-800011d8:	b20ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-800011dc:	00000013          	nop
-800011e0:	03c12083          	lw	ra,60(sp)
-800011e4:	03812403          	lw	s0,56(sp)
-800011e8:	04010113          	addi	sp,sp,64
-800011ec:	00008067          	ret
+80001084 <vx_e_mat_add>:
+80001084:	fc010113          	addi	sp,sp,-64
+80001088:	02112e23          	sw	ra,60(sp)
+8000108c:	02812c23          	sw	s0,56(sp)
+80001090:	04010413          	addi	s0,sp,64
+80001094:	fca42e23          	sw	a0,-36(s0)
+80001098:	fcb42c23          	sw	a1,-40(s0)
+8000109c:	fcc42a23          	sw	a2,-44(s0)
+800010a0:	fcd42823          	sw	a3,-48(s0)
+800010a4:	fce42623          	sw	a4,-52(s0)
+800010a8:	810037b7          	lui	a5,0x81003
+800010ac:	fdc42703          	lw	a4,-36(s0)
+800010b0:	98e7a423          	sw	a4,-1656(a5) # 81002988 <main_sp+0xffffcfcc>
+800010b4:	810037b7          	lui	a5,0x81003
+800010b8:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800010bc:	fd842703          	lw	a4,-40(s0)
+800010c0:	00e7a223          	sw	a4,4(a5)
+800010c4:	810037b7          	lui	a5,0x81003
+800010c8:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800010cc:	fd442703          	lw	a4,-44(s0)
+800010d0:	00e7a423          	sw	a4,8(a5)
+800010d4:	810037b7          	lui	a5,0x81003
+800010d8:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800010dc:	fcc42703          	lw	a4,-52(s0)
+800010e0:	00e7a623          	sw	a4,12(a5)
+800010e4:	810037b7          	lui	a5,0x81003
+800010e8:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800010ec:	fd042703          	lw	a4,-48(s0)
+800010f0:	00e7a823          	sw	a4,16(a5)
+800010f4:	8d0ff0ef          	jal	ra,800001c4 <vx_available_threads>
+800010f8:	fea42423          	sw	a0,-24(s0)
+800010fc:	fcc42703          	lw	a4,-52(s0)
+80001100:	fe842783          	lw	a5,-24(s0)
+80001104:	02f757b3          	divu	a5,a4,a5
+80001108:	fef42623          	sw	a5,-20(s0)
+8000110c:	fcc42703          	lw	a4,-52(s0)
+80001110:	fe842783          	lw	a5,-24(s0)
+80001114:	02f777b3          	remu	a5,a4,a5
+80001118:	00078863          	beqz	a5,80001128 <vx_e_mat_add+0xa4>
+8000111c:	fec42783          	lw	a5,-20(s0)
+80001120:	00178793          	addi	a5,a5,1
+80001124:	fef42623          	sw	a5,-20(s0)
+80001128:	810037b7          	lui	a5,0x81003
+8000112c:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001130:	fec42703          	lw	a4,-20(s0)
+80001134:	00e7aa23          	sw	a4,20(a5)
+80001138:	fcc42703          	lw	a4,-52(s0)
+8000113c:	fe842783          	lw	a5,-24(s0)
+80001140:	02f76263          	bltu	a4,a5,80001164 <vx_e_mat_add+0xe0>
+80001144:	810037b7          	lui	a5,0x81003
+80001148:	98878693          	addi	a3,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+8000114c:	800017b7          	lui	a5,0x80001
+80001150:	1bc78613          	addi	a2,a5,444 # 800011bc <main_sp+0xfeffb800>
+80001154:	fe842583          	lw	a1,-24(s0)
+80001158:	fd042503          	lw	a0,-48(s0)
+8000115c:	ac8ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80001160:	0200006f          	j	80001180 <vx_e_mat_add+0xfc>
+80001164:	810037b7          	lui	a5,0x81003
+80001168:	98878693          	addi	a3,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+8000116c:	800017b7          	lui	a5,0x80001
+80001170:	1bc78613          	addi	a2,a5,444 # 800011bc <main_sp+0xfeffb800>
+80001174:	fcc42583          	lw	a1,-52(s0)
+80001178:	fd042503          	lw	a0,-48(s0)
+8000117c:	aa8ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80001180:	83cff0ef          	jal	ra,800001bc <vx_available_warps>
+80001184:	fea42223          	sw	a0,-28(s0)
+80001188:	fd042703          	lw	a4,-48(s0)
+8000118c:	fe442783          	lw	a5,-28(s0)
+80001190:	00e7f863          	bgeu	a5,a4,800011a0 <vx_e_mat_add+0x11c>
+80001194:	fe442503          	lw	a0,-28(s0)
+80001198:	b78ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+8000119c:	00c0006f          	j	800011a8 <vx_e_mat_add+0x124>
+800011a0:	fd042503          	lw	a0,-48(s0)
+800011a4:	b6cff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+800011a8:	00000013          	nop
+800011ac:	03c12083          	lw	ra,60(sp)
+800011b0:	03812403          	lw	s0,56(sp)
+800011b4:	04010113          	addi	sp,sp,64
+800011b8:	00008067          	ret
 
-800011f0 <_vx_e_mat_add>:
-800011f0:	fb010113          	addi	sp,sp,-80
-800011f4:	04112623          	sw	ra,76(sp)
-800011f8:	04812423          	sw	s0,72(sp)
-800011fc:	05010413          	addi	s0,sp,80
-80001200:	faa42e23          	sw	a0,-68(s0)
-80001204:	fab42c23          	sw	a1,-72(s0)
-80001208:	bbcff0ef          	jal	ra,800005c4 <vx_get_arg_struct>
-8000120c:	fea42023          	sw	a0,-32(s0)
-80001210:	fe042783          	lw	a5,-32(s0)
-80001214:	0007a783          	lw	a5,0(a5)
-80001218:	fcf42e23          	sw	a5,-36(s0)
-8000121c:	fe042783          	lw	a5,-32(s0)
-80001220:	0047a783          	lw	a5,4(a5)
-80001224:	0007a783          	lw	a5,0(a5)
-80001228:	fcf42c23          	sw	a5,-40(s0)
-8000122c:	fe042783          	lw	a5,-32(s0)
-80001230:	0087a783          	lw	a5,8(a5)
-80001234:	fcf42a23          	sw	a5,-44(s0)
+800011bc <_vx_e_mat_add>:
+800011bc:	fb010113          	addi	sp,sp,-80
+800011c0:	04112623          	sw	ra,76(sp)
+800011c4:	04812423          	sw	s0,72(sp)
+800011c8:	05010413          	addi	s0,sp,80
+800011cc:	faa42e23          	sw	a0,-68(s0)
+800011d0:	fab42c23          	sw	a1,-72(s0)
+800011d4:	c08ff0ef          	jal	ra,800005dc <vx_get_arg_struct>
+800011d8:	fea42023          	sw	a0,-32(s0)
+800011dc:	fe042783          	lw	a5,-32(s0)
+800011e0:	0007a783          	lw	a5,0(a5)
+800011e4:	fcf42e23          	sw	a5,-36(s0)
+800011e8:	fe042783          	lw	a5,-32(s0)
+800011ec:	0047a783          	lw	a5,4(a5)
+800011f0:	0007a783          	lw	a5,0(a5)
+800011f4:	fcf42c23          	sw	a5,-40(s0)
+800011f8:	fe042783          	lw	a5,-32(s0)
+800011fc:	0087a783          	lw	a5,8(a5)
+80001200:	fcf42a23          	sw	a5,-44(s0)
+80001204:	fe042783          	lw	a5,-32(s0)
+80001208:	0147a783          	lw	a5,20(a5)
+8000120c:	fef42623          	sw	a5,-20(s0)
+80001210:	fec42703          	lw	a4,-20(s0)
+80001214:	fbc42783          	lw	a5,-68(s0)
+80001218:	02f707b3          	mul	a5,a4,a5
+8000121c:	fef42423          	sw	a5,-24(s0)
+80001220:	fec42783          	lw	a5,-20(s0)
+80001224:	00079a63          	bnez	a5,80001238 <_vx_e_mat_add+0x7c>
+80001228:	00100793          	li	a5,1
+8000122c:	fef42623          	sw	a5,-20(s0)
+80001230:	fbc42783          	lw	a5,-68(s0)
+80001234:	fef42423          	sw	a5,-24(s0)
 80001238:	fe042783          	lw	a5,-32(s0)
-8000123c:	0147a783          	lw	a5,20(a5)
-80001240:	fef42623          	sw	a5,-20(s0)
-80001244:	fec42703          	lw	a4,-20(s0)
-80001248:	fbc42783          	lw	a5,-68(s0)
-8000124c:	02f707b3          	mul	a5,a4,a5
-80001250:	fef42423          	sw	a5,-24(s0)
-80001254:	fec42783          	lw	a5,-20(s0)
-80001258:	00079a63          	bnez	a5,8000126c <_vx_e_mat_add+0x7c>
-8000125c:	00100793          	li	a5,1
-80001260:	fef42623          	sw	a5,-20(s0)
-80001264:	fbc42783          	lw	a5,-68(s0)
-80001268:	fef42423          	sw	a5,-24(s0)
-8000126c:	fe042783          	lw	a5,-32(s0)
-80001270:	00c7a783          	lw	a5,12(a5)
-80001274:	fcf42823          	sw	a5,-48(s0)
-80001278:	fe042223          	sw	zero,-28(s0)
-8000127c:	0b00006f          	j	8000132c <_vx_e_mat_add+0x13c>
-80001280:	fb842703          	lw	a4,-72(s0)
-80001284:	fd042783          	lw	a5,-48(s0)
-80001288:	02f70733          	mul	a4,a4,a5
-8000128c:	fe842783          	lw	a5,-24(s0)
-80001290:	00f707b3          	add	a5,a4,a5
-80001294:	fcf42623          	sw	a5,-52(s0)
-80001298:	fe842703          	lw	a4,-24(s0)
-8000129c:	fd042783          	lw	a5,-48(s0)
-800012a0:	00f737b3          	sltu	a5,a4,a5
-800012a4:	0ff7f793          	andi	a5,a5,255
-800012a8:	fcf42423          	sw	a5,-56(s0)
-800012ac:	fc842783          	lw	a5,-56(s0)
-800012b0:	0017b793          	seqz	a5,a5
-800012b4:	fcf403a3          	sb	a5,-57(s0)
-800012b8:	fc744783          	lbu	a5,-57(s0)
-800012bc:	00078f13          	mv	t5,a5
-800012c0:	800017b7          	lui	a5,0x80001
-800012c4:	31878f93          	addi	t6,a5,792 # 80001318 <main_sp+0xfeffb914>
-800012c8:	000f206b          	0xf206b
-800012cc:	01ff707b          	0x1ff707b
-800012d0:	fcc42783          	lw	a5,-52(s0)
-800012d4:	00279793          	slli	a5,a5,0x2
-800012d8:	fdc42703          	lw	a4,-36(s0)
-800012dc:	00f707b3          	add	a5,a4,a5
-800012e0:	0007a683          	lw	a3,0(a5)
-800012e4:	fcc42783          	lw	a5,-52(s0)
-800012e8:	00279793          	slli	a5,a5,0x2
-800012ec:	fd442703          	lw	a4,-44(s0)
-800012f0:	00f707b3          	add	a5,a4,a5
-800012f4:	fd842703          	lw	a4,-40(s0)
-800012f8:	00e68733          	add	a4,a3,a4
-800012fc:	00e7a023          	sw	a4,0(a5)
-80001300:	fe842783          	lw	a5,-24(s0)
-80001304:	00178793          	addi	a5,a5,1
-80001308:	fef42423          	sw	a5,-24(s0)
-8000130c:	800017b7          	lui	a5,0x80001
-80001310:	31c78e13          	addi	t3,a5,796 # 8000131c <main_sp+0xfeffb918>
-80001314:	000e0067          	jr	t3
-80001318:	00000013          	nop
-8000131c:	0000306b          	0x306b
-80001320:	fe442783          	lw	a5,-28(s0)
-80001324:	00178793          	addi	a5,a5,1
-80001328:	fef42223          	sw	a5,-28(s0)
-8000132c:	fe442783          	lw	a5,-28(s0)
-80001330:	fec42703          	lw	a4,-20(s0)
-80001334:	f4e7e6e3          	bltu	a5,a4,80001280 <_vx_e_mat_add+0x90>
-80001338:	00000013          	nop
-8000133c:	04c12083          	lw	ra,76(sp)
-80001340:	04812403          	lw	s0,72(sp)
-80001344:	05010113          	addi	sp,sp,80
-80001348:	00008067          	ret
+8000123c:	00c7a783          	lw	a5,12(a5)
+80001240:	fcf42823          	sw	a5,-48(s0)
+80001244:	fe042223          	sw	zero,-28(s0)
+80001248:	0b00006f          	j	800012f8 <_vx_e_mat_add+0x13c>
+8000124c:	fb842703          	lw	a4,-72(s0)
+80001250:	fd042783          	lw	a5,-48(s0)
+80001254:	02f70733          	mul	a4,a4,a5
+80001258:	fe842783          	lw	a5,-24(s0)
+8000125c:	00f707b3          	add	a5,a4,a5
+80001260:	fcf42623          	sw	a5,-52(s0)
+80001264:	fe842703          	lw	a4,-24(s0)
+80001268:	fd042783          	lw	a5,-48(s0)
+8000126c:	00f737b3          	sltu	a5,a4,a5
+80001270:	0ff7f793          	andi	a5,a5,255
+80001274:	fcf42423          	sw	a5,-56(s0)
+80001278:	fc842783          	lw	a5,-56(s0)
+8000127c:	0017b793          	seqz	a5,a5
+80001280:	fcf403a3          	sb	a5,-57(s0)
+80001284:	fc744783          	lbu	a5,-57(s0)
+80001288:	00078f13          	mv	t5,a5
+8000128c:	800017b7          	lui	a5,0x80001
+80001290:	2e478f93          	addi	t6,a5,740 # 800012e4 <main_sp+0xfeffb928>
+80001294:	000f206b          	0xf206b
+80001298:	01ff707b          	0x1ff707b
+8000129c:	fcc42783          	lw	a5,-52(s0)
+800012a0:	00279793          	slli	a5,a5,0x2
+800012a4:	fdc42703          	lw	a4,-36(s0)
+800012a8:	00f707b3          	add	a5,a4,a5
+800012ac:	0007a683          	lw	a3,0(a5)
+800012b0:	fcc42783          	lw	a5,-52(s0)
+800012b4:	00279793          	slli	a5,a5,0x2
+800012b8:	fd442703          	lw	a4,-44(s0)
+800012bc:	00f707b3          	add	a5,a4,a5
+800012c0:	fd842703          	lw	a4,-40(s0)
+800012c4:	00e68733          	add	a4,a3,a4
+800012c8:	00e7a023          	sw	a4,0(a5)
+800012cc:	fe842783          	lw	a5,-24(s0)
+800012d0:	00178793          	addi	a5,a5,1
+800012d4:	fef42423          	sw	a5,-24(s0)
+800012d8:	800017b7          	lui	a5,0x80001
+800012dc:	2e878e13          	addi	t3,a5,744 # 800012e8 <main_sp+0xfeffb92c>
+800012e0:	000e0067          	jr	t3
+800012e4:	00000013          	nop
+800012e8:	0000306b          	0x306b
+800012ec:	fe442783          	lw	a5,-28(s0)
+800012f0:	00178793          	addi	a5,a5,1
+800012f4:	fef42223          	sw	a5,-28(s0)
+800012f8:	fe442783          	lw	a5,-28(s0)
+800012fc:	fec42703          	lw	a4,-20(s0)
+80001300:	f4e7e6e3          	bltu	a5,a4,8000124c <_vx_e_mat_add+0x90>
+80001304:	00000013          	nop
+80001308:	04c12083          	lw	ra,76(sp)
+8000130c:	04812403          	lw	s0,72(sp)
+80001310:	05010113          	addi	sp,sp,80
+80001314:	00008067          	ret
 
-8000134c <vx_e_mat_mult>:
-8000134c:	fc010113          	addi	sp,sp,-64
-80001350:	02112e23          	sw	ra,60(sp)
-80001354:	02812c23          	sw	s0,56(sp)
-80001358:	04010413          	addi	s0,sp,64
-8000135c:	fca42e23          	sw	a0,-36(s0)
-80001360:	fcb42c23          	sw	a1,-40(s0)
-80001364:	fcc42a23          	sw	a2,-44(s0)
-80001368:	fcd42823          	sw	a3,-48(s0)
-8000136c:	fce42623          	sw	a4,-52(s0)
-80001370:	810037b7          	lui	a5,0x81003
-80001374:	fdc42703          	lw	a4,-36(s0)
-80001378:	9ce7a823          	sw	a4,-1584(a5) # 810029d0 <main_sp+0xffffcfcc>
-8000137c:	810037b7          	lui	a5,0x81003
-80001380:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001384:	fd842703          	lw	a4,-40(s0)
-80001388:	00e7a223          	sw	a4,4(a5)
-8000138c:	810037b7          	lui	a5,0x81003
-80001390:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001394:	fd442703          	lw	a4,-44(s0)
-80001398:	00e7a423          	sw	a4,8(a5)
-8000139c:	810037b7          	lui	a5,0x81003
-800013a0:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-800013a4:	fcc42703          	lw	a4,-52(s0)
-800013a8:	00e7a623          	sw	a4,12(a5)
-800013ac:	810037b7          	lui	a5,0x81003
-800013b0:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-800013b4:	fd042703          	lw	a4,-48(s0)
-800013b8:	00e7a823          	sw	a4,16(a5)
-800013bc:	df1fe0ef          	jal	ra,800001ac <vx_available_threads>
-800013c0:	fea42423          	sw	a0,-24(s0)
-800013c4:	fcc42703          	lw	a4,-52(s0)
-800013c8:	fe842783          	lw	a5,-24(s0)
-800013cc:	02f757b3          	divu	a5,a4,a5
-800013d0:	fef42623          	sw	a5,-20(s0)
-800013d4:	fcc42703          	lw	a4,-52(s0)
-800013d8:	fe842783          	lw	a5,-24(s0)
-800013dc:	02f777b3          	remu	a5,a4,a5
-800013e0:	00078863          	beqz	a5,800013f0 <vx_e_mat_mult+0xa4>
-800013e4:	fec42783          	lw	a5,-20(s0)
-800013e8:	00178793          	addi	a5,a5,1
-800013ec:	fef42623          	sw	a5,-20(s0)
-800013f0:	810037b7          	lui	a5,0x81003
-800013f4:	9d078793          	addi	a5,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-800013f8:	fec42703          	lw	a4,-20(s0)
-800013fc:	00e7aa23          	sw	a4,20(a5)
-80001400:	fcc42703          	lw	a4,-52(s0)
-80001404:	fe842783          	lw	a5,-24(s0)
-80001408:	02f76263          	bltu	a4,a5,8000142c <vx_e_mat_mult+0xe0>
-8000140c:	810037b7          	lui	a5,0x81003
-80001410:	9d078693          	addi	a3,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001414:	800017b7          	lui	a5,0x80001
-80001418:	48478613          	addi	a2,a5,1156 # 80001484 <main_sp+0xfeffba80>
-8000141c:	fe842583          	lw	a1,-24(s0)
-80001420:	fd042503          	lw	a0,-48(s0)
-80001424:	fe9fe0ef          	jal	ra,8000040c <vx_spawnWarps>
-80001428:	0200006f          	j	80001448 <vx_e_mat_mult+0xfc>
-8000142c:	810037b7          	lui	a5,0x81003
-80001430:	9d078693          	addi	a3,a5,-1584 # 810029d0 <main_sp+0xffffcfcc>
-80001434:	800017b7          	lui	a5,0x80001
-80001438:	48478613          	addi	a2,a5,1156 # 80001484 <main_sp+0xfeffba80>
-8000143c:	fcc42583          	lw	a1,-52(s0)
-80001440:	fd042503          	lw	a0,-48(s0)
-80001444:	fc9fe0ef          	jal	ra,8000040c <vx_spawnWarps>
-80001448:	d5dfe0ef          	jal	ra,800001a4 <vx_available_warps>
-8000144c:	fea42223          	sw	a0,-28(s0)
-80001450:	fd042703          	lw	a4,-48(s0)
-80001454:	fe442783          	lw	a5,-28(s0)
-80001458:	00e7f863          	bgeu	a5,a4,80001468 <vx_e_mat_mult+0x11c>
-8000145c:	fe442503          	lw	a0,-28(s0)
-80001460:	898ff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80001464:	00c0006f          	j	80001470 <vx_e_mat_mult+0x124>
-80001468:	fd042503          	lw	a0,-48(s0)
-8000146c:	88cff0ef          	jal	ra,800004f8 <vx_wait_for_warps>
-80001470:	00000013          	nop
-80001474:	03c12083          	lw	ra,60(sp)
-80001478:	03812403          	lw	s0,56(sp)
-8000147c:	04010113          	addi	sp,sp,64
-80001480:	00008067          	ret
+80001318 <vx_e_mat_mult>:
+80001318:	fc010113          	addi	sp,sp,-64
+8000131c:	02112e23          	sw	ra,60(sp)
+80001320:	02812c23          	sw	s0,56(sp)
+80001324:	04010413          	addi	s0,sp,64
+80001328:	fca42e23          	sw	a0,-36(s0)
+8000132c:	fcb42c23          	sw	a1,-40(s0)
+80001330:	fcc42a23          	sw	a2,-44(s0)
+80001334:	fcd42823          	sw	a3,-48(s0)
+80001338:	fce42623          	sw	a4,-52(s0)
+8000133c:	810037b7          	lui	a5,0x81003
+80001340:	fdc42703          	lw	a4,-36(s0)
+80001344:	98e7a423          	sw	a4,-1656(a5) # 81002988 <main_sp+0xffffcfcc>
+80001348:	810037b7          	lui	a5,0x81003
+8000134c:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001350:	fd842703          	lw	a4,-40(s0)
+80001354:	00e7a223          	sw	a4,4(a5)
+80001358:	810037b7          	lui	a5,0x81003
+8000135c:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001360:	fd442703          	lw	a4,-44(s0)
+80001364:	00e7a423          	sw	a4,8(a5)
+80001368:	810037b7          	lui	a5,0x81003
+8000136c:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001370:	fcc42703          	lw	a4,-52(s0)
+80001374:	00e7a623          	sw	a4,12(a5)
+80001378:	810037b7          	lui	a5,0x81003
+8000137c:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001380:	fd042703          	lw	a4,-48(s0)
+80001384:	00e7a823          	sw	a4,16(a5)
+80001388:	e3dfe0ef          	jal	ra,800001c4 <vx_available_threads>
+8000138c:	fea42423          	sw	a0,-24(s0)
+80001390:	fcc42703          	lw	a4,-52(s0)
+80001394:	fe842783          	lw	a5,-24(s0)
+80001398:	02f757b3          	divu	a5,a4,a5
+8000139c:	fef42623          	sw	a5,-20(s0)
+800013a0:	fcc42703          	lw	a4,-52(s0)
+800013a4:	fe842783          	lw	a5,-24(s0)
+800013a8:	02f777b3          	remu	a5,a4,a5
+800013ac:	00078863          	beqz	a5,800013bc <vx_e_mat_mult+0xa4>
+800013b0:	fec42783          	lw	a5,-20(s0)
+800013b4:	00178793          	addi	a5,a5,1
+800013b8:	fef42623          	sw	a5,-20(s0)
+800013bc:	810037b7          	lui	a5,0x81003
+800013c0:	98878793          	addi	a5,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800013c4:	fec42703          	lw	a4,-20(s0)
+800013c8:	00e7aa23          	sw	a4,20(a5)
+800013cc:	fcc42703          	lw	a4,-52(s0)
+800013d0:	fe842783          	lw	a5,-24(s0)
+800013d4:	02f76263          	bltu	a4,a5,800013f8 <vx_e_mat_mult+0xe0>
+800013d8:	810037b7          	lui	a5,0x81003
+800013dc:	98878693          	addi	a3,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+800013e0:	800017b7          	lui	a5,0x80001
+800013e4:	45078613          	addi	a2,a5,1104 # 80001450 <main_sp+0xfeffba94>
+800013e8:	fe842583          	lw	a1,-24(s0)
+800013ec:	fd042503          	lw	a0,-48(s0)
+800013f0:	834ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+800013f4:	0200006f          	j	80001414 <vx_e_mat_mult+0xfc>
+800013f8:	810037b7          	lui	a5,0x81003
+800013fc:	98878693          	addi	a3,a5,-1656 # 81002988 <main_sp+0xffffcfcc>
+80001400:	800017b7          	lui	a5,0x80001
+80001404:	45078613          	addi	a2,a5,1104 # 80001450 <main_sp+0xfeffba94>
+80001408:	fcc42583          	lw	a1,-52(s0)
+8000140c:	fd042503          	lw	a0,-48(s0)
+80001410:	814ff0ef          	jal	ra,80000424 <vx_spawnWarps>
+80001414:	da9fe0ef          	jal	ra,800001bc <vx_available_warps>
+80001418:	fea42223          	sw	a0,-28(s0)
+8000141c:	fd042703          	lw	a4,-48(s0)
+80001420:	fe442783          	lw	a5,-28(s0)
+80001424:	00e7f863          	bgeu	a5,a4,80001434 <vx_e_mat_mult+0x11c>
+80001428:	fe442503          	lw	a0,-28(s0)
+8000142c:	8e4ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+80001430:	00c0006f          	j	8000143c <vx_e_mat_mult+0x124>
+80001434:	fd042503          	lw	a0,-48(s0)
+80001438:	8d8ff0ef          	jal	ra,80000510 <vx_wait_for_warps>
+8000143c:	00000013          	nop
+80001440:	03c12083          	lw	ra,60(sp)
+80001444:	03812403          	lw	s0,56(sp)
+80001448:	04010113          	addi	sp,sp,64
+8000144c:	00008067          	ret
 
-80001484 <_vx_e_mat_mult>:
-80001484:	fb010113          	addi	sp,sp,-80
-80001488:	04112623          	sw	ra,76(sp)
-8000148c:	04812423          	sw	s0,72(sp)
-80001490:	05010413          	addi	s0,sp,80
-80001494:	faa42e23          	sw	a0,-68(s0)
-80001498:	fab42c23          	sw	a1,-72(s0)
-8000149c:	928ff0ef          	jal	ra,800005c4 <vx_get_arg_struct>
-800014a0:	fea42023          	sw	a0,-32(s0)
-800014a4:	fe042783          	lw	a5,-32(s0)
-800014a8:	0007a783          	lw	a5,0(a5)
-800014ac:	fcf42e23          	sw	a5,-36(s0)
-800014b0:	fe042783          	lw	a5,-32(s0)
-800014b4:	0047a783          	lw	a5,4(a5)
-800014b8:	0007a783          	lw	a5,0(a5)
-800014bc:	fcf42c23          	sw	a5,-40(s0)
-800014c0:	fe042783          	lw	a5,-32(s0)
-800014c4:	0087a783          	lw	a5,8(a5)
-800014c8:	fcf42a23          	sw	a5,-44(s0)
+80001450 <_vx_e_mat_mult>:
+80001450:	fb010113          	addi	sp,sp,-80
+80001454:	04112623          	sw	ra,76(sp)
+80001458:	04812423          	sw	s0,72(sp)
+8000145c:	05010413          	addi	s0,sp,80
+80001460:	faa42e23          	sw	a0,-68(s0)
+80001464:	fab42c23          	sw	a1,-72(s0)
+80001468:	974ff0ef          	jal	ra,800005dc <vx_get_arg_struct>
+8000146c:	fea42023          	sw	a0,-32(s0)
+80001470:	fe042783          	lw	a5,-32(s0)
+80001474:	0007a783          	lw	a5,0(a5)
+80001478:	fcf42e23          	sw	a5,-36(s0)
+8000147c:	fe042783          	lw	a5,-32(s0)
+80001480:	0047a783          	lw	a5,4(a5)
+80001484:	0007a783          	lw	a5,0(a5)
+80001488:	fcf42c23          	sw	a5,-40(s0)
+8000148c:	fe042783          	lw	a5,-32(s0)
+80001490:	0087a783          	lw	a5,8(a5)
+80001494:	fcf42a23          	sw	a5,-44(s0)
+80001498:	fe042783          	lw	a5,-32(s0)
+8000149c:	0147a783          	lw	a5,20(a5)
+800014a0:	fef42623          	sw	a5,-20(s0)
+800014a4:	fec42703          	lw	a4,-20(s0)
+800014a8:	fbc42783          	lw	a5,-68(s0)
+800014ac:	02f707b3          	mul	a5,a4,a5
+800014b0:	fef42423          	sw	a5,-24(s0)
+800014b4:	fec42783          	lw	a5,-20(s0)
+800014b8:	00079a63          	bnez	a5,800014cc <_vx_e_mat_mult+0x7c>
+800014bc:	00100793          	li	a5,1
+800014c0:	fef42623          	sw	a5,-20(s0)
+800014c4:	fbc42783          	lw	a5,-68(s0)
+800014c8:	fef42423          	sw	a5,-24(s0)
 800014cc:	fe042783          	lw	a5,-32(s0)
-800014d0:	0147a783          	lw	a5,20(a5)
-800014d4:	fef42623          	sw	a5,-20(s0)
-800014d8:	fec42703          	lw	a4,-20(s0)
-800014dc:	fbc42783          	lw	a5,-68(s0)
-800014e0:	02f707b3          	mul	a5,a4,a5
-800014e4:	fef42423          	sw	a5,-24(s0)
-800014e8:	fec42783          	lw	a5,-20(s0)
-800014ec:	00079a63          	bnez	a5,80001500 <_vx_e_mat_mult+0x7c>
-800014f0:	00100793          	li	a5,1
-800014f4:	fef42623          	sw	a5,-20(s0)
-800014f8:	fbc42783          	lw	a5,-68(s0)
-800014fc:	fef42423          	sw	a5,-24(s0)
-80001500:	fe042783          	lw	a5,-32(s0)
-80001504:	00c7a783          	lw	a5,12(a5)
-80001508:	fcf42823          	sw	a5,-48(s0)
-8000150c:	fe042223          	sw	zero,-28(s0)
-80001510:	0b00006f          	j	800015c0 <_vx_e_mat_mult+0x13c>
-80001514:	fb842703          	lw	a4,-72(s0)
-80001518:	fd042783          	lw	a5,-48(s0)
-8000151c:	02f70733          	mul	a4,a4,a5
-80001520:	fe842783          	lw	a5,-24(s0)
-80001524:	00f707b3          	add	a5,a4,a5
-80001528:	fcf42623          	sw	a5,-52(s0)
-8000152c:	fe842703          	lw	a4,-24(s0)
-80001530:	fd042783          	lw	a5,-48(s0)
-80001534:	00f737b3          	sltu	a5,a4,a5
-80001538:	0ff7f793          	andi	a5,a5,255
-8000153c:	fcf42423          	sw	a5,-56(s0)
-80001540:	fc842783          	lw	a5,-56(s0)
-80001544:	0017b793          	seqz	a5,a5
-80001548:	fcf403a3          	sb	a5,-57(s0)
-8000154c:	fc744783          	lbu	a5,-57(s0)
-80001550:	00078f13          	mv	t5,a5
-80001554:	800017b7          	lui	a5,0x80001
-80001558:	5ac78f93          	addi	t6,a5,1452 # 800015ac <main_sp+0xfeffbba8>
-8000155c:	000f206b          	0xf206b
-80001560:	01ff707b          	0x1ff707b
-80001564:	fcc42783          	lw	a5,-52(s0)
-80001568:	00279793          	slli	a5,a5,0x2
-8000156c:	fdc42703          	lw	a4,-36(s0)
-80001570:	00f707b3          	add	a5,a4,a5
-80001574:	0007a683          	lw	a3,0(a5)
-80001578:	fcc42783          	lw	a5,-52(s0)
-8000157c:	00279793          	slli	a5,a5,0x2
-80001580:	fd442703          	lw	a4,-44(s0)
-80001584:	00f707b3          	add	a5,a4,a5
-80001588:	fd842703          	lw	a4,-40(s0)
-8000158c:	02e68733          	mul	a4,a3,a4
-80001590:	00e7a023          	sw	a4,0(a5)
-80001594:	fe842783          	lw	a5,-24(s0)
-80001598:	00178793          	addi	a5,a5,1
-8000159c:	fef42423          	sw	a5,-24(s0)
-800015a0:	800017b7          	lui	a5,0x80001
-800015a4:	5b078e13          	addi	t3,a5,1456 # 800015b0 <main_sp+0xfeffbbac>
-800015a8:	000e0067          	jr	t3
-800015ac:	00000013          	nop
-800015b0:	0000306b          	0x306b
-800015b4:	fe442783          	lw	a5,-28(s0)
-800015b8:	00178793          	addi	a5,a5,1
-800015bc:	fef42223          	sw	a5,-28(s0)
-800015c0:	fe442783          	lw	a5,-28(s0)
+800014d0:	00c7a783          	lw	a5,12(a5)
+800014d4:	fcf42823          	sw	a5,-48(s0)
+800014d8:	fe042223          	sw	zero,-28(s0)
+800014dc:	0b00006f          	j	8000158c <_vx_e_mat_mult+0x13c>
+800014e0:	fb842703          	lw	a4,-72(s0)
+800014e4:	fd042783          	lw	a5,-48(s0)
+800014e8:	02f70733          	mul	a4,a4,a5
+800014ec:	fe842783          	lw	a5,-24(s0)
+800014f0:	00f707b3          	add	a5,a4,a5
+800014f4:	fcf42623          	sw	a5,-52(s0)
+800014f8:	fe842703          	lw	a4,-24(s0)
+800014fc:	fd042783          	lw	a5,-48(s0)
+80001500:	00f737b3          	sltu	a5,a4,a5
+80001504:	0ff7f793          	andi	a5,a5,255
+80001508:	fcf42423          	sw	a5,-56(s0)
+8000150c:	fc842783          	lw	a5,-56(s0)
+80001510:	0017b793          	seqz	a5,a5
+80001514:	fcf403a3          	sb	a5,-57(s0)
+80001518:	fc744783          	lbu	a5,-57(s0)
+8000151c:	00078f13          	mv	t5,a5
+80001520:	800017b7          	lui	a5,0x80001
+80001524:	57878f93          	addi	t6,a5,1400 # 80001578 <main_sp+0xfeffbbbc>
+80001528:	000f206b          	0xf206b
+8000152c:	01ff707b          	0x1ff707b
+80001530:	fcc42783          	lw	a5,-52(s0)
+80001534:	00279793          	slli	a5,a5,0x2
+80001538:	fdc42703          	lw	a4,-36(s0)
+8000153c:	00f707b3          	add	a5,a4,a5
+80001540:	0007a683          	lw	a3,0(a5)
+80001544:	fcc42783          	lw	a5,-52(s0)
+80001548:	00279793          	slli	a5,a5,0x2
+8000154c:	fd442703          	lw	a4,-44(s0)
+80001550:	00f707b3          	add	a5,a4,a5
+80001554:	fd842703          	lw	a4,-40(s0)
+80001558:	02e68733          	mul	a4,a3,a4
+8000155c:	00e7a023          	sw	a4,0(a5)
+80001560:	fe842783          	lw	a5,-24(s0)
+80001564:	00178793          	addi	a5,a5,1
+80001568:	fef42423          	sw	a5,-24(s0)
+8000156c:	800017b7          	lui	a5,0x80001
+80001570:	57c78e13          	addi	t3,a5,1404 # 8000157c <main_sp+0xfeffbbc0>
+80001574:	000e0067          	jr	t3
+80001578:	00000013          	nop
+8000157c:	0000306b          	0x306b
+80001580:	fe442783          	lw	a5,-28(s0)
+80001584:	00178793          	addi	a5,a5,1
+80001588:	fef42223          	sw	a5,-28(s0)
+8000158c:	fe442783          	lw	a5,-28(s0)
+80001590:	fec42703          	lw	a4,-20(s0)
+80001594:	f4e7e6e3          	bltu	a5,a4,800014e0 <_vx_e_mat_mult+0x90>
+80001598:	00000013          	nop
+8000159c:	04c12083          	lw	ra,76(sp)
+800015a0:	04812403          	lw	s0,72(sp)
+800015a4:	05010113          	addi	sp,sp,80
+800015a8:	00008067          	ret
+
+800015ac <initialize_mats>:
+800015ac:	fe010113          	addi	sp,sp,-32
+800015b0:	00812e23          	sw	s0,28(sp)
+800015b4:	02010413          	addi	s0,sp,32
+800015b8:	fe042623          	sw	zero,-20(s0)
+800015bc:	0480006f          	j	80001604 <initialize_mats+0x58>
+800015c0:	810037b7          	lui	a5,0x81003
 800015c4:	fec42703          	lw	a4,-20(s0)
-800015c8:	f4e7e6e3          	bltu	a5,a4,80001514 <_vx_e_mat_mult+0x90>
-800015cc:	00000013          	nop
-800015d0:	04c12083          	lw	ra,76(sp)
-800015d4:	04812403          	lw	s0,72(sp)
-800015d8:	05010113          	addi	sp,sp,80
-800015dc:	00008067          	ret
+800015c8:	00271713          	slli	a4,a4,0x2
+800015cc:	9a078793          	addi	a5,a5,-1632 # 810029a0 <main_sp+0xffffcfe4>
+800015d0:	00f707b3          	add	a5,a4,a5
+800015d4:	00300713          	li	a4,3
+800015d8:	00e7a023          	sw	a4,0(a5)
+800015dc:	810047b7          	lui	a5,0x81004
+800015e0:	fec42703          	lw	a4,-20(s0)
+800015e4:	00271713          	slli	a4,a4,0x2
+800015e8:	9a078793          	addi	a5,a5,-1632 # 810039a0 <main_sp+0xffffdfe4>
+800015ec:	00f707b3          	add	a5,a4,a5
+800015f0:	00200713          	li	a4,2
+800015f4:	00e7a023          	sw	a4,0(a5)
+800015f8:	fec42783          	lw	a5,-20(s0)
+800015fc:	00178793          	addi	a5,a5,1
+80001600:	fef42623          	sw	a5,-20(s0)
+80001604:	fec42703          	lw	a4,-20(s0)
+80001608:	0ff00793          	li	a5,255
+8000160c:	fae7dae3          	bge	a5,a4,800015c0 <initialize_mats+0x14>
+80001610:	00000013          	nop
+80001614:	01c12403          	lw	s0,28(sp)
+80001618:	02010113          	addi	sp,sp,32
+8000161c:	00008067          	ret
 
-800015e0 <initialize_mats>:
-800015e0:	fe010113          	addi	sp,sp,-32
-800015e4:	00812e23          	sw	s0,28(sp)
-800015e8:	02010413          	addi	s0,sp,32
-800015ec:	fe042623          	sw	zero,-20(s0)
-800015f0:	0480006f          	j	80001638 <initialize_mats+0x58>
-800015f4:	810037b7          	lui	a5,0x81003
-800015f8:	fec42703          	lw	a4,-20(s0)
-800015fc:	00271713          	slli	a4,a4,0x2
-80001600:	9e878793          	addi	a5,a5,-1560 # 810029e8 <main_sp+0xffffcfe4>
-80001604:	00f707b3          	add	a5,a4,a5
-80001608:	00300713          	li	a4,3
-8000160c:	00e7a023          	sw	a4,0(a5)
-80001610:	810047b7          	lui	a5,0x81004
-80001614:	fec42703          	lw	a4,-20(s0)
-80001618:	00271713          	slli	a4,a4,0x2
-8000161c:	9e878793          	addi	a5,a5,-1560 # 810039e8 <main_sp+0xffffdfe4>
-80001620:	00f707b3          	add	a5,a4,a5
-80001624:	00200713          	li	a4,2
-80001628:	00e7a023          	sw	a4,0(a5)
-8000162c:	fec42783          	lw	a5,-20(s0)
-80001630:	00178793          	addi	a5,a5,1
-80001634:	fef42623          	sw	a5,-20(s0)
-80001638:	fec42703          	lw	a4,-20(s0)
-8000163c:	03f00793          	li	a5,63
-80001640:	fae7dae3          	bge	a5,a4,800015f4 <initialize_mats+0x14>
-80001644:	00000013          	nop
-80001648:	01c12403          	lw	s0,28(sp)
-8000164c:	02010113          	addi	sp,sp,32
-80001650:	00008067          	ret
+80001620 <print_matrix>:
+80001620:	fd010113          	addi	sp,sp,-48
+80001624:	02112623          	sw	ra,44(sp)
+80001628:	02812423          	sw	s0,40(sp)
+8000162c:	03010413          	addi	s0,sp,48
+80001630:	fca42e23          	sw	a0,-36(s0)
+80001634:	810007b7          	lui	a5,0x81000
+80001638:	11078513          	addi	a0,a5,272 # 81000110 <main_sp+0xffffa754>
+8000163c:	90cff0ef          	jal	ra,80000748 <vx_print_str>
+80001640:	fe042623          	sw	zero,-20(s0)
+80001644:	0580006f          	j	8000169c <print_matrix+0x7c>
+80001648:	fec42783          	lw	a5,-20(s0)
+8000164c:	00078e63          	beqz	a5,80001668 <print_matrix+0x48>
+80001650:	fec42783          	lw	a5,-20(s0)
+80001654:	00f7f793          	andi	a5,a5,15
+80001658:	00079863          	bnez	a5,80001668 <print_matrix+0x48>
+8000165c:	810007b7          	lui	a5,0x81000
+80001660:	13478513          	addi	a0,a5,308 # 81000134 <main_sp+0xffffa778>
+80001664:	8e4ff0ef          	jal	ra,80000748 <vx_print_str>
+80001668:	fec42783          	lw	a5,-20(s0)
+8000166c:	00279793          	slli	a5,a5,0x2
+80001670:	fdc42703          	lw	a4,-36(s0)
+80001674:	00f707b3          	add	a5,a4,a5
+80001678:	0007a783          	lw	a5,0(a5)
+8000167c:	00078513          	mv	a0,a5
+80001680:	904ff0ef          	jal	ra,80000784 <vx_print_hex>
+80001684:	810007b7          	lui	a5,0x81000
+80001688:	13878513          	addi	a0,a5,312 # 81000138 <main_sp+0xffffa77c>
+8000168c:	8bcff0ef          	jal	ra,80000748 <vx_print_str>
+80001690:	fec42783          	lw	a5,-20(s0)
+80001694:	00178793          	addi	a5,a5,1
+80001698:	fef42623          	sw	a5,-20(s0)
+8000169c:	fec42703          	lw	a4,-20(s0)
+800016a0:	0ff00793          	li	a5,255
+800016a4:	fae7d2e3          	bge	a5,a4,80001648 <print_matrix+0x28>
+800016a8:	810007b7          	lui	a5,0x81000
+800016ac:	13c78513          	addi	a0,a5,316 # 8100013c <main_sp+0xffffa780>
+800016b0:	898ff0ef          	jal	ra,80000748 <vx_print_str>
+800016b4:	00000013          	nop
+800016b8:	02c12083          	lw	ra,44(sp)
+800016bc:	02812403          	lw	s0,40(sp)
+800016c0:	03010113          	addi	sp,sp,48
+800016c4:	00008067          	ret
 
-80001654 <print_matrix>:
-80001654:	fd010113          	addi	sp,sp,-48
-80001658:	02112623          	sw	ra,44(sp)
-8000165c:	02812423          	sw	s0,40(sp)
-80001660:	03010413          	addi	s0,sp,48
-80001664:	fca42e23          	sw	a0,-36(s0)
-80001668:	810007b7          	lui	a5,0x81000
-8000166c:	11078513          	addi	a0,a5,272 # 81000110 <main_sp+0xffffa70c>
-80001670:	8c0ff0ef          	jal	ra,80000730 <vx_print_str>
-80001674:	fe042623          	sw	zero,-20(s0)
-80001678:	0580006f          	j	800016d0 <print_matrix+0x7c>
-8000167c:	fec42783          	lw	a5,-20(s0)
-80001680:	00078e63          	beqz	a5,8000169c <print_matrix+0x48>
-80001684:	fec42783          	lw	a5,-20(s0)
-80001688:	0077f793          	andi	a5,a5,7
-8000168c:	00079863          	bnez	a5,8000169c <print_matrix+0x48>
-80001690:	810007b7          	lui	a5,0x81000
-80001694:	13478513          	addi	a0,a5,308 # 81000134 <main_sp+0xffffa730>
-80001698:	898ff0ef          	jal	ra,80000730 <vx_print_str>
-8000169c:	fec42783          	lw	a5,-20(s0)
-800016a0:	00279793          	slli	a5,a5,0x2
-800016a4:	fdc42703          	lw	a4,-36(s0)
-800016a8:	00f707b3          	add	a5,a4,a5
-800016ac:	0007a783          	lw	a5,0(a5)
-800016b0:	00078513          	mv	a0,a5
-800016b4:	8b8ff0ef          	jal	ra,8000076c <vx_print_hex>
-800016b8:	810007b7          	lui	a5,0x81000
-800016bc:	13878513          	addi	a0,a5,312 # 81000138 <main_sp+0xffffa734>
-800016c0:	870ff0ef          	jal	ra,80000730 <vx_print_str>
-800016c4:	fec42783          	lw	a5,-20(s0)
-800016c8:	00178793          	addi	a5,a5,1
-800016cc:	fef42623          	sw	a5,-20(s0)
-800016d0:	fec42703          	lw	a4,-20(s0)
-800016d4:	03f00793          	li	a5,63
-800016d8:	fae7d2e3          	bge	a5,a4,8000167c <print_matrix+0x28>
-800016dc:	810007b7          	lui	a5,0x81000
-800016e0:	13c78513          	addi	a0,a5,316 # 8100013c <main_sp+0xffffa738>
-800016e4:	84cff0ef          	jal	ra,80000730 <vx_print_str>
-800016e8:	00000013          	nop
-800016ec:	02c12083          	lw	ra,44(sp)
-800016f0:	02812403          	lw	s0,40(sp)
-800016f4:	03010113          	addi	sp,sp,48
-800016f8:	00008067          	ret
-
-800016fc <main>:
-800016fc:	fe010113          	addi	sp,sp,-32
-80001700:	00112e23          	sw	ra,28(sp)
-80001704:	00812c23          	sw	s0,24(sp)
-80001708:	02010413          	addi	s0,sp,32
-8000170c:	ed5ff0ef          	jal	ra,800015e0 <initialize_mats>
-80001710:	00800693          	li	a3,8
-80001714:	810057b7          	lui	a5,0x81005
-80001718:	9e878613          	addi	a2,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-8000171c:	810047b7          	lui	a5,0x81004
-80001720:	9e878593          	addi	a1,a5,-1560 # 810039e8 <main_sp+0xffffdfe4>
-80001724:	810037b7          	lui	a5,0x81003
-80001728:	9e878513          	addi	a0,a5,-1560 # 810029e8 <main_sp+0xffffcfe4>
-8000172c:	94cff0ef          	jal	ra,80000878 <vx_sq_mat_mult>
-80001730:	810007b7          	lui	a5,0x81000
-80001734:	16078513          	addi	a0,a5,352 # 81000160 <main_sp+0xffffa75c>
-80001738:	ff9fe0ef          	jal	ra,80000730 <vx_print_str>
-8000173c:	810057b7          	lui	a5,0x81005
-80001740:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001744:	f11ff0ef          	jal	ra,80001654 <print_matrix>
-80001748:	00800713          	li	a4,8
-8000174c:	00800693          	li	a3,8
-80001750:	810057b7          	lui	a5,0x81005
-80001754:	9e878613          	addi	a2,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001758:	810047b7          	lui	a5,0x81004
-8000175c:	9e878593          	addi	a1,a5,-1560 # 810039e8 <main_sp+0xffffdfe4>
-80001760:	810037b7          	lui	a5,0x81003
-80001764:	9e878513          	addi	a0,a5,-1560 # 810029e8 <main_sp+0xffffcfe4>
-80001768:	c10ff0ef          	jal	ra,80000b78 <vx_mat_add>
-8000176c:	810007b7          	lui	a5,0x81000
-80001770:	17c78513          	addi	a0,a5,380 # 8100017c <main_sp+0xffffa778>
-80001774:	fbdfe0ef          	jal	ra,80000730 <vx_print_str>
-80001778:	810057b7          	lui	a5,0x81005
-8000177c:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001780:	ed5ff0ef          	jal	ra,80001654 <print_matrix>
-80001784:	00800713          	li	a4,8
-80001788:	00800693          	li	a3,8
-8000178c:	810057b7          	lui	a5,0x81005
-80001790:	9e878613          	addi	a2,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001794:	810047b7          	lui	a5,0x81004
-80001798:	9e878593          	addi	a1,a5,-1560 # 810039e8 <main_sp+0xffffdfe4>
-8000179c:	810037b7          	lui	a5,0x81003
-800017a0:	9e878513          	addi	a0,a5,-1560 # 810029e8 <main_sp+0xffffcfe4>
-800017a4:	e74ff0ef          	jal	ra,80000e18 <vx_mat_sub>
-800017a8:	810007b7          	lui	a5,0x81000
-800017ac:	19078513          	addi	a0,a5,400 # 81000190 <main_sp+0xffffa78c>
-800017b0:	f81fe0ef          	jal	ra,80000730 <vx_print_str>
-800017b4:	810057b7          	lui	a5,0x81005
-800017b8:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-800017bc:	e99ff0ef          	jal	ra,80001654 <print_matrix>
-800017c0:	00300793          	li	a5,3
-800017c4:	fef42623          	sw	a5,-20(s0)
-800017c8:	fec40593          	addi	a1,s0,-20
-800017cc:	00800713          	li	a4,8
-800017d0:	00800693          	li	a3,8
-800017d4:	810057b7          	lui	a5,0x81005
-800017d8:	9e878613          	addi	a2,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-800017dc:	810057b7          	lui	a5,0x81005
-800017e0:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-800017e4:	8d5ff0ef          	jal	ra,800010b8 <vx_e_mat_add>
-800017e8:	810007b7          	lui	a5,0x81000
-800017ec:	1a878513          	addi	a0,a5,424 # 810001a8 <main_sp+0xffffa7a4>
-800017f0:	f41fe0ef          	jal	ra,80000730 <vx_print_str>
-800017f4:	810057b7          	lui	a5,0x81005
-800017f8:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-800017fc:	e59ff0ef          	jal	ra,80001654 <print_matrix>
-80001800:	fec40593          	addi	a1,s0,-20
-80001804:	00800713          	li	a4,8
-80001808:	00800693          	li	a3,8
-8000180c:	810057b7          	lui	a5,0x81005
-80001810:	9e878613          	addi	a2,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001814:	810057b7          	lui	a5,0x81005
-80001818:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-8000181c:	b31ff0ef          	jal	ra,8000134c <vx_e_mat_mult>
-80001820:	810007b7          	lui	a5,0x81000
-80001824:	1a878513          	addi	a0,a5,424 # 810001a8 <main_sp+0xffffa7a4>
-80001828:	f09fe0ef          	jal	ra,80000730 <vx_print_str>
-8000182c:	810057b7          	lui	a5,0x81005
-80001830:	9e878513          	addi	a0,a5,-1560 # 810049e8 <main_sp+0xffffefe4>
-80001834:	e21ff0ef          	jal	ra,80001654 <print_matrix>
-80001838:	00000793          	li	a5,0
-8000183c:	00078513          	mv	a0,a5
-80001840:	01c12083          	lw	ra,28(sp)
-80001844:	01812403          	lw	s0,24(sp)
-80001848:	02010113          	addi	sp,sp,32
-8000184c:	00008067          	ret
+800016c8 <main>:
+800016c8:	ff010113          	addi	sp,sp,-16
+800016cc:	00112623          	sw	ra,12(sp)
+800016d0:	00812423          	sw	s0,8(sp)
+800016d4:	01010413          	addi	s0,sp,16
+800016d8:	ed5ff0ef          	jal	ra,800015ac <initialize_mats>
+800016dc:	01000693          	li	a3,16
+800016e0:	810057b7          	lui	a5,0x81005
+800016e4:	9a078613          	addi	a2,a5,-1632 # 810049a0 <main_sp+0xffffefe4>
+800016e8:	810047b7          	lui	a5,0x81004
+800016ec:	9a078593          	addi	a1,a5,-1632 # 810039a0 <main_sp+0xffffdfe4>
+800016f0:	810037b7          	lui	a5,0x81003
+800016f4:	9a078513          	addi	a0,a5,-1632 # 810029a0 <main_sp+0xffffcfe4>
+800016f8:	998ff0ef          	jal	ra,80000890 <vx_sq_mat_mult>
+800016fc:	810007b7          	lui	a5,0x81000
+80001700:	16078513          	addi	a0,a5,352 # 81000160 <main_sp+0xffffa7a4>
+80001704:	844ff0ef          	jal	ra,80000748 <vx_print_str>
+80001708:	810057b7          	lui	a5,0x81005
+8000170c:	9a078513          	addi	a0,a5,-1632 # 810049a0 <main_sp+0xffffefe4>
+80001710:	f11ff0ef          	jal	ra,80001620 <print_matrix>
+80001714:	00000793          	li	a5,0
+80001718:	00078513          	mv	a0,a5
+8000171c:	00c12083          	lw	ra,12(sp)
+80001720:	00812403          	lw	s0,8(sp)
+80001724:	01010113          	addi	sp,sp,16
+80001728:	00008067          	ret
 
 Disassembly of section .rodata:
 
@@ -1679,7 +1606,7 @@ Disassembly of section .rodata:
 8100002a:	0000                	unimp
 8100002c:	0062                	c.slli	zero,0x18
 8100002e:	0000                	unimp
-81000030:	00000063          	beqz	zero,81000030 <main+0xffe934>
+81000030:	00000063          	beqz	zero,81000030 <main+0xffe968>
 81000034:	0064                	addi	s1,sp,12
 81000036:	0000                	unimp
 81000038:	0065                	c.nop	25
@@ -1708,7 +1635,7 @@ Disassembly of section .rodata:
 8100006a:	0000                	unimp
 8100006c:	0062                	c.slli	zero,0x18
 8100006e:	0000                	unimp
-81000070:	00000063          	beqz	zero,81000070 <main+0xffe974>
+81000070:	00000063          	beqz	zero,81000070 <main+0xffe9a8>
 81000074:	0064                	addi	s1,sp,12
 81000076:	0000                	unimp
 81000078:	0065                	c.nop	25
@@ -1739,7 +1666,7 @@ Disassembly of section .rodata:
 810000ae:	0000                	unimp
 810000b0:	0062                	c.slli	zero,0x18
 810000b2:	0000                	unimp
-810000b4:	00000063          	beqz	zero,810000b4 <main+0xffe9b8>
+810000b4:	00000063          	beqz	zero,810000b4 <main+0xffe9ec>
 810000b8:	0064                	addi	s1,sp,12
 810000ba:	0000                	unimp
 810000bc:	0065                	c.nop	25
@@ -1773,28 +1700,28 @@ Disassembly of section .rodata:
 810000fa:	0000                	unimp
 810000fc:	0062                	c.slli	zero,0x18
 810000fe:	0000                	unimp
-81000100:	00000063          	beqz	zero,81000100 <main+0xffea04>
+81000100:	00000063          	beqz	zero,81000100 <main+0xffea38>
 81000104:	0064                	addi	s1,sp,12
 81000106:	0000                	unimp
 81000108:	0065                	c.nop	25
 8100010a:	0000                	unimp
 8100010c:	0066                	c.slli	zero,0x19
 8100010e:	0000                	unimp
-81000110:	2d2d                	jal	8100074a <q+0x3e6>
-81000112:	2d2d                	jal	8100074c <q+0x3e8>
-81000114:	2d2d                	jal	8100074e <q+0x3ea>
-81000116:	2d2d                	jal	81000750 <q+0x3ec>
-81000118:	2d2d                	jal	81000752 <q+0x3ee>
-8100011a:	2d2d                	jal	81000754 <q+0x3f0>
-8100011c:	2d2d                	jal	81000756 <q+0x3f2>
-8100011e:	2d2d                	jal	81000758 <q+0x3f4>
-81000120:	2d2d                	jal	8100075a <q+0x3f6>
-81000122:	2d2d                	jal	8100075c <q+0x3f8>
-81000124:	2d2d                	jal	8100075e <q+0x3fa>
-81000126:	2d2d                	jal	81000760 <q+0x3fc>
-81000128:	2d2d                	jal	81000762 <q+0x3fe>
-8100012a:	2d2d                	jal	81000764 <q+0x400>
-8100012c:	2d2d                	jal	81000766 <q+0x402>
+81000110:	2d2d                	jal	8100074a <q+0x42e>
+81000112:	2d2d                	jal	8100074c <q+0x430>
+81000114:	2d2d                	jal	8100074e <q+0x432>
+81000116:	2d2d                	jal	81000750 <q+0x434>
+81000118:	2d2d                	jal	81000752 <q+0x436>
+8100011a:	2d2d                	jal	81000754 <q+0x438>
+8100011c:	2d2d                	jal	81000756 <q+0x43a>
+8100011e:	2d2d                	jal	81000758 <q+0x43c>
+81000120:	2d2d                	jal	8100075a <q+0x43e>
+81000122:	2d2d                	jal	8100075c <q+0x440>
+81000124:	2d2d                	jal	8100075e <q+0x442>
+81000126:	2d2d                	jal	81000760 <q+0x444>
+81000128:	2d2d                	jal	81000762 <q+0x446>
+8100012a:	2d2d                	jal	81000764 <q+0x448>
+8100012c:	2d2d                	jal	81000766 <q+0x44a>
 8100012e:	0a2d                	addi	s4,s4,11
 81000130:	0000                	unimp
 81000132:	0000                	unimp
@@ -1803,21 +1730,21 @@ Disassembly of section .rodata:
 81000138:	0020                	addi	s0,sp,8
 8100013a:	0000                	unimp
 8100013c:	2d0a                	fld	fs10,128(sp)
-8100013e:	2d2d                	jal	81000778 <q+0x414>
-81000140:	2d2d                	jal	8100077a <q+0x416>
-81000142:	2d2d                	jal	8100077c <q+0x418>
-81000144:	2d2d                	jal	8100077e <q+0x41a>
-81000146:	2d2d                	jal	81000780 <q+0x41c>
-81000148:	2d2d                	jal	81000782 <q+0x41e>
-8100014a:	2d2d                	jal	81000784 <q+0x420>
-8100014c:	2d2d                	jal	81000786 <q+0x422>
-8100014e:	2d2d                	jal	81000788 <q+0x424>
-81000150:	2d2d                	jal	8100078a <q+0x426>
-81000152:	2d2d                	jal	8100078c <q+0x428>
-81000154:	2d2d                	jal	8100078e <q+0x42a>
-81000156:	2d2d                	jal	81000790 <q+0x42c>
-81000158:	2d2d                	jal	81000792 <q+0x42e>
-8100015a:	2d2d                	jal	81000794 <q+0x430>
+8100013e:	2d2d                	jal	81000778 <q+0x45c>
+81000140:	2d2d                	jal	8100077a <q+0x45e>
+81000142:	2d2d                	jal	8100077c <q+0x460>
+81000144:	2d2d                	jal	8100077e <q+0x462>
+81000146:	2d2d                	jal	81000780 <q+0x464>
+81000148:	2d2d                	jal	81000782 <q+0x466>
+8100014a:	2d2d                	jal	81000784 <q+0x468>
+8100014c:	2d2d                	jal	81000786 <q+0x46a>
+8100014e:	2d2d                	jal	81000788 <q+0x46c>
+81000150:	2d2d                	jal	8100078a <q+0x46e>
+81000152:	2d2d                	jal	8100078c <q+0x470>
+81000154:	2d2d                	jal	8100078e <q+0x472>
+81000156:	2d2d                	jal	81000790 <q+0x474>
+81000158:	2d2d                	jal	81000792 <q+0x476>
+8100015a:	2d2d                	jal	81000794 <q+0x478>
 8100015c:	000a                	c.slli	zero,0x2
 8100015e:	0000                	unimp
 81000160:	0a0a                	slli	s4,s4,0x2
@@ -1832,227 +1759,191 @@ Disassembly of section .rodata:
 81000172:	7461                	lui	s0,0xffff8
 81000174:	6f69                	lui	t5,0x1a
 81000176:	0a6e                	slli	s4,s4,0x1b
-81000178:	0000                	unimp
-8100017a:	0000                	unimp
-8100017c:	0a0a                	slli	s4,s4,0x2
-8100017e:	614d                	addi	sp,sp,176
-81000180:	7274                	flw	fa3,100(a2)
-81000182:	7869                	lui	a6,0xffffa
-81000184:	4120                	lw	s0,64(a0)
-81000186:	6464                	flw	fs1,76(s0)
-81000188:	7469                	lui	s0,0xffffa
-8100018a:	6f69                	lui	t5,0x1a
-8100018c:	0a6e                	slli	s4,s4,0x1b
-8100018e:	0000                	unimp
-81000190:	0a0a                	slli	s4,s4,0x2
-81000192:	614d                	addi	sp,sp,176
-81000194:	7274                	flw	fa3,100(a2)
-81000196:	7869                	lui	a6,0xffffa
-81000198:	5320                	lw	s0,96(a4)
-8100019a:	6275                	lui	tp,0x1d
-8100019c:	7274                	flw	fa3,100(a2)
-8100019e:	6361                	lui	t1,0x18
-810001a0:	6974                	flw	fa3,84(a0)
-810001a2:	000a6e6f          	jal	t3,810a61a2 <main_sp+0xa079e>
-810001a6:	0000                	unimp
-810001a8:	0a0a                	slli	s4,s4,0x2
-810001aa:	614d                	addi	sp,sp,176
-810001ac:	7274                	flw	fa3,100(a2)
-810001ae:	7869                	lui	a6,0xffffa
-810001b0:	4520                	lw	s0,72(a0)
-810001b2:	656c                	flw	fa1,76(a0)
-810001b4:	656d                	lui	a0,0x1b
-810001b6:	746e                	flw	fs0,248(sp)
-810001b8:	4120                	lw	s0,64(a0)
-810001ba:	6464                	flw	fs1,76(s0)
-810001bc:	7469                	lui	s0,0xffffa
-810001be:	6f69                	lui	t5,0x1a
-810001c0:	0a6e                	slli	s4,s4,0x1b
 	...
 
 Disassembly of section .data:
 
-810001c4 <hextoa>:
-810001c4:	0000                	unimp
+8100017c <hextoa>:
+8100017c:	0000                	unimp
+8100017e:	8100                	0x8100
+81000180:	0004                	0x4
+81000182:	8100                	0x8100
+81000184:	0008                	0x8
+81000186:	8100                	0x8100
+81000188:	000c                	0xc
+8100018a:	8100                	0x8100
+8100018c:	0010                	0x10
+8100018e:	8100                	0x8100
+81000190:	0014                	0x14
+81000192:	8100                	0x8100
+81000194:	0018                	0x18
+81000196:	8100                	0x8100
+81000198:	001c                	0x1c
+8100019a:	8100                	0x8100
+8100019c:	0020                	addi	s0,sp,8
+8100019e:	8100                	0x8100
+810001a0:	0024                	addi	s1,sp,8
+810001a2:	8100                	0x8100
+810001a4:	0028                	addi	a0,sp,8
+810001a6:	8100                	0x8100
+810001a8:	002c                	addi	a1,sp,8
+810001aa:	8100                	0x8100
+810001ac:	0030                	addi	a2,sp,8
+810001ae:	8100                	0x8100
+810001b0:	0034                	addi	a3,sp,8
+810001b2:	8100                	0x8100
+810001b4:	0038                	addi	a4,sp,8
+810001b6:	8100                	0x8100
+810001b8:	003c                	addi	a5,sp,8
+810001ba:	8100                	0x8100
+
+810001bc <hextoa>:
+810001bc:	0040                	addi	s0,sp,4
+810001be:	8100                	0x8100
+810001c0:	0044                	addi	s1,sp,4
+810001c2:	8100                	0x8100
+810001c4:	0048                	addi	a0,sp,4
 810001c6:	8100                	0x8100
-810001c8:	0004                	0x4
+810001c8:	004c                	addi	a1,sp,4
 810001ca:	8100                	0x8100
-810001cc:	0008                	0x8
+810001cc:	0050                	addi	a2,sp,4
 810001ce:	8100                	0x8100
-810001d0:	000c                	0xc
+810001d0:	0054                	addi	a3,sp,4
 810001d2:	8100                	0x8100
-810001d4:	0010                	0x10
+810001d4:	0058                	addi	a4,sp,4
 810001d6:	8100                	0x8100
-810001d8:	0014                	0x14
+810001d8:	005c                	addi	a5,sp,4
 810001da:	8100                	0x8100
-810001dc:	0018                	0x18
+810001dc:	0060                	addi	s0,sp,12
 810001de:	8100                	0x8100
-810001e0:	001c                	0x1c
+810001e0:	0064                	addi	s1,sp,12
 810001e2:	8100                	0x8100
-810001e4:	0020                	addi	s0,sp,8
+810001e4:	0068                	addi	a0,sp,12
 810001e6:	8100                	0x8100
-810001e8:	0024                	addi	s1,sp,8
+810001e8:	006c                	addi	a1,sp,12
 810001ea:	8100                	0x8100
-810001ec:	0028                	addi	a0,sp,8
+810001ec:	0070                	addi	a2,sp,12
 810001ee:	8100                	0x8100
-810001f0:	002c                	addi	a1,sp,8
+810001f0:	0074                	addi	a3,sp,12
 810001f2:	8100                	0x8100
-810001f4:	0030                	addi	a2,sp,8
+810001f4:	0078                	addi	a4,sp,12
 810001f6:	8100                	0x8100
-810001f8:	0034                	addi	a3,sp,8
+810001f8:	007c                	addi	a5,sp,12
 810001fa:	8100                	0x8100
-810001fc:	0038                	addi	a4,sp,8
+
+810001fc <hextoa>:
+810001fc:	0084                	addi	s1,sp,64
 810001fe:	8100                	0x8100
-81000200:	003c                	addi	a5,sp,8
+81000200:	0088                	addi	a0,sp,64
 81000202:	8100                	0x8100
-
-81000204 <hextoa>:
-81000204:	0040                	addi	s0,sp,4
+81000204:	008c                	addi	a1,sp,64
 81000206:	8100                	0x8100
-81000208:	0044                	addi	s1,sp,4
+81000208:	0090                	addi	a2,sp,64
 8100020a:	8100                	0x8100
-8100020c:	0048                	addi	a0,sp,4
+8100020c:	0094                	addi	a3,sp,64
 8100020e:	8100                	0x8100
-81000210:	004c                	addi	a1,sp,4
+81000210:	0098                	addi	a4,sp,64
 81000212:	8100                	0x8100
-81000214:	0050                	addi	a2,sp,4
+81000214:	009c                	addi	a5,sp,64
 81000216:	8100                	0x8100
-81000218:	0054                	addi	a3,sp,4
+81000218:	00a0                	addi	s0,sp,72
 8100021a:	8100                	0x8100
-8100021c:	0058                	addi	a4,sp,4
+8100021c:	00a4                	addi	s1,sp,72
 8100021e:	8100                	0x8100
-81000220:	005c                	addi	a5,sp,4
+81000220:	00a8                	addi	a0,sp,72
 81000222:	8100                	0x8100
-81000224:	0060                	addi	s0,sp,12
+81000224:	00ac                	addi	a1,sp,72
 81000226:	8100                	0x8100
-81000228:	0064                	addi	s1,sp,12
+81000228:	00b0                	addi	a2,sp,72
 8100022a:	8100                	0x8100
-8100022c:	0068                	addi	a0,sp,12
+8100022c:	00b4                	addi	a3,sp,72
 8100022e:	8100                	0x8100
-81000230:	006c                	addi	a1,sp,12
+81000230:	00b8                	addi	a4,sp,72
 81000232:	8100                	0x8100
-81000234:	0070                	addi	a2,sp,12
+81000234:	00bc                	addi	a5,sp,72
 81000236:	8100                	0x8100
-81000238:	0074                	addi	a3,sp,12
+81000238:	00c0                	addi	s0,sp,68
 8100023a:	8100                	0x8100
-8100023c:	0078                	addi	a4,sp,12
+
+8100023c <hextoa>:
+8100023c:	00d0                	addi	a2,sp,68
 8100023e:	8100                	0x8100
-81000240:	007c                	addi	a5,sp,12
+81000240:	00d4                	addi	a3,sp,68
 81000242:	8100                	0x8100
-
-81000244 <hextoa>:
-81000244:	0084                	addi	s1,sp,64
+81000244:	00d8                	addi	a4,sp,68
 81000246:	8100                	0x8100
-81000248:	0088                	addi	a0,sp,64
+81000248:	00dc                	addi	a5,sp,68
 8100024a:	8100                	0x8100
-8100024c:	008c                	addi	a1,sp,64
+8100024c:	00e0                	addi	s0,sp,76
 8100024e:	8100                	0x8100
-81000250:	0090                	addi	a2,sp,64
+81000250:	00e4                	addi	s1,sp,76
 81000252:	8100                	0x8100
-81000254:	0094                	addi	a3,sp,64
+81000254:	00e8                	addi	a0,sp,76
 81000256:	8100                	0x8100
-81000258:	0098                	addi	a4,sp,64
+81000258:	00ec                	addi	a1,sp,76
 8100025a:	8100                	0x8100
-8100025c:	009c                	addi	a5,sp,64
+8100025c:	00f0                	addi	a2,sp,76
 8100025e:	8100                	0x8100
-81000260:	00a0                	addi	s0,sp,72
+81000260:	00f4                	addi	a3,sp,76
 81000262:	8100                	0x8100
-81000264:	00a4                	addi	s1,sp,72
+81000264:	00f8                	addi	a4,sp,76
 81000266:	8100                	0x8100
-81000268:	00a8                	addi	a0,sp,72
+81000268:	00fc                	addi	a5,sp,76
 8100026a:	8100                	0x8100
-8100026c:	00ac                	addi	a1,sp,72
+8100026c:	0100                	addi	s0,sp,128
 8100026e:	8100                	0x8100
-81000270:	00b0                	addi	a2,sp,72
+81000270:	0104                	addi	s1,sp,128
 81000272:	8100                	0x8100
-81000274:	00b4                	addi	a3,sp,72
+81000274:	0108                	addi	a0,sp,128
 81000276:	8100                	0x8100
-81000278:	00b8                	addi	a4,sp,72
+81000278:	010c                	addi	a1,sp,128
 8100027a:	8100                	0x8100
-8100027c:	00bc                	addi	a5,sp,72
-8100027e:	8100                	0x8100
-81000280:	00c0                	addi	s0,sp,68
-81000282:	8100                	0x8100
-
-81000284 <hextoa>:
-81000284:	00d0                	addi	a2,sp,68
-81000286:	8100                	0x8100
-81000288:	00d4                	addi	a3,sp,68
-8100028a:	8100                	0x8100
-8100028c:	00d8                	addi	a4,sp,68
-8100028e:	8100                	0x8100
-81000290:	00dc                	addi	a5,sp,68
-81000292:	8100                	0x8100
-81000294:	00e0                	addi	s0,sp,76
-81000296:	8100                	0x8100
-81000298:	00e4                	addi	s1,sp,76
-8100029a:	8100                	0x8100
-8100029c:	00e8                	addi	a0,sp,76
-8100029e:	8100                	0x8100
-810002a0:	00ec                	addi	a1,sp,76
-810002a2:	8100                	0x8100
-810002a4:	00f0                	addi	a2,sp,76
-810002a6:	8100                	0x8100
-810002a8:	00f4                	addi	a3,sp,76
-810002aa:	8100                	0x8100
-810002ac:	00f8                	addi	a4,sp,76
-810002ae:	8100                	0x8100
-810002b0:	00fc                	addi	a5,sp,76
-810002b2:	8100                	0x8100
-810002b4:	0100                	addi	s0,sp,128
-810002b6:	8100                	0x8100
-810002b8:	0104                	addi	s1,sp,128
-810002ba:	8100                	0x8100
-810002bc:	0108                	addi	a0,sp,128
-810002be:	8100                	0x8100
-810002c0:	010c                	addi	a1,sp,128
-810002c2:	8100                	0x8100
 
 Disassembly of section .bss:
 
-810002c4 <done>:
+8100027c <done>:
 	...
 
-810002e0 <main_sp>:
-810002e0:	0000                	unimp
+81000298 <main_sp>:
+81000298:	0000                	unimp
 	...
 
-810002e4 <context>:
+8100029c <context>:
 	...
 
-81000364 <q>:
+8100031c <q>:
 	...
 
-81002984 <done>:
+8100293c <done>:
 	...
 
-810029a0 <main_sp>:
-810029a0:	0000                	unimp
+81002958 <main_sp>:
+81002958:	0000                	unimp
 	...
 
-810029a4 <mat_mult_args>:
+8100295c <mat_mult_args>:
 	...
 
-810029b8 <mat_r_args>:
+81002970 <mat_r_args>:
 	...
 
-810029d0 <mat_e_args>:
+81002988 <mat_e_args>:
 	...
 
-810029e8 <x>:
+810029a0 <x>:
 	...
 
-810039e8 <y>:
+810039a0 <y>:
 	...
 
-810049e8 <z>:
+810049a0 <z>:
 	...
 
-810059e8 <done>:
+810059a0 <done>:
 	...
 
-81005a04 <main_sp>:
-81005a04:	0000                	unimp
+810059bc <main_sp>:
+810059bc:	0000                	unimp
 	...
 
 Disassembly of section .comment:
diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf
index 1bad09ba804b1b2812569d1cbf30315a5f75cb94..68431a8407e2a3171b5211c061505c2f59158e18 100755
GIT binary patch
delta 2570
zcmb`IZA?>F7{{M`+j4cAqve7{inMS`tBe@H4(h;+8BCGP)EP51VKWmpoy*1+)M(O-
z+q6<Q6>1(-Bt(c|i!r+CNY-TI18yYU5)JB{TjmmQn$#>?T9zgF0^Od|UbvS86F=C5
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zwG*vIV_DV2e{FF9OWY{$Lc6h?GC`c@4>uVdS>Hc+4|K3Y1~Bu$i9Bz^!^Td|jQOVT
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AzyJUM

delta 2805
zcmb`Je@qi+7{{Nx77kI@!htQIwoqE;W)@HeEU*n7a?XuenVF6anf%b<FO0AaH#4rG
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diff --git a/kernel/vortex_test.hex b/kernel/vortex_test.hex
index 1e7886e6..e3063c3e 100644
--- a/kernel/vortex_test.hex
+++ b/kernel/vortex_test.hex
@@ -1,393 +1,375 @@
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 :10001000340000003500000036000000370000000A
@@ -412,27 +394,22 @@
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 :100150002D2D2D2D2D2D2D2D2D2D2D2D0A00000079
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-:1002A400F0000081F4000081F8000081FC0000816E
-:1002B4000001008104010081080100810C0100811A
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+:10026C000001008104010081080100810C01008162
 :040000058000000077
 :00000001FF
diff --git a/kernel/vx_include/vx_front.c b/kernel/vx_include/vx_front.c
index c64db4c7..cc51ba2e 100644
--- a/kernel/vx_include/vx_front.c
+++ b/kernel/vx_include/vx_front.c
@@ -74,21 +74,21 @@ void _vx_mat_mult(unsigned tid, unsigned wid)
 		unsigned total = 0;
 		for (unsigned place = 0; place < mat_dim; ++place)
 		{
-			unsigned x_i = (wid * mat_dim)   + place;
-			unsigned y_i = (mat_dim * place) + i_index;
+			unsigned x_i = (wid     * mat_dim)   + place;
+			unsigned y_i = (mat_dim * place  )   + i_index;
 
 			total += (x_ptr[x_i] * y_ptr[y_i]);
 		}
 
 			int final_i = (wid * mat_dim) + i_index;
-			unsigned cond = i_index < mat_dim;
-			__if(cond)
-			{
+			// unsigned cond = i_index < mat_dim;
+			// __if(cond)
+			// {
 				z_ptr[final_i] = total;
 				i_index++;
-			}
-			__else
-			__end_if
+			// }
+			// __else
+			// __end_if
 	}
 
 	// for (int z = 0; z < ((1000 * wid) + 1000); z++);
diff --git a/kernel/vx_main.c b/kernel/vx_main.c
index 28b83600..f9b88ac9 100644
--- a/kernel/vx_main.c
+++ b/kernel/vx_main.c
@@ -5,10 +5,10 @@ unsigned x[1024] = {0};
 unsigned y[1024] = {0};
 unsigned z[1024] = {0};
 
-#define MAT_DIM 8
+#define MAT_DIM 16
 
-#define NUM_COLS 8
-#define NUM_ROWS 8
+#define NUM_COLS 16
+#define NUM_ROWS 16
 
 void initialize_mats()
 {
@@ -42,28 +42,28 @@ int main()
 	print_matrix(z);
 
 
-	// matrix addition
-	vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);
-	vx_print_str("\n\nMatrix Addition\n");
-	print_matrix(z);
+	// // matrix addition
+	// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);
+	// vx_print_str("\n\nMatrix Addition\n");
+	// print_matrix(z);
 
 
-	// matrix sub
-	vx_mat_sub(x, y, z, NUM_ROWS, NUM_COLS);
-	vx_print_str("\n\nMatrix Subtraction\n");
-	print_matrix(z);
+	// // matrix sub
+	// vx_mat_sub(x, y, z, NUM_ROWS, NUM_COLS);
+	// vx_print_str("\n\nMatrix Subtraction\n");
+	// print_matrix(z);
 
-	unsigned scal = 3;
+	// unsigned scal = 3;
 
-	// matrix element add
-	vx_e_mat_add(z, &scal, z, NUM_ROWS, NUM_COLS);
-	vx_print_str("\n\nMatrix Element Addition\n");
-	print_matrix(z);
+	// // matrix element add
+	// vx_e_mat_add(z, &scal, z, NUM_ROWS, NUM_COLS);
+	// vx_print_str("\n\nMatrix Element Addition\n");
+	// print_matrix(z);
 
-	// matrix element add
-	vx_e_mat_mult(z, &scal, z, NUM_ROWS, NUM_COLS);
-	vx_print_str("\n\nMatrix Element Addition\n");
-	print_matrix(z);
+	// // matrix element add
+	// vx_e_mat_mult(z, &scal, z, NUM_ROWS, NUM_COLS);
+	// vx_print_str("\n\nMatrix Element Addition\n");
+	// print_matrix(z);
 
 
 	return 0;
diff --git a/kernel/vx_os/vx_back/vx_back.s b/kernel/vx_os/vx_back/vx_back.s
index 546d309a..c913d2d8 100644
--- a/kernel/vx_os/vx_back/vx_back.s
+++ b/kernel/vx_os/vx_back/vx_back.s
@@ -6,7 +6,7 @@
 .type _start, @function
 .global _start
 _start:
-    li a0, 1          # Num Warps
+    li a0, 2          # Num Warps
     csrw 0x20, a0     # Setting the number of available warps 
     li a0, 2          # Num Threads
     csrw 0x21, a0     # Setting the number of available threads
@@ -31,11 +31,17 @@ loop_cond:
 loop_body:
     addi  sp,sp,-2048 # Allocate 2k stack for new thread
     mv    t1, a0      # #lane = i
-    .word 0x3506b           # clone register state
+    .word 0x3506b     # clone register state
 loop_inc:
     addi a0, a0, 1
     j loop_cond
 loop_done:
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop
     mv    sp,t5  # Restoring the stack
     li    a0,0   # setting tid = 0 for main thread
     mv    t6,a2  # setting func_addr 
diff --git a/rtl/VX_context.v b/rtl/VX_context.v
index c18e255e..eebe0b99 100644
--- a/rtl/VX_context.v
+++ b/rtl/VX_context.v
@@ -4,6 +4,7 @@
 module VX_context (
   input wire        clk,
   input wire        in_warp,
+  input wire        in_wb_warp,
   input wire        in_valid[`NT_M1:0],
   input wire        in_write_register,
   input wire[4:0]   in_rd,
@@ -20,18 +21,26 @@ module VX_context (
 
   output reg[31:0]   out_a_reg_data[`NT_M1:0],
   output reg[31:0]   out_b_reg_data[`NT_M1:0],
-  output wire        out_clone_stall
+  output wire        out_clone_stall,
+  output wire[31:0]  w0_t0_registers[31:0]
 	
 );
+		reg[5:0] state_stall;
+		initial begin
+			state_stall = 0;
+		end
+
 		wire[31:0] rd1_register[`NT_M1:0];
 		wire[31:0] rd2_register[`NT_M1:0];
 		/* verilator lint_off UNUSED */
 		wire[31:0] clone_regsiters[31:0];
 		/* verilator lint_on UNUSED */
+
+		assign w0_t0_registers = clone_regsiters;
 		
 		VX_register_file vx_register_file_master(
 			.clk               (clk),
-			.in_warp           (in_warp),
+			.in_wb_warp        (in_wb_warp),
 			.in_valid          (in_valid[0]),
 			.in_write_register (in_write_register),
 			.in_rd             (in_rd),
@@ -52,6 +61,7 @@ module VX_context (
 			VX_register_file_slave vx_register_file_slave(
 				.clk               (clk),
 				.in_warp           (in_warp),
+				.in_wb_warp        (in_wb_warp),
 				.in_valid          (in_valid[index]),
 				.in_write_register (in_write_register),
 				.in_rd             (in_rd),
@@ -64,11 +74,10 @@ module VX_context (
 				.out_src1_data     (rd1_register[index]),
 				.out_src2_data     (rd2_register[index])
 			);
-		  end  
+		  end
 		endgenerate
 
 
-		reg[5:0] state_stall = 0;
 		always @(posedge clk) begin
 			if ((in_is_clone) && state_stall == 0) begin
 				state_stall <= 10;
diff --git a/rtl/VX_context_slave.v b/rtl/VX_context_slave.v
new file mode 100644
index 00000000..fc5c4d0b
--- /dev/null
+++ b/rtl/VX_context_slave.v
@@ -0,0 +1,145 @@
+
+`include "VX_define.v"
+
+module VX_context_slave (
+  input wire        clk,
+  input wire        in_warp,
+  input wire        in_wb_warp,
+  input wire        in_valid[`NT_M1:0],
+  input wire        in_write_register,
+  input wire[4:0]   in_rd,
+  input wire[31:0]  in_write_data[`NT_M1:0],
+  input wire[4:0]   in_src1,
+  input wire[4:0]   in_src2,
+  input wire[31:0]  in_curr_PC,
+  input wire        in_is_clone,
+  input wire        in_is_jal,
+  input wire        in_src1_fwd,
+  input wire[31:0]  in_src1_fwd_data[`NT_M1:0],
+  input wire        in_src2_fwd,
+  input wire[31:0]  in_src2_fwd_data[`NT_M1:0],
+  input wire[31:0]  in_wspawn_regs[31:0],
+  input wire        in_wspawn,
+
+  output reg[31:0]   out_a_reg_data[`NT_M1:0],
+  output reg[31:0]   out_b_reg_data[`NT_M1:0],
+  output wire        out_clone_stall
+	
+);
+		wire[31:0] rd1_register[`NT_M1:0];
+		wire[31:0] rd2_register[`NT_M1:0];
+		/* verilator lint_off UNUSED */
+		wire[31:0] clone_regsiters[31:0];
+		/* verilator lint_on UNUSED */
+
+
+		reg[5:0] clone_state_stall = 0;
+		reg[5:0] wspawn_state_stall = 0;
+
+		initial begin
+			clone_state_stall  = 0;
+			wspawn_state_stall = 0;
+		end
+
+
+		wire to_wspawn = wspawn_state_stall == 2;
+		// always @(*) begin
+		// 	if (to_wspawn)
+		// 		$display("-----> to_wspawn == 1");
+		// end
+		VX_register_file_master_slave vx_register_file_master(
+			.clk               (clk),
+			.in_wb_warp        (in_wb_warp),
+			.in_valid          (in_valid[0]),
+			.in_write_register (in_write_register),
+			.in_rd             (in_rd),
+			.in_data           (in_write_data[0]),
+			.in_src1           (in_src1),
+			.in_src2           (in_src2),
+			.in_wspawn         (in_wspawn),
+			.in_to_wspawn      (to_wspawn),
+			.in_wspawn_regs    (in_wspawn_regs),
+			.out_regs          (clone_regsiters),
+			.out_src1_data     (rd1_register[0]),
+			.out_src2_data     (rd2_register[0])
+		);
+
+		genvar index;
+		generate  
+		for (index=1; index < `NT; index=index+1)  
+		  begin: gen_code_label  
+			wire to_clone;
+		  	assign to_clone = (index == rd1_register[0]) && (clone_state_stall == 1);
+			VX_register_file_slave vx_register_file_slave(
+				.clk               (clk),
+				.in_warp           (in_warp),
+				.in_wb_warp        (in_wb_warp),
+				.in_valid          (in_valid[index]),
+				.in_write_register (in_write_register),
+				.in_rd             (in_rd),
+				.in_data           (in_write_data[index]),
+				.in_src1           (in_src1),
+				.in_src2           (in_src2),
+				.in_clone          (in_is_clone),
+				.in_to_clone       (to_clone),
+				.in_regs           (clone_regsiters),
+				.out_src1_data     (rd1_register[index]),
+				.out_src2_data     (rd2_register[index])
+			);
+		  end
+		endgenerate
+
+		// always @(*) begin
+		// 	if (in_valid[0] && in_valid[1]) begin
+		// 		$display("Reg write: %h %h", in_write_data[0], in_write_data[1]);
+		// 	end else if (in_valid[0]) begin
+		// 		$display("Reg write: %h", in_write_data[0]);
+		// 	end
+		// end
+
+
+		// for clone
+		always @(posedge clk) begin
+			if ((in_is_clone) && clone_state_stall == 0) begin
+				clone_state_stall <= 10;
+				// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
+			end else if (clone_state_stall == 1) begin
+				// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, in_is_clone);
+				clone_state_stall <= 0;
+			end else if (clone_state_stall > 0) begin
+				clone_state_stall <= clone_state_stall - 1;
+				// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
+			end
+		end
+
+
+		// for wspawn
+		always @(posedge clk) begin
+			if ((in_wspawn) && wspawn_state_stall == 0) begin
+				wspawn_state_stall <= 10;
+				// $display("starting wspawn stalling -- in_wspawn: %d -- stall %d", in_wspawn, wspwan_stall);
+			end else if (wspawn_state_stall == 1) begin
+				// $display("ENDING wspawn stalling -- in_wspawn %d -- stall: %d", in_wspawn, wspwan_stall);
+				wspawn_state_stall <= 0;
+			end else if (wspawn_state_stall > 0) begin
+				wspawn_state_stall <= wspawn_state_stall - 1;
+				// $display("wspawn state: %d  in_wspawn: %d -- stall: %d", wspawn_state_stall, in_wspawn, wspwan_stall);
+			end
+		end
+
+
+		genvar index_out_reg;
+		generate
+			for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
+				begin
+					assign out_a_reg_data[index_out_reg]   = (    (in_is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
+					assign out_b_reg_data[index_out_reg]   = (in_src2_fwd == 1'b1) ?  in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
+				end
+		endgenerate
+
+		wire clone_stall  = ((clone_state_stall  == 0) && in_is_clone) || ((clone_state_stall  != 1) && in_is_clone);
+		wire wspwan_stall = ((wspawn_state_stall == 0) && in_wspawn)   || (wspawn_state_stall   > 1);
+
+		assign out_clone_stall = clone_stall || wspwan_stall;
+
+endmodule
\ No newline at end of file
diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v
index 3fb8901f..c9b0115a 100644
--- a/rtl/VX_decode.v
+++ b/rtl/VX_decode.v
@@ -3,55 +3,55 @@
 
 module VX_decode(
 	// Fetch Inputs
-	input wire        clk,
-	input wire[31:0]  in_instruction,
-	input wire[31:0]  in_curr_PC,
-	input wire        in_valid[`NT_M1:0],
+	input wire            clk,
+	input wire[31:0]      in_instruction,
+	input wire[31:0]      in_curr_PC,
+	input wire            in_valid[`NT_M1:0],
 	// WriteBack inputs
-	input wire[31:0]  in_write_data[`NT_M1:0],
-	input wire[4:0]   in_rd,
-	input wire[1:0]   in_wb,
-	input wire        in_wb_valid[`NT_M1:0],
-	input wire[`NW_M1:0]   in_wb_warp_num,
+	input wire[31:0]      in_write_data[`NT_M1:0],
+	input wire[4:0]       in_rd,
+	input wire[1:0]       in_wb,
+	input wire            in_wb_valid[`NT_M1:0],
+	input wire[`NW_M1:0]  in_wb_warp_num,
 
 	// FORWARDING INPUTS
-	input wire        in_src1_fwd,
-	input wire[31:0]  in_src1_fwd_data[`NT_M1:0],
-	input wire        in_src2_fwd,
-	input wire[31:0]  in_src2_fwd_data[`NT_M1:0],
-
-	input wire[`NW_M1:0]   in_warp_num,
-
-
-	output wire[11:0] out_csr_address,
-	output wire       out_is_csr,
-	output wire[31:0] out_csr_mask,
+	input wire            in_src1_fwd,
+	input wire[31:0]      in_src1_fwd_data[`NT_M1:0],
+	input wire            in_src2_fwd,
+	input wire[31:0]      in_src2_fwd_data[`NT_M1:0],
 
+	input wire[`NW_M1:0]  in_warp_num,
 
+	output wire[11:0]     out_csr_address,
+	output wire           out_is_csr,
+	output wire[31:0]     out_csr_mask,
 
 	// Outputs
-	output wire[4:0]  out_rd,
-	output wire[4:0]  out_rs1,
-	output wire[4:0]  out_rs2,
-	output wire[31:0] out_a_reg_data[`NT_M1:0],
-	output wire[31:0] out_b_reg_data[`NT_M1:0],
-	output wire[1:0]  out_wb,
-	output wire[4:0]  out_alu_op,
-	output wire       out_rs2_src,
-	output reg[31:0]  out_itype_immed,
-	output wire[2:0]  out_mem_read,
-	output wire[2:0]  out_mem_write,
-	output reg[2:0]   out_branch_type,
-	output reg        out_branch_stall,
-	output reg        out_jal,
-	output reg[31:0]  out_jal_offset,
-	output reg[19:0]  out_upper_immed,
-	output wire[31:0] out_PC_next,
-	output reg        out_clone_stall,
-	output wire       out_change_mask,
-	output wire       out_thread_mask[`NT_M1:0],
-	output wire       out_valid[`NT_M1:0],
-	output wire[`NW_M1:0]  out_warp_num
+	output wire[4:0]      out_rd,
+	output wire[4:0]      out_rs1,
+	output wire[4:0]      out_rs2,
+	output wire[31:0]     out_a_reg_data[`NT_M1:0],
+	output wire[31:0]     out_b_reg_data[`NT_M1:0],
+	output wire[1:0]      out_wb,
+	output wire[4:0]      out_alu_op,
+	output wire           out_rs2_src,
+	output reg[31:0]      out_itype_immed,
+	output wire[2:0]      out_mem_read,
+	output wire[2:0]      out_mem_write,
+	output reg[2:0]       out_branch_type,
+	output reg            out_branch_stall,
+	output reg            out_jal,
+	output reg[31:0]      out_jal_offset,
+	output reg[19:0]      out_upper_immed,
+	output wire[31:0]     out_PC_next,
+	output reg            out_clone_stall,
+	output wire           out_change_mask,
+	output wire           out_thread_mask[`NT_M1:0],
+	output wire           out_valid[`NT_M1:0],
+	output wire[`NW_M1:0] out_warp_num,
+	output wire           out_wspawn,
+	output wire[31:0]     out_wspawn_pc,
+	output wire           out_ebreak
 );
 
 		wire[6:0]  curr_opcode;
@@ -73,6 +73,7 @@ module VX_decode(
 		wire       is_clone;
 		wire       is_jalrs;
 		wire       is_jmprt;
+		wire       is_wspawn;
 
 		wire       write_register;
 
@@ -110,11 +111,28 @@ module VX_decode(
 		reg[4:0]   alu_op;
 		reg[4:0]   mul_alu;
 
-		wire context_zero_valid = (in_wb_warp_num == 0);
+		wire[31:0] w0_t0_registers[31:0];
 
-		VX_context VX_Context(
+		wire       context_zero_valid = (in_wb_warp_num == 0);
+		wire[31:0] zero_a_reg_data[`NT_M1:0];
+		wire[31:0] zero_b_reg_data[`NT_M1:0];
+		reg        zero_clone_stall;
+
+		// always @(*) begin
+		// 	$display("DECODE WARP: %h", in_warp_num);
+		// end
+
+		wire curr_warp_zero  = in_warp_num == 0;
+		wire curr_warp_one   = in_warp_num == 1;
+
+		// always @(*) begin
+		// 	$display("DECODE WARP: %h PC: %h",in_warp_num, in_curr_PC);
+		// end
+
+		VX_context VX_Context_zero(
 			.clk              (clk),
-			.in_warp          (context_zero_valid),
+			.in_warp          (curr_warp_zero),
+			.in_wb_warp       (context_zero_valid),
 			.in_valid         (in_wb_valid),
 			.in_rd            (in_rd),
 			.in_src1          (out_rs1),
@@ -128,13 +146,52 @@ module VX_decode(
 			.in_src2_fwd_data (in_src2_fwd_data),
 			.in_write_register(write_register),
 			.in_write_data    (in_write_data),
-			.out_a_reg_data   (out_a_reg_data),
-			.out_b_reg_data   (out_b_reg_data),
-			.out_clone_stall  (out_clone_stall)
-			);
+			.out_a_reg_data   (zero_a_reg_data),
+			.out_b_reg_data   (zero_b_reg_data),
+			.out_clone_stall  (zero_clone_stall),
+			.w0_t0_registers  (w0_t0_registers)
+		);
+
+		wire       context_one_valid = (in_wb_warp_num == 1);
+		wire[31:0] one_a_reg_data[`NT_M1:0];
+		wire[31:0] one_b_reg_data[`NT_M1:0];
+		reg        one_clone_stall;
+		VX_context_slave VX_Context_one(
+			.clk              (clk),
+			.in_warp          (curr_warp_one),
+			.in_wb_warp       (context_one_valid),
+			.in_valid         (in_wb_valid),
+			.in_rd            (in_rd),
+			.in_src1          (out_rs1),
+			.in_src2          (out_rs2),
+			.in_curr_PC       (in_curr_PC),
+			.in_is_clone      (is_clone),
+			.in_is_jal        (is_jal),
+			.in_src1_fwd      (in_src1_fwd),
+			.in_src1_fwd_data (in_src1_fwd_data),
+			.in_src2_fwd      (in_src2_fwd),
+			.in_src2_fwd_data (in_src2_fwd_data),
+			.in_write_register(write_register),
+			.in_write_data    (in_write_data),
+			.in_wspawn_regs   (w0_t0_registers),
+			.in_wspawn        (is_wspawn),
+			.out_a_reg_data   (one_a_reg_data),
+			.out_b_reg_data   (one_b_reg_data),
+			.out_clone_stall  (one_clone_stall)
+		);
+
+		assign out_a_reg_data  = curr_warp_zero ? zero_a_reg_data  : one_a_reg_data;
+		assign out_b_reg_data  = curr_warp_zero ? zero_b_reg_data  : one_b_reg_data;
+		assign out_clone_stall = zero_clone_stall || one_clone_stall;
+
+		// always @(*) begin
+		// 	if (context_one_valid) begin
+		// 		$display("PC: %h -> src1: %h\tsrc2: %h",in_curr_PC, one_a_reg_data[0], one_b_reg_data[0]);
+		// 	end
+		// end
 
 		assign out_warp_num = in_warp_num;
-		assign out_valid = in_valid;
+		assign out_valid    = in_valid;
 
 		assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
 
@@ -171,6 +228,10 @@ module VX_decode(
 		assign is_clone     = is_gpgpu && (func3 == 5);
 		assign is_jalrs     = is_gpgpu && (func3 == 6);
 		assign is_jmprt     = is_gpgpu && (func3 == 4);
+		assign is_wspawn    = is_gpgpu && (func3 == 0);
+
+		assign out_wspawn    = is_wspawn;
+		assign out_wspawn_pc = out_a_reg_data[0];
 
 		// always @(*) begin
 		// 	if (is_jalrs) begin
@@ -259,7 +320,7 @@ module VX_decode(
 			case(curr_opcode)
 				`LUI_INST:   out_upper_immed  = {func7, out_rs2, out_rs1, func3};
 				`AUIPC_INST: out_upper_immed  = {func7, out_rs2, out_rs1, func3};
-				default:    out_upper_immed  = 20'h0;
+				default:     out_upper_immed  = 20'h0;
 			endcase // curr_opcode
 		end
 
@@ -306,6 +367,7 @@ module VX_decode(
 					end
 				`SYS_INST:
 					begin
+						// $display("SYS EBREAK %h", (jal_sys_jal && in_valid[0]) );
 						out_jal        = jal_sys_jal && in_valid[0];
 						out_jal_offset = jal_sys_off;
 					end
@@ -317,6 +379,13 @@ module VX_decode(
 			endcase
 		end
 
+		wire is_ebreak;
+
+
+		assign is_ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && in_valid[0]);
+
+
+		assign out_ebreak = is_ebreak;
 
 		// CSR
 
diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v
index a156b629..a483b96c 100644
--- a/rtl/VX_execute.v
+++ b/rtl/VX_execute.v
@@ -68,6 +68,13 @@ module VX_execute (
 				end
 		endgenerate
 
+		// always @(*) begin
+		// 	if ((in_alu_op == `MUL) && (in_warp_num == 1)) begin
+		// 		$display("@PC: %h ---> %d * %d = %d\t%d * %d = %d", in_curr_PC, in_a_reg_data[0], in_b_reg_data[0], out_alu_result[0], in_a_reg_data[1], in_b_reg_data[1], out_alu_result[1]);
+		// 	end
+		
+		// end
+
 
 		assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
 		assign out_jal      = in_jal;
diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v
index 090b80f8..f9e52047 100644
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -2,30 +2,34 @@
 `include "VX_define.v"
 
 module VX_fetch (
-	input  wire        clk,
-	input  wire        reset,
-	input  wire        in_branch_dir,
-	input  wire        in_freeze,
-	input  wire[31:0]  in_branch_dest,
-	input  wire        in_branch_stall,
-	input  wire        in_fwd_stall,
-	input  wire        in_branch_stall_exe,
-	input  wire        in_clone_stall,
-	input  wire        in_jal,
-	input  wire[31:0]  in_jal_dest,
-	input  wire        in_interrupt,
-	input  wire        in_debug,
-	input  wire[31:0]  in_instruction,
-	input  wire        in_thread_mask[`NT_M1:0],
-	input  wire        in_change_mask,
+	input  wire           clk,
+	input  wire           reset,
+	input  wire           in_branch_dir,
+	input  wire           in_freeze,
+	input  wire[31:0]     in_branch_dest,
+	input  wire           in_branch_stall,
+	input  wire           in_fwd_stall,
+	input  wire           in_branch_stall_exe,
+	input  wire           in_clone_stall,
+	input  wire           in_jal,
+	input  wire[31:0]     in_jal_dest,
+	input  wire           in_interrupt,
+	input  wire           in_debug,
+	input  wire[31:0]     in_instruction,
+	input  wire           in_thread_mask[`NT_M1:0],
+	input  wire           in_change_mask,
 	input  wire[`NW_M1:0] in_decode_warp_num,
 	input  wire[`NW_M1:0] in_memory_warp_num,
+	input  wire           in_wspawn,
+	input  wire[31:0]     in_wspawn_pc,
+	input  wire           in_ebreak,
 
-	output wire[31:0]  out_instruction,
-	output wire        out_delay,
+	output wire[31:0]     out_instruction,
+	output wire           out_delay,
 	output wire[`NW_M1:0] out_warp_num,
-	output wire[31:0]  out_curr_PC,
-	output wire        out_valid[`NT_M1:0]
+	output wire[31:0]     out_curr_PC,
+	output wire           out_valid[`NT_M1:0],
+	output wire           out_ebreak
 );
 
 		reg       stall;
@@ -39,42 +43,98 @@ module VX_fetch (
 			warp_state = 0;
 		end
 
+		wire add_warp    = in_wspawn && !in_ebreak && !in_clone_stall;
+		wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
+
 		always @(posedge clk or posedge reset) begin
-			if (reset || (warp_num == warp_state)) begin
-				warp_num <= 0;
+			if (reset || (warp_num == warp_state) || remove_warp || add_warp) begin
+				warp_num   <= 0;
 			end else begin
-				warp_num <= warp_num + 1;
+				warp_num   <= warp_num + 1;
 			end
 
+			if (add_warp) begin
+				// $display("Adding a new warp %h", warp_state);
+				warp_state <= warp_state + 1;
+			end else if (remove_warp) begin
+				// $display("Removing a warp %h", warp_state);
+				warp_state <= warp_state - 1;
+			end
 		end
 
+		assign out_ebreak = (warp_state == 0) && in_ebreak;
+
 
 		assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
 
 
-		wire[31:0] warp_pc;
-		wire       warp_valid[`NT_M1:0];
 
+		wire       warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
+		wire       warp_zero_jal         = in_jal         && (in_memory_warp_num == 0);
+		wire       warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == 0);
+		wire       warp_zero_stall       = stall          || (warp_num == 1);
+		wire       warp_zero_wspawn      = 0;
+		wire[31:0] warp_zero_wspawn_pc   = 32'h0;
 
-		wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
-		wire warp_zero_jal         = in_jal         && (in_memory_warp_num == 0);
-		wire warp_zero_branch      = in_branch_dir  && (in_memory_warp_num == 0);
-		VX_warp VX_Warp(
+		wire[31:0] warp_zero_pc;
+		wire       warp_zero_valid[`NT_M1:0];
+		VX_warp VX_Warp_zero(
 			.clk           (clk),
 			.reset         (reset),
-			.stall         (stall),
+			.stall         (warp_zero_stall),
 			.in_thread_mask(in_thread_mask),
 			.in_change_mask(warp_zero_change_mask),
 			.in_jal        (warp_zero_jal),
 			.in_jal_dest   (in_jal_dest),
 			.in_branch_dir (warp_zero_branch),
 			.in_branch_dest(in_branch_dest),
-			.out_PC        (warp_pc),
-			.out_valid     (warp_valid)
+			.in_wspawn     (warp_zero_wspawn),
+			.in_wspawn_pc  (warp_zero_wspawn_pc),
+			.out_PC        (warp_zero_pc),
+			.out_valid     (warp_zero_valid)
 			);
 
 
-		assign out_PC = warp_pc;
+		wire       warp_one_change_mask = in_change_mask && (in_decode_warp_num == 1);
+		wire       warp_one_jal         = in_jal         && (in_memory_warp_num == 1);
+		wire       warp_one_branch      = in_branch_dir  && (in_memory_warp_num == 1);
+		wire       warp_one_stall       = stall          || (warp_num == 0);
+		wire[31:0] warp_one_pc;
+		wire       warp_one_valid[`NT_M1:0];
+		VX_warp VX_Warp_one(
+			.clk           (clk),
+			.reset         (reset),
+			.stall         (warp_one_stall),
+			.in_thread_mask(in_thread_mask),
+			.in_change_mask(warp_one_change_mask),
+			.in_jal        (warp_one_jal),
+			.in_jal_dest   (in_jal_dest),
+			.in_branch_dir (warp_one_branch),
+			.in_branch_dest(in_branch_dest),
+			.in_wspawn     (in_wspawn),
+			.in_wspawn_pc  (in_wspawn_pc),
+			.out_PC        (warp_one_pc),
+			.out_valid     (warp_one_valid)
+			);
+
+		// always @(*) begin
+		// 	if (in_wspawn) begin
+		// 		$display("Spawning a warp @ %h",in_wspawn_pc);
+		// 	end
+		// end
+
+		// always @(posedge clk) begin 
+		// 	$display("curr warp: %h Threads:%d%d PC: %h", warp_num, out_valid[0],out_valid[1], out_PC);
+		// end
+
+		// always @(*) begin
+		// 	if (warp_num == 1) begin
+		// 		$display("Going to PC: %h", warp_one_pc);
+		// 	end
+		// end
+
+		assign out_PC    = (warp_num == 0) ? warp_zero_pc    : warp_one_pc;
+		assign out_valid = (warp_num == 0) ? warp_zero_valid : warp_one_valid;
 
 		// always @(*) begin
 		// 	$display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
@@ -82,9 +142,9 @@ module VX_fetch (
 
 
 		assign out_curr_PC     = out_PC;
-		assign out_valid       = warp_valid;
 		assign out_warp_num    = warp_num;
 		assign out_delay       = 0;
+
 		assign out_instruction = stall ? 32'b0 : in_instruction;
 
 
diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v
index cca232f2..fa271841 100644
--- a/rtl/VX_memory.v
+++ b/rtl/VX_memory.v
@@ -65,6 +65,12 @@ module VX_memory (
 		assign out_cache_driver_in_data      = in_rd2;
 		assign out_cache_driver_in_valid     = in_valid;
 
+		// always @(*) begin
+		// 	if (in_valid[0] && (in_mem_write == `SW_MEM_WRITE) && (in_alu_result[0] >= 32'h810049a0)) begin
+		// 		$display("SW$ PC: %h - Warp: %h -> [%h]%h = %h || [%h]%h = %h",in_curr_PC, in_warp_num, in_valid[0], in_alu_result[0], in_rd2[0], in_valid[1], in_alu_result[1], in_rd2[1]);
+		// 	end
+		// end
+
 
 
 		// wire[31:0] sm_out_data[`NT_M1:0];
@@ -113,7 +119,13 @@ module VX_memory (
 					end
 				`BLT:  out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
 				`BGT:  out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN     : `NOT_TAKEN;
-				`BLTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
+				`BLTU: 
+					begin 
+						out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN; 
+						if (in_warp_num == 1) begin
+							// $display("BLTU PC:%h : %d < %d = %d", in_curr_PC, in_rs1, in_rs2, (in_alu_result[0][31] == 0)); 
+						end
+					end
 				`BGTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN     : `NOT_TAKEN;
 				`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
 				default:    out_branch_dir = `NOT_TAKEN;
diff --git a/rtl/VX_register_file.v b/rtl/VX_register_file.v
index 61cba771..c9273125 100644
--- a/rtl/VX_register_file.v
+++ b/rtl/VX_register_file.v
@@ -2,7 +2,7 @@
 
 module VX_register_file (
   input wire        clk,
-  input wire        in_warp,
+  input wire        in_wb_warp,
   input wire        in_valid,
   input wire        in_write_register,
   input wire[4:0]   in_rd,
@@ -30,6 +30,11 @@ module VX_register_file (
 	// 	end
 	// end
 
+	// always @(*) begin
+	// 	$display("TID: %d: %h",10,registers[10]);
+	// 	$display("WID: %d: %h",11,registers[11]);
+	// end
+
 	assign out_regs = registers;
 
 	assign write_data     = in_data;
@@ -38,7 +43,7 @@ module VX_register_file (
 	assign write_enable   = (in_write_register && (in_rd != 5'h0)) && in_valid;
 
 	always @(posedge clk) begin
-		if(write_enable && in_warp) begin
+		if(write_enable && in_wb_warp) begin
 			// $display("RF: Writing %h to %d",write_data, write_register);
 			registers[write_register] <= write_data;
 		end
diff --git a/rtl/VX_register_file_master_slave.v b/rtl/VX_register_file_master_slave.v
new file mode 100644
index 00000000..cf50d9e5
--- /dev/null
+++ b/rtl/VX_register_file_master_slave.v
@@ -0,0 +1,72 @@
+
+module VX_register_file_master_slave (
+  input wire         clk,
+  input wire         in_wb_warp,
+  input wire         in_valid,
+  input wire         in_write_register,
+  input wire[4:0]    in_rd,
+  input wire[31:0]   in_data,
+  input wire[4:0]    in_src1,
+  input wire[4:0]    in_src2,
+  input wire         in_wspawn,
+  input wire         in_to_wspawn,
+  input wire[31:0]   in_wspawn_regs[31:0],
+
+  output reg[31:0]   out_src1_data,
+  output reg[31:0]   out_src2_data,
+  output wire[31:0]  out_regs[31:0]
+);
+
+	reg[31:0] registers[31:0];
+
+	wire[31:0] write_data;
+
+	wire[4:0] write_register;
+
+	wire write_enable;
+
+
+	assign out_regs = registers;
+
+	// reg[5:0] i;
+	// always @(posedge clk) begin
+	// 	for (i = 0; i < 32; i++) begin
+	// 		$display("%d: %h",i, registers[i[4:0]]);
+	// 	end
+	// end
+
+	// integer i;
+
+	assign write_data     = in_data;
+	assign write_register = in_rd;
+
+	// always @(*) begin
+	// 	$display("TID: %d: %h",10,registers[10]);
+	// 	$display("WID: %d: %h",11,registers[11]);
+	// end
+
+	assign write_enable   = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
+
+	always @(posedge clk) begin
+		if(write_enable && !in_wspawn) begin
+			// $display("RF: Writing %h to %d",write_data, write_register);
+			registers[write_register] <= write_data;
+		end else if (in_wspawn && in_to_wspawn) begin
+			// $display("WSPAWN IN MASTER SLAVE");
+			registers <= in_wspawn_regs;
+		end
+	end
+
+	// always @(posedge clk) begin
+	// 	for (i = 0; i < 32; i = i + 1)
+	// 		$display("(%d): %x", i, registers[i]);
+	
+	// end
+
+	always @(negedge clk) begin
+		out_src1_data <= registers[in_src1];
+		out_src2_data <= registers[in_src2];
+	end
+
+
+endmodule
\ No newline at end of file
diff --git a/rtl/VX_register_file_slave.v b/rtl/VX_register_file_slave.v
index 2a2e8b88..77951f3b 100644
--- a/rtl/VX_register_file_slave.v
+++ b/rtl/VX_register_file_slave.v
@@ -6,6 +6,7 @@
 module VX_register_file_slave (
   input wire         clk,
   input wire         in_warp,
+  input wire         in_wb_warp,
   input wire         in_valid,
   input wire         in_write_register,
   input wire[4:0]    in_rd,
@@ -37,17 +38,23 @@ module VX_register_file_slave (
 
 	// integer i;
 
+	// always @(*) begin
+	// 	if (in_warp) begin
+	// 		$display("TID: %d: %h",10,registers[10]);
+	// 		$display("WID: %d: %h",11,registers[11]);
+	// 	end
+	// end
+
 	assign write_data     = in_data;
 	assign write_register = in_rd;
 
-	assign write_enable   = (in_write_register && (in_rd != 5'h0)) && in_valid;
+	assign write_enable   = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
 
 	always @(posedge clk) begin
-		if(write_enable && !in_clone && in_warp) begin
+		if(write_enable && !in_clone) begin
 			// $display("RF: Writing %h to %d",write_data, write_register);
 			registers[write_register] <= write_data;
-		end else if (in_clone && in_to_clone) begin
-			// $display("CLONING IN SLAVE");
+		end else if (in_clone && in_to_clone && in_warp) begin
 			registers <= in_regs;
 		end
 	end
diff --git a/rtl/VX_warp.v b/rtl/VX_warp.v
index f81b2871..cf6039c3 100644
--- a/rtl/VX_warp.v
+++ b/rtl/VX_warp.v
@@ -11,7 +11,8 @@ module VX_warp (
 	input  wire[31:0] in_jal_dest,
 	input  wire       in_branch_dir,
 	input  wire[31:0] in_branch_dest,
-
+	input  wire       in_wspawn,
+	input  wire[31:0] in_wspawn_pc,
 
 	output wire[31:0] out_PC,
 	output wire       out_valid[`NT_M1:0]
@@ -62,7 +63,10 @@ module VX_warp (
 		always @(posedge clk or posedge reset) begin
 			if (reset) begin
 				real_PC <= 0;
-			end else if (stall == 1'b0) begin
+			end else if (in_wspawn == 1'b1) begin
+				// $display("Inside warp ***** Spawn @ %H",in_wspawn_pc);
+				real_PC <= in_wspawn_pc;
+			end else if (!stall) begin
 				real_PC <= use_PC + 32'h4;
 			end else begin
 				real_PC <= use_PC;
diff --git a/rtl/Vortex.v b/rtl/Vortex.v
index b7ddee77..34c23946 100644
--- a/rtl/Vortex.v
+++ b/rtl/Vortex.v
@@ -13,7 +13,8 @@ module Vortex(
 	output wire[2:0]      out_cache_driver_in_mem_read,
 	output wire[2:0]      out_cache_driver_in_mem_write,
 	output wire           out_cache_driver_in_valid[`NT_M1:0],
-	output wire[31:0]     out_cache_driver_in_data[`NT_M1:0]
+	output wire[31:0]     out_cache_driver_in_data[`NT_M1:0],
+	output wire           out_ebreak
 	);
 
 // wire[31:0] in_cache_driver_out_data[`NT_M1:0];
@@ -25,11 +26,12 @@ module Vortex(
 assign curr_PC = fetch_curr_PC;
 
 // From fetch
-wire[31:0]   fetch_instruction;
-wire         fetch_delay;
-wire[31:0]   fetch_curr_PC;
-wire         fetch_valid[`NT_M1:0];
+wire[31:0]     fetch_instruction;
+wire           fetch_delay;
+wire[31:0]     fetch_curr_PC;
+wire           fetch_valid[`NT_M1:0];
 wire[`NW_M1:0] fetch_warp_num;
+wire           fetch_ebreak;
 
 // From f_d_register
 wire[31:0]   f_d_instruction;
@@ -62,7 +64,10 @@ wire            decode_valid[`NT_M1:0];
 wire            decode_clone_stall;
 wire            decode_change_mask;
 wire            decode_thread_mask[`NT_M1:0];
-wire[`NW_M1:0]    decode_warp_num;
+wire[`NW_M1:0]  decode_warp_num;
+wire            decode_wspawn;
+wire[31:0]      decode_wspawn_pc;
+wire            decode_ebreak;
 
 // From d_e_register
 wire[11:0]      d_e_csr_address;
@@ -193,7 +198,7 @@ wire debug;
 assign debug        = 1'b0;
 assign interrupt    = 1'b0;
 assign total_freeze = fetch_delay || memory_delay;
-
+assign out_ebreak   = fetch_ebreak;
 
 VX_fetch vx_fetch(
 		.clk                (clk),
@@ -214,12 +219,16 @@ VX_fetch vx_fetch(
 		.in_change_mask     (decode_change_mask),
 		.in_decode_warp_num (decode_warp_num),
 		.in_memory_warp_num (memory_warp_num),
+		.in_wspawn          (decode_wspawn),
+		.in_wspawn_pc       (decode_wspawn_pc),
+		.in_ebreak          (decode_ebreak),
 
 		.out_instruction    (fetch_instruction),
 		.out_delay          (fetch_delay),
 		.out_curr_PC        (fetch_curr_PC),
 		.out_warp_num       (fetch_warp_num),
-		.out_valid          (fetch_valid)
+		.out_valid          (fetch_valid),
+		.out_ebreak         (fetch_ebreak)
 	);
 
 
@@ -280,7 +289,10 @@ VX_decode vx_decode(
 		.out_clone_stall (decode_clone_stall),
 		.out_change_mask (decode_change_mask),
 		.out_thread_mask (decode_thread_mask),
-		.out_warp_num    (decode_warp_num)
+		.out_warp_num    (decode_warp_num),
+		.out_wspawn      (decode_wspawn),
+		.out_wspawn_pc   (decode_wspawn_pc),
+		.out_ebreak      (decode_ebreak)
 	);
 
 
diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex
index fb1f5621a128ad78bfa1828db23c8e44893fb36a..5882e08dba35a8d869979c6893e81d27c8c40e10 100755
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diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp
index 8d6a0f68..de9647a3 100644
--- a/rtl/obj_dir/VVortex.cpp
+++ b/rtl/obj_dir/VVortex.cpp
@@ -95,12 +95,21 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_initial__TOP__1\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    // INITIAL at VX_warp.v:27
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC = 0U;
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] = 0U;
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] = 1U;
-    // INITIAL at VX_context.v:71
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0U;
+    // INITIAL at VX_warp.v:28
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC = 0U;
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[1U] = 0U;
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[0U] = 1U;
+    // INITIAL at VX_warp.v:28
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC = 0U;
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[1U] = 0U;
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[0U] = 1U;
+    // INITIAL at VX_context.v:29
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0U;
+    // INITIAL at VX_context_slave.v:36
+    // INITIAL at VX_context_slave.v:37
+    // INITIAL at VX_context_slave.v:39
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall = 0U;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall = 0U;
     // INITIAL at VX_m_w_reg.v:41
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = 0U;
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = 0U;
@@ -161,7 +170,7 @@ void VVortex::_initial__TOP__1(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num = 0U;
-    // INITIAL at VX_fetch.v:37
+    // INITIAL at VX_fetch.v:41
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state = 0U;
 }
@@ -182,105 +191,109 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
@@ -288,10 +301,110 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[1U];
@@ -322,7 +435,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:404
+    // ALWAYS at VX_decode.v:473
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -348,10 +461,19 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal 
+	= ((0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			 >> 0xcU))) & (2U > (0xfffU 
+					     & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+						>> 0x14U))));
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone = 
 	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
 	 & (5U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			 >> 0xcU))));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn 
+	= ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
+	   & (0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			   >> 0xcU))));
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt = 
 	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
 	 & (4U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
@@ -392,6 +514,9 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 						   [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address]))));
     vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read;
     vlTOPp->out_cache_driver_in_mem_write = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_write;
+    vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
+					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
+						  << 1U));
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
 	[1U];
@@ -464,106 +589,202 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
 	[0U];
     vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
+	[0U];
     vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
@@ -572,7 +793,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[0U];
-    // ALWAYS at VX_decode.v:335
+    // ALWAYS at VX_decode.v:404
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -707,12 +928,22 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 							       >> 0x14U)))
 							 : 0xdeadbeefU)
 						        : 0xdeadbeefU))))));
-    vlTOPp->Vortex__DOT__decode_clone_stall = (((0U 
-						 == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)) 
-						| (1U 
-						   != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) 
-					       & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone));
-    // ALWAYS at VX_decode.v:287
+    vlTOPp->Vortex__DOT__decode_clone_stall = ((((0U 
+						  == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)) 
+						 | (1U 
+						    != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) 
+						& (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)) 
+					       | ((((0U 
+						     == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall)) 
+						    | (1U 
+						       != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall))) 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)) 
+						  | (((0U 
+						       == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)) 
+						      & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn)) 
+						     | (1U 
+							< (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)))));
+    // ALWAYS at VX_decode.v:348
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -800,7 +1031,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     } else {
 	vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU;
     }
-    // ALWAYS at VX_decode.v:346
+    // ALWAYS at VX_decode.v:415
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -859,10 +1090,8 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     } else {
 	vlTOPp->Vortex__DOT__decode_branch_type = 0U;
     }
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask 
-	= (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) 
-	    | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)) 
-	   & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) 
+					       | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt));
     vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
@@ -913,106 +1142,298 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
 	[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
@@ -1110,6 +1531,12 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 							  >> 0x19U)))
 						      ? 0U
 						      : 1U))))))))));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask 
+	= ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) 
+	   & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask 
+	= ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) 
+	   & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] 
 	= vlTOPp->Vortex__DOT__e_m_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] 
@@ -1170,10 +1597,16 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
@@ -1182,7 +1615,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[0U];
-    // ALWAYS at VX_decode.v:287
+    // ALWAYS at VX_decode.v:348
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -1196,16 +1629,7 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 						      & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 1U) 
 							 & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-							    & (((0U 
-								 == 
-								 (7U 
-								  & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-								     >> 0xcU))) 
-								& (2U 
-								   > 
-								   (0xfffU 
-								    & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-								       >> 0x14U)))) 
+							    & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) 
 							       & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 							       [0U])))));
 	    } else {
@@ -1247,7 +1671,12 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     } else {
 	vlTOPp->Vortex__DOT__decode_jal = 0U;
     }
-    // ALWAYS at VX_decode.v:346
+    vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak 
+	= ((0x73U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
+	   & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) 
+	      & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	      [0U]));
+    // ALWAYS at VX_decode.v:415
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -1295,6 +1724,102 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     } else {
 	vlTOPp->Vortex__DOT__decode_branch_stall = 0U;
     }
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] 
 	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
 	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
@@ -1327,45 +1852,58 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
-    // ALWAYS at VX_warp.v:49
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC 
-	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
-	    & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
-	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
-	    : ((((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		  ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		      ? ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) 
-			 & (~ (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			       [0U] >> 0x1fU))) : (
-						   (1U 
-						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-						    ? 
-						   (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-						    [0U] 
-						    >> 0x1fU)
-						    : 
-						   (~ 
-						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-						     [0U] 
-						     >> 0x1fU))))
-		  : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		      ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-			  ? (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			     [0U] >> 0x1fU) : (0U != 
-					       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-					       [0U]))
-		      : ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) 
-			 & (0U == vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			    [0U])))) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
-	        ? (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
-		   + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
-		      << 1U)) : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC));
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
+    // ALWAYS at VX_memory.v:113
+    vlTOPp->Vortex__DOT__memory_branch_dir = (1U & 
+					      ((4U 
+						& (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+					        ? (
+						   (2U 
+						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						    ? 
+						   ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) 
+						    & (~ 
+						       (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+							[0U] 
+							>> 0x1fU)))
+						    : 
+						   ((1U 
+						     & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						     ? 
+						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U] 
+						     >> 0x1fU)
+						     : 
+						    (~ 
+						     (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						      [0U] 
+						      >> 0x1fU))))
+					        : (
+						   (2U 
+						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						    ? 
+						   ((1U 
+						     & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						     ? 
+						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U] 
+						     >> 0x1fU)
+						     : 
+						    (0U 
+						     != 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U]))
+						    : 
+						   ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) 
+						    & (0U 
+						       == 
+						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						       [0U])))));
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[1U];
@@ -1408,10 +1946,116 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[0U];
+    vlTOPp->out_ebreak = ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)) 
+			  & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp = 
+	(((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) 
+	  & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak))) 
+	 & (~ (IData)(vlTOPp->Vortex__DOT__decode_clone_stall)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak) 
+	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn))) 
+	   & (~ (IData)(vlTOPp->Vortex__DOT__decode_clone_stall)));
     vlTOPp->Vortex__DOT__vx_fetch__DOT__stall = ((((IData)(vlTOPp->Vortex__DOT__decode_clone_stall) 
 						   | (IData)(vlTOPp->Vortex__DOT__decode_branch_stall)) 
 						  | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) 
 						 | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall));
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0U];
     vlTOPp->Vortex__DOT__writeback_write_data[1U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[1U];
@@ -1430,11 +2074,28 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
-    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC;
     vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
 	[1U];
     vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
 	[0U];
+    // ALWAYS at VX_warp.v:50
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
+	    & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
+	    : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) 
+		& (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	        ? vlTOPp->Vortex__DOT__memory_branch_dest
+	        : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC));
+    // ALWAYS at VX_warp.v:50
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
+	    & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
+	    : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) 
+		& (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	        ? vlTOPp->Vortex__DOT__memory_branch_dest
+	        : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC));
     vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
@@ -1461,6 +2122,108 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__decode_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__decode_valid[0U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) 
+	   | (1U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) 
+	   | (0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[1U];
@@ -1471,6 +2234,10 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__memory_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__memory_valid[0U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC = ((0U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+						   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC
+						   : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC);
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
@@ -1741,12 +2508,19 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
 						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))))));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	[0U];
+    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] 
@@ -1899,54 +2673,122 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
 	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data
-	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data
+	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register
 	       [0U]));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[1U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
 	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data
-	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data
+	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register
 	       [1U]));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[0U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data
+	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register
+	       [0U]));
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[1U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data
+	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register
+	       [1U]));
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data
-	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register
 	   [0U]);
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data
-	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register
 	   [1U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[0U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register
+	   [0U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[1U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register
+	   [1U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data
+	   [0U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data
+	   [0U]);
     vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
@@ -1987,45 +2829,82 @@ void VVortex::_settle__TOP__2(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__decode_thread_mask[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[0U] 
 	= vlTOPp->Vortex__DOT__decode_thread_mask[0U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[1U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
 	[1U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[0U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
 	[0U];
-    // ALWAYS at VX_warp.v:35
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
+	[1U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
+	[0U];
+    // ALWAYS at VX_warp.v:36
     if (vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask) {
-	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] 
-	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[1U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
 	    [1U];
-	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] 
-	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[0U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
 	    [0U];
     }
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[0U] 
+    // ALWAYS at VX_warp.v:36
+    if (vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask) {
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[1U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	    [1U];
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[0U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	    [0U];
+    }
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask)
-	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
-	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
+	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid
 		   [0U]));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[1U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask)
-	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
-	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
+	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid
 		   [1U]));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[0U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask)
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid
+		   [0U]));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[1U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask)
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid
+		   [1U]));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid
 	[1U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid
+	[0U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid
+	   [1U] : vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid
+	   [0U] : vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid
+	   [0U]);
     vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
@@ -2041,89 +2920,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp)
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Variables
     // Begin mtask footprint  all: 
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0);
-    // Body
-    vlTOPp->__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num;
-    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U;
-    // ALWAYS at VX_fetch.v:42
-    vlTOPp->__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num 
-	= (3U & (((IData)(vlTOPp->reset) | ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num) 
-					    == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)))
-		  ? 0U : ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))));
-    // ALWAYS at VX_warp.v:62
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC 
-	= ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)
-					   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC
-					   : ((IData)(4U) 
-					      + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC)));
-    // ALWAYS at VX_f_d_reg.v:36
-    if (vlTOPp->reset) {
-	__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U;
-    } else {
-	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
-		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 
-		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
-		[1U];
-	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U;
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 
-		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
-		[0U];
-	}
-    }
-    // ALWAYSPOST at VX_f_d_reg.v:42
-    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) {
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U;
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U;
-    }
-    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) {
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2;
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3;
-    }
-    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
-	[0U];
-    vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
-	[1U];
-    vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
-	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__f_d_valid[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
-	= vlTOPp->Vortex__DOT__f_d_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
-	[0U];
-    vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
-	[1U];
-    vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
-	[0U];
-}
-
-VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__4\n"); );
-    VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Variables
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0);
-    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,0,0);
-    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
+    VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
+    VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall,5,0);
+    VL_SIG8(__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1,0,0);
+    VL_SIG8(__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0);
@@ -2133,40 +2943,106 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0);
     VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
     VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
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     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0);
@@ -2180,12 +3056,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0);
     // Body
-    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall;
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 = 0U;
+    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall;
+    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall;
+    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 0U;
     // ALWAYS at VX_m_w_reg.v:63
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
@@ -2207,17 +3091,47 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
 	[0U];
-    // ALWAYS at VX_context.v:72
+    // ALWAYS at VX_context.v:81
     if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) 
-	 & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)))) {
-	__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0xaU;
+	 & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) {
+	__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0xaU;
     } else {
-	if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) {
-	    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = 0U;
+	if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) {
+	    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = 0U;
 	} else {
-	    if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) {
-		__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall 
-		    = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall) 
+	    if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) {
+		__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall 
+		    = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall) 
+				- (IData)(1U)));
+	    }
+	}
+    }
+    // ALWAYS at VX_context_slave.v:102
+    if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) 
+	 & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall)))) {
+	__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall = 0xaU;
+    } else {
+	if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall))) {
+	    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall = 0U;
+	} else {
+	    if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall))) {
+		__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall 
+		    = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall) 
+				- (IData)(1U)));
+	    }
+	}
+    }
+    // ALWAYS at VX_context_slave.v:117
+    if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) 
+	 & (0U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)))) {
+	__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall = 0xaU;
+    } else {
+	if ((1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall))) {
+	    __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall = 0U;
+	} else {
+	    if ((0U < (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall))) {
+		__Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall 
+		    = (0x3fU & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall) 
 				- (IData)(1U)));
 	    }
 	}
@@ -2273,11 +3187,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
 	[0U];
-    // ALWAYS at VX_e_m_reg.v:128
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal;
-    // ALWAYS at VX_e_m_reg.v:128
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
     // ALWAYS at VX_d_e_reg.v:145
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -2290,6 +3199,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
 	   [0U]);
     // ALWAYS at VX_e_m_reg.v:128
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal;
+    // ALWAYS at VX_e_m_reg.v:128
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
+    // ALWAYS at VX_e_m_reg.v:128
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read;
     // ALWAYS at VX_e_m_reg.v:128
@@ -2317,16 +3231,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
 	   [0U]);
-    // ALWAYS at VX_register_file.v:40
+    // ALWAYS at VX_register_file.v:45
     if (((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
 	   & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
-	  & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid
+	  & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid
 	  [0U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num)))) {
-	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 
-	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data
 	    [0U];
-	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0 
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
     }
     // ALWAYS at VX_csr_handler.v:43
@@ -2348,118 +3262,349 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
 	   [0U]);
-    // ALWAYS at VX_register_file_slave.v:45
+    // ALWAYS at VX_register_file_master_slave.v:50
     if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
 	    & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
-	   & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid
-	   [1U]) & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone))) 
-	 & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num)))) {
-	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
-	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data
-	    [1U];
-	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
+	   & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid
+	   [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) 
+	 & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn)))) {
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data
+	    [0U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0 
 	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
     } else {
-	if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) 
-	     & ((1U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register
-		 [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))))) {
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	if (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) 
+	     & (2U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)))) {
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1fU];
-	    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U;
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1 = 1U;
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v2 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1eU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v3 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1dU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v4 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1cU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v5 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1bU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v6 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x1aU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v7 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x19U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v8 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x18U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v9 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x17U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v10 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x16U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v11 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x15U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v12 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x14U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v13 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x13U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v14 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x12U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v15 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x11U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v16 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0x10U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v17 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xfU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v18 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xeU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v19 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xdU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v20 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xcU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v21 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xbU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v22 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[0xaU];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v23 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[9U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v24 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[8U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v25 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[7U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v26 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[6U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v27 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[5U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v28 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[4U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v29 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[3U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v30 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[2U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v31 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
 		[1U];
-	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 
-		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v32 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs
+		[0U];
+	}
+    }
+    // ALWAYS at VX_register_file_slave.v:53
+    if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+	    & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+	   & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid
+	   [1U]) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) 
+	 & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)))) {
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data
+	    [1U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
+    } else {
+	if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) 
+	      & ((1U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register
+		  [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)))) 
+	     & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) {
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1fU];
+	    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U;
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1eU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1dU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1cU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1bU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1aU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x19U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x18U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x17U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x16U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x15U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x14U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x13U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x12U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x11U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x10U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xfU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xeU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xdU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xcU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xbU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xaU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[9U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[8U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[7U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[6U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[5U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[4U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[3U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[2U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[1U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0U];
+	}
+    }
+    // ALWAYS at VX_register_file_slave.v:53
+    if ((((((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) 
+	    & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd))) 
+	   & vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid
+	   [1U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num))) 
+	 & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)))) {
+	__Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data
+	    [1U];
+	__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 = 1U;
+	__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0 
+	    = vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd;
+    } else {
+	if ((((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone) 
+	      & ((1U == vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register
+		  [0U]) & (1U == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall)))) 
+	     & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)))) {
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1fU];
+	    __Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1 = 1U;
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1eU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1dU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1cU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1bU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x1aU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x19U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x18U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x17U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x16U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x15U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x14U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x13U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x12U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x11U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0x10U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xfU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xeU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xdU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xcU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xbU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[0xaU];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[9U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[8U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[7U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[6U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[5U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[4U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[3U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[2U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
+		[1U];
+	    __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32 
+		= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs
 		[0U];
 	}
     }
@@ -2503,10 +3648,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1;
-    // ALWAYSPOST at VX_register_file.v:43
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers__v0;
+    // ALWAYSPOST at VX_register_file.v:48
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers__v0;
     }
     // ALWAYSPOST at VX_csr_handler.v:45
     if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) {
@@ -2518,79 +3663,225 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1;
-    // ALWAYSPOST at VX_register_file_slave.v:48
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall 
+	= __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall;
+    // ALWAYSPOST at VX_register_file_master_slave.v:53
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v0;
     }
-    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) {
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31;
-	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] 
-	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32;
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1fU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v1;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1eU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v2;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1dU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v3;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1cU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v4;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1bU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v5;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x1aU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v6;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x19U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v7;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x18U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v8;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x17U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v9;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x16U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v10;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x15U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v11;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x14U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v12;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x13U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v13;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x12U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v14;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x11U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v15;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0x10U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v16;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xfU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v17;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xeU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v18;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xdU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v19;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xcU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v20;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xbU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v21;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0xaU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v22;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[9U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v23;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[8U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v24;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[7U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v25;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[6U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v26;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[5U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v27;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[4U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v28;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[3U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v29;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[2U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v30;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[1U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v31;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[0U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers__v32;
     }
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall 
-	= __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall;
+    // ALWAYSPOST at VX_register_file_slave.v:56
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0;
+    }
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32;
+    }
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall 
+	= __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall;
+    // ALWAYSPOST at VX_register_file_slave.v:56
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0;
+    }
+    if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1) {
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1fU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1eU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1dU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1cU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1bU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x1aU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x19U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x18U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x17U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x16U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x15U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x14U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x13U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x12U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x11U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0x10U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xfU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xeU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xdU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xcU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xbU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0xaU] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[9U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[8U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[7U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[6U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[5U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[4U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[3U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[2U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[1U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31;
+	vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[0U] 
+	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32;
+    }
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall 
+	= __Vdly__Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall;
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[1U];
@@ -2627,6 +3918,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[0U];
     // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal = ((~ (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)) 
 						 & (IData)(vlTOPp->Vortex__DOT__decode_jal));
@@ -2634,12 +3931,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type));
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
-	[0U];
     vlTOPp->out_cache_driver_in_mem_read = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__mem_read;
     // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__mem_read 
@@ -2662,6 +3953,9 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? 0U : vlTOPp->Vortex__DOT__decode_jal_offset);
+    vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
+					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
+						  << 1U));
     // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -2682,101 +3976,101 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
 	[0U];
     // ALWAYS at VX_e_m_reg.v:128
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address 
@@ -2800,12 +4094,108 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[0U];
+    // ALWAYS at VX_m_w_reg.v:63
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd;
     // ALWAYS at VX_m_w_reg.v:63
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num;
     // ALWAYS at VX_m_w_reg.v:63
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd;
-    // ALWAYS at VX_m_w_reg.v:63
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb;
     vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[1U];
@@ -2839,101 +4229,101 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs
 	[0U];
     vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U 
 						 == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))
@@ -2961,6 +4351,102 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	[1U];
     vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs
+	[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
@@ -2993,13 +4479,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
-    vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
-						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
-						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[0U];
+    vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
+						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
+						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
@@ -3012,101 +4498,197 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__d_e_a_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__d_e_a_reg_data[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1fU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1eU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1dU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1cU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1bU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x1aU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x19U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x18U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x17U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x16U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x15U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x14U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x13U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x12U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x11U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0x10U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xfU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xeU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xdU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xcU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xbU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0xaU];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[9U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[8U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[7U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[6U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[5U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[4U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[3U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[2U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters
 	[0U];
     // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_address 
@@ -3137,17 +4719,119 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__d_e_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__d_e_b_reg_data[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters
+	[0U];
+    // ALWAYS at VX_e_m_reg.v:128
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd;
     // ALWAYS at VX_e_m_reg.v:128
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num;
     // ALWAYS at VX_e_m_reg.v:128
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd;
-    // ALWAYS at VX_e_m_reg.v:128
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb;
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] 
@@ -3188,6 +4872,52 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
+    // ALWAYS at VX_memory.v:113
+    vlTOPp->Vortex__DOT__memory_branch_dir = (1U & 
+					      ((4U 
+						& (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+					        ? (
+						   (2U 
+						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						    ? 
+						   ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) 
+						    & (~ 
+						       (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+							[0U] 
+							>> 0x1fU)))
+						    : 
+						   ((1U 
+						     & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						     ? 
+						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U] 
+						     >> 0x1fU)
+						     : 
+						    (~ 
+						     (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						      [0U] 
+						      >> 0x1fU))))
+					        : (
+						   (2U 
+						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						    ? 
+						   ((1U 
+						     & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
+						     ? 
+						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U] 
+						     >> 0x1fU)
+						     : 
+						    (0U 
+						     != 
+						     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						     [0U]))
+						    : 
+						   ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) 
+						    & (0U 
+						       == 
+						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+						       [0U])))));
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[1U];
@@ -3200,6 +4930,102 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[1U];
@@ -3250,6 +5076,102 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__w0_t0_registers
+	[0U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
@@ -3265,10 +5187,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 					      [1U]), 
 		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2));
     // ALWAYS at VX_d_e_reg.v:145
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num 
-	= (3U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-		  ? 0U : (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
-    // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU 
 						& ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 						    ? 0U
@@ -3276,6 +5194,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 						   (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						    >> 7U)));
     // ALWAYS at VX_d_e_reg.v:145
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num 
+	= (3U & ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+		  ? 0U : (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    // ALWAYS at VX_d_e_reg.v:145
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 						 ? 0U
 						 : 
@@ -3343,6 +5265,102 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__execute_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__execute_valid[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1fU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1fU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1eU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1eU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1dU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1dU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1cU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1cU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1bU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1bU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x1aU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x1aU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x19U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x19U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x18U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x18U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x17U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x17U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x16U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x16U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x15U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x15U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x14U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x14U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x13U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x13U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x12U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x12U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x11U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x11U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0x10U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0x10U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xfU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xfU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xeU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xeU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xdU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xdU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xcU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xcU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xbU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xbU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0xaU] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0xaU];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[9U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[9U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[8U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[8U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[7U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[7U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[6U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[6U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[5U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[5U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[4U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[4U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[3U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[3U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[2U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[2U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs
+	[0U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__execute_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] 
@@ -3601,10 +5619,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 						 (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 						  [1U] 
 						  + vlTOPp->Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2))))));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[0U] 
@@ -3625,6 +5649,157 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
 }
 
+VL_INLINE_OPT void VVortex::_sequent__TOP__4(VVortex__Syms* __restrict vlSymsp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__4\n"); );
+    VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+    // Variables
+    // Begin mtask footprint  all: 
+    VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
+    VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_state,1,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0);
+    // Body
+    __Vdly__Vortex__DOT__vx_fetch__DOT__warp_state 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state;
+    __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num;
+    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U;
+    // ALWAYS at VX_warp.v:63
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC 
+	= ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall)
+					   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC
+					   : ((IData)(4U) 
+					      + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC)));
+    // ALWAYS at VX_fetch.v:49
+    __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = 
+	(3U & (((((IData)(vlTOPp->reset) | ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num) 
+					    == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state))) 
+		 | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp)) 
+		| (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp))
+	        ? 0U : ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))));
+    if (vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp) {
+	__Vdly__Vortex__DOT__vx_fetch__DOT__warp_state 
+	    = (3U & ((IData)(1U) + (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)));
+    } else {
+	if (vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp) {
+	    __Vdly__Vortex__DOT__vx_fetch__DOT__warp_state 
+		= (3U & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state) 
+			 - (IData)(1U)));
+	}
+    }
+    // ALWAYS at VX_warp.v:63
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC 
+	= ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn)
+					   ? vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+					  [0U] : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall)
+						   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC
+						   : 
+						  ((IData)(4U) 
+						   + vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC))));
+    // ALWAYS at VX_f_d_reg.v:36
+    if (vlTOPp->reset) {
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U;
+    } else {
+	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
+		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
+	    vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC 
+		= vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC;
+	}
+    }
+    // ALWAYS at VX_f_d_reg.v:36
+    if (vlTOPp->reset) {
+	__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U;
+    } else {
+	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
+		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 
+		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
+		[1U];
+	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U;
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 
+		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
+		[0U];
+	}
+    }
+    // ALWAYS at VX_f_d_reg.v:36
+    if (vlTOPp->reset) {
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num = 0U;
+    } else {
+	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
+		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
+	    vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num 
+		= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num;
+	}
+    }
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state 
+	= __Vdly__Vortex__DOT__vx_fetch__DOT__warp_state;
+    // ALWAYSPOST at VX_f_d_reg.v:42
+    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) {
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U;
+    }
+    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) {
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] 
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] 
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3;
+    }
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num;
+    // ALWAYS at VX_warp.v:50
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
+	    & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
+	    : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) 
+		& (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	        ? vlTOPp->Vortex__DOT__memory_branch_dest
+	        : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC));
+    // ALWAYS at VX_warp.v:50
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
+	    & (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
+	    : (((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) 
+		& (1U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
+	        ? vlTOPp->Vortex__DOT__memory_branch_dest
+	        : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC));
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[0U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC = ((0U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+						   ? vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC
+						   : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC);
+    vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[0U];
+    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__out_PC;
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[0U];
+    vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
+	= vlTOPp->Vortex__DOT__decode_valid[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
+	= vlTOPp->Vortex__DOT__decode_valid[0U];
+}
+
 VL_INLINE_OPT void VVortex::_combo__TOP__5(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__5\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
@@ -3657,64 +5832,68 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp)
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__6\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    // ALWAYS at VX_register_file_slave.v:61
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
+    // ALWAYS at VX_register_file_slave.v:68
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0xfU))];
-    // ALWAYS at VX_register_file.v:47
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    // ALWAYS at VX_register_file_slave.v:68
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0xfU))];
-    // ALWAYS at VX_register_file_slave.v:61
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
+    // ALWAYS at VX_register_file_master_slave.v:66
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    // ALWAYS at VX_register_file_slave.v:68
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0x14U))];
-    // ALWAYS at VX_register_file.v:47
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers
+    // ALWAYS at VX_register_file_slave.v:68
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers
 	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		   >> 0x14U))];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data;
+    // ALWAYS at VX_register_file_master_slave.v:66
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:52
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    // ALWAYS at VX_register_file.v:52
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data;
 }
 
 VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__7\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
-	= vlTOPp->Vortex__DOT__decode_valid[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
-	= vlTOPp->Vortex__DOT__decode_valid[0U];
-    // ALWAYS at VX_f_d_reg.v:36
-    if (vlTOPp->reset) {
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U;
-    } else {
-	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
-		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
-	    vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC 
-		= vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC;
-	}
-    }
-    // ALWAYS at VX_f_d_reg.v:36
-    if (vlTOPp->reset) {
-	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num = 0U;
-    } else {
-	if ((1U & (~ ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) 
-		      | (IData)(vlTOPp->Vortex__DOT__decode_clone_stall))))) {
-	    vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num 
-		= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num;
-	}
-    }
     // ALWAYS at VX_f_d_reg.v:36
     if (vlTOPp->reset) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U;
@@ -3726,41 +5905,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 		    ? 0U : vlTOPp->fe_instruction);
 	}
     }
-    // ALWAYS at VX_warp.v:49
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC 
-	= (((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
-	    & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
-	    ? vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest
-	    : ((((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		  ? ((2U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		      ? ((~ (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) 
-			 & (~ (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			       [0U] >> 0x1fU))) : (
-						   (1U 
-						    & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-						    ? 
-						   (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-						    [0U] 
-						    >> 0x1fU)
-						    : 
-						   (~ 
-						    (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-						     [0U] 
-						     >> 0x1fU))))
-		  : ((2U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-		      ? ((1U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type))
-			  ? (vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			     [0U] >> 0x1fU) : (0U != 
-					       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-					       [0U]))
-		      : ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type) 
-			 & (0U == vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-			    [0U])))) & (0U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)))
-	        ? (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
-		   + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
-		      << 1U)) : vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num = vlTOPp->__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num;
-    vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC;
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = 
 	((0x13U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
 	 | (3U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)));
@@ -3779,7 +5923,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						  (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 						   >> 0x14U)
 						   : 0x55U));
-    // ALWAYS at VX_decode.v:404
+    // ALWAYS at VX_decode.v:473
     vlTOPp->__Vtableidx1 = (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				  >> 0xcU));
     vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu = 
@@ -3805,14 +5949,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						      (7U 
 						       & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 0xcU))));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal 
+	= ((0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			 >> 0xcU))) & (2U > (0xfffU 
+					     & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+						>> 0x14U))));
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone = 
 	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
 	 & (5U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			 >> 0xcU))));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn 
+	= ((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
+	   & (0U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			   >> 0xcU))));
     vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt = 
 	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
 	 & (4U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			 >> 0xcU))));
+    vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = 
+	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
+	 & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			 >> 0xcU))));
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd 
 	= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			>> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
@@ -3820,10 +5977,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 				>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) 
 	   & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) 
 	      == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num)));
-    vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs = 
-	((0x6bU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
-	 & (6U == (7U & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-			 >> 0xcU))));
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd 
 	= (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			>> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
@@ -3832,7 +5985,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						!= (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) 
 	   & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) 
 	      == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__warp_num)));
-    // ALWAYS at VX_decode.v:335
+    // ALWAYS at VX_decode.v:404
     vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U 
 						& vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)
 					        ? (
@@ -3967,21 +6120,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 							       >> 0x14U)))
 							 : 0xdeadbeefU)
 						        : 0xdeadbeefU))))));
-    vlTOPp->Vortex__DOT__decode_clone_stall = (((0U 
-						 == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall)) 
-						| (1U 
-						   != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall))) 
-					       & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone));
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd 
-	= ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-			 >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) 
-	      & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-				 >> 0xfU)))) & (0U 
-						!= (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) 
-	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
-	   & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) 
-	      == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)));
-    // ALWAYS at VX_decode.v:287
+    vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak 
+	= ((0x73U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) 
+	   & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) 
+	      & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	      [0U]));
+    vlTOPp->Vortex__DOT__decode_clone_stall = ((((0U 
+						  == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall)) 
+						 | (1U 
+						    != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall))) 
+						& (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)) 
+					       | ((((0U 
+						     == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall)) 
+						    | (1U 
+						       != (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall))) 
+						   & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_clone)) 
+						  | (((0U 
+						       == (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)) 
+						      & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn)) 
+						     | (1U 
+							< (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall)))));
+    // ALWAYS at VX_decode.v:348
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -4069,7 +6228,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     } else {
 	vlTOPp->Vortex__DOT__decode_jal_offset = 0xdeadbeefU;
     }
-    // ALWAYS at VX_decode.v:287
+    // ALWAYS at VX_decode.v:348
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -4083,16 +6242,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 						      & ((vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 							  >> 1U) 
 							 & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-							    & (((0U 
-								 == 
-								 (7U 
-								  & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-								     >> 0xcU))) 
-								& (2U 
-								   > 
-								   (0xfffU 
-								    & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-								       >> 0x14U)))) 
+							    & ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__jal_sys_jal) 
 							       & vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 							       [0U])))));
 	    } else {
@@ -4134,7 +6284,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     } else {
 	vlTOPp->Vortex__DOT__decode_jal = 0U;
     }
-    // ALWAYS at VX_decode.v:346
+    // ALWAYS at VX_decode.v:415
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -4193,7 +6343,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     } else {
 	vlTOPp->Vortex__DOT__decode_branch_type = 0U;
     }
-    // ALWAYS at VX_decode.v:346
+    // ALWAYS at VX_decode.v:415
     if ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	if ((0x20U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
 	    if ((0x10U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) {
@@ -4241,10 +6391,17 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     } else {
 	vlTOPp->Vortex__DOT__decode_branch_stall = 0U;
     }
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask 
-	= (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) 
-	    | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt)) 
-	   & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__decode_change_mask = ((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jalrs) 
+					       | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_jmprt));
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd 
+	= ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			 >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) 
+	      & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+				 >> 0xfU)))) & (0U 
+						!= (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) 
+	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
+	   & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) 
+	      == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)));
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd 
 	= ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			 >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) 
@@ -4254,16 +6411,16 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) 
 	   & ((IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num) 
 	      == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__warp_num)));
-    vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd 
-	= (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-			  >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) 
-	       & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-				  >> 0xfU)))) & (0U 
-						 != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) 
-	     & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) 
-		== (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) 
-	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
-	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)));
+    vlTOPp->out_ebreak = ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_state)) 
+			  & (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__add_warp = 
+	(((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn) 
+	  & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak))) 
+	 & (~ (IData)(vlTOPp->Vortex__DOT__decode_clone_stall)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__remove_warp 
+	= (((IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_ebreak) 
+	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_wspawn))) 
+	   & (~ (IData)(vlTOPp->Vortex__DOT__decode_clone_stall)));
     vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu 
 	= ((0x63U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? ((5U > (IData)(vlTOPp->Vortex__DOT__decode_branch_type))
@@ -4345,6 +6502,22 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 							  >> 0x19U)))
 						      ? 0U
 						      : 1U))))))))));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask 
+	= ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) 
+	   & (0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask 
+	= ((IData)(vlTOPp->Vortex__DOT__decode_change_mask) 
+	   & (1U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd 
+	= (((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+			  >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) 
+	       & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+				  >> 0xfU)))) & (0U 
+						 != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) 
+	     & ((IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__warp_num) 
+		== (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))) 
+	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
+	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)));
     vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
 						   | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) 
 						  & (2U 
@@ -4377,6 +6550,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__forwarding_src2_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) 
 						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) 
+	   | (1U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) 
+	   | (0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num)));
 }
 
 VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) {
@@ -4519,54 +6698,122 @@ VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	[1U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	[0U];
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
 	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data
-	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data
+	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register
 	       [0U]));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[1U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
 	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
-	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data
-	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data
+	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register
 	       [1U]));
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[0U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data
+	       [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register
+	       [0U]));
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[1U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data
+	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register
+	       [1U]));
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data
-	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register
 	   [0U]);
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
-	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data
-	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register
 	   [1U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[0U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register
+	   [0U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[1U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register
+	   [1U]);
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data
+	[0U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data
+	[1U];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data
+	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_a_reg_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_a_reg_data
+	   [0U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data
+	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_decode__DOT__zero_b_reg_data
+	   [0U] : vlTOPp->Vortex__DOT__vx_decode__DOT__one_b_reg_data
+	   [0U]);
     vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
@@ -4607,45 +6854,82 @@ VL_INLINE_OPT void VVortex::_combo__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__decode_thread_mask[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[0U] 
 	= vlTOPp->Vortex__DOT__decode_thread_mask[0U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[1U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
 	[1U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[0U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
 	[0U];
-    // ALWAYS at VX_warp.v:35
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
+	[1U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask
+	[0U];
+    // ALWAYS at VX_warp.v:36
     if (vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask) {
-	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[1U] 
-	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[1U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
 	    [1U];
-	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[0U] 
-	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[0U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
 	    [0U];
     }
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[0U] 
+    // ALWAYS at VX_warp.v:36
+    if (vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask) {
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[1U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	    [1U];
+	vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[0U] 
+	    = vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	    [0U];
+    }
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[0U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask)
-	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
-	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
+	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid
 		   [0U]));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[1U] 
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask)
-	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask
-	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
-		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask
+	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid
 		   [1U]));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[0U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask)
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	   [0U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid
+		   [0U]));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[1U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_change_mask)
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask
+	   [1U] : ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_stall)) 
+		   & vlTOPp->Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid
+		   [1U]));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid
 	[1U];
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid
+	[0U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid[1U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid
+	[1U];
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid[0U] 
+	= vlTOPp->Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid
 	[0U];
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[1U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid
-	[1U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid
+	   [1U] : vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid
+	   [1U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[0U] 
-	= vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_valid
-	[0U];
+	= ((0U == (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_num))
+	    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_zero_valid
+	   [0U] : vlTOPp->Vortex__DOT__vx_fetch__DOT__warp_one_valid
+	   [0U]);
     vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
@@ -4660,11 +6944,11 @@ void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_eval\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) 
-	 | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
+    if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
 	vlTOPp->_sequent__TOP__3(vlSymsp);
     }
-    if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
+    if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) 
+	 | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
 	vlTOPp->_sequent__TOP__4(vlSymsp);
     }
     vlTOPp->_combo__TOP__5(vlSymsp);
@@ -4745,6 +7029,7 @@ void VVortex::_ctor_var_reset() {
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
+    out_ebreak = VL_RAND_RESET_I(1);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
@@ -4767,6 +7052,7 @@ void VVortex::_ctor_var_reset() {
 	    Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__decode_clone_stall = VL_RAND_RESET_I(1);
+    Vortex__DOT__decode_change_mask = VL_RAND_RESET_I(1);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__decode_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
     }}
@@ -4798,6 +7084,8 @@ void VVortex::_ctor_var_reset() {
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
+    Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1);
+    Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
@@ -5001,22 +7289,42 @@ void VVortex::_ctor_var_reset() {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_fetch__DOT__out_PC = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_fetch__DOT__warp_num = VL_RAND_RESET_I(2);
     Vortex__DOT__vx_fetch__DOT__warp_state = VL_RAND_RESET_I(2);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_fetch__DOT__warp_valid[__Vi0] = VL_RAND_RESET_I(1);
-    }}
+    Vortex__DOT__vx_fetch__DOT__add_warp = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_fetch__DOT__remove_warp = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_fetch__DOT__warp_zero_stall = VL_RAND_RESET_I(1);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[__Vi0] = VL_RAND_RESET_I(1);
+	    Vortex__DOT__vx_fetch__DOT__warp_zero_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
+	    Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
+	    Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    Vortex__DOT__vx_fetch__DOT__warp_one_change_mask = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_fetch__DOT__warp_one_stall = VL_RAND_RESET_I(1);
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_fetch__DOT__warp_one_valid[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC = VL_RAND_RESET_I(32);
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC = VL_RAND_RESET_I(32);
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32);
@@ -5029,25 +7337,66 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_decode__DOT__is_clone = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_decode__DOT__is_jalrs = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_decode__DOT__is_jmprt = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_decode__DOT__is_wspawn = VL_RAND_RESET_I(1);
+    Vortex__DOT__vx_decode__DOT__jal_sys_jal = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12);
     Vortex__DOT__vx_decode__DOT__mul_alu = VL_RAND_RESET_I(5);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__w0_t0_registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__zero_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__zero_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[__Vi0] = VL_RAND_RESET_I(1);
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[__Vi0] = VL_RAND_RESET_I(1);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__one_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__one_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
@@ -5055,32 +7404,63 @@ void VVortex::_ctor_var_reset() {
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[__Vi0] = VL_RAND_RESET_I(1);
     }}
+    Vortex__DOT__vx_decode__DOT__is_ebreak = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_decode__DOT__temp_final_alu = VL_RAND_RESET_I(5);
+    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall = VL_RAND_RESET_I(6);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall = VL_RAND_RESET_I(6);
-    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32);
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+	    Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall = VL_RAND_RESET_I(6);
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall = VL_RAND_RESET_I(6);
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data = VL_RAND_RESET_I(32);
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data = VL_RAND_RESET_I(32);
+    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data = VL_RAND_RESET_I(32);
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
+    }}
+    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
+	    Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5);
     { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
@@ -5193,5 +7573,4 @@ void VVortex::_ctor_var_reset() {
     __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[5] = 0x15U;
     __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[6] = 0x16U;
     __Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[7] = 0x17U;
-    __Vdly__Vortex__DOT__vx_fetch__DOT__warp_num = VL_RAND_RESET_I(2);
 }
diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h
index e6668355..5f027ce3 100644
--- a/rtl/obj_dir/VVortex.h
+++ b/rtl/obj_dir/VVortex.h
@@ -25,6 +25,7 @@ VL_MODULE(VVortex) {
     VL_IN8(reset,0,0);
     VL_OUT8(out_cache_driver_in_mem_read,2,0);
     VL_OUT8(out_cache_driver_in_mem_write,2,0);
+    VL_OUT8(out_ebreak,0,0);
     VL_IN(fe_instruction,31,0);
     VL_OUT(curr_PC,31,0);
     VL_IN(in_cache_driver_out_data[2],31,0);
@@ -41,23 +42,35 @@ VL_MODULE(VVortex) {
 	VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
 	VL_SIG8(Vortex__DOT__decode_jal,0,0);
 	VL_SIG8(Vortex__DOT__decode_clone_stall,0,0);
+	VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
 	VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
+	VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
 	VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
 	VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
 	VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,1,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask,0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_stall,0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_change_mask,0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_stall,0,0);
 	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,1,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
-	VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall,5,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
 	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
 	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
 	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
@@ -89,20 +102,24 @@ VL_MODULE(VVortex) {
 	VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
 	VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
 	VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
+    };
+    struct {
 	VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
 	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
 	VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
 	VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
+	VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
 	VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
-	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC,31,0);
-	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
 	VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
-    };
-    struct {
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
@@ -142,16 +159,30 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
 	VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
 	VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_valid[2],0,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[2],0,0);
 	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__zero_a_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__zero_b_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__one_a_reg_data[2],31,0);
+    };
+    struct {
+	VL_SIG(Vortex__DOT__vx_decode__DOT__one_b_reg_data[2],31,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2],0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2],0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[32],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[32],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
 	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
 	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
@@ -167,8 +198,6 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
-    };
-    struct {
 	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
 	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
     };
@@ -179,13 +208,16 @@ VL_MODULE(VVortex) {
     struct {
 	// Begin mtask footprint  all: 
 	VL_SIG8(__Vtableidx1,2,0);
-	VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
 	VL_SIG8(__Vclklast__TOP__clk,0,0);
 	VL_SIG8(__Vclklast__TOP__reset,0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
 	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
 	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
 	VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
@@ -239,24 +271,37 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
+    };
+    struct {
 	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
-    };
-    struct {
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
 	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[2],0,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[2],0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[2],0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[2],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[2],31,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[2],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[2],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[2],31,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[2],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
     };
     static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
     
diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a
index 8712c3475c9284e57682ce814873300b4539be92..5826850fd0ce66fc417fbc5cac299eca9104c1f5 100644
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diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
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diff --git a/rtl/obj_dir/VVortex__ver.d b/rtl/obj_dir/VVortex__ver.d
index d75f342b..59bfa3e0 100644
--- a/rtl/obj_dir/VVortex__ver.d
+++ b/rtl/obj_dir/VVortex__ver.d
@@ -1 +1 @@
-obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v 
+obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v 
diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat
index 8abc1a82..0b79583a 100644
--- a/rtl/obj_dir/VVortex__verFiles.dat
+++ b/rtl/obj_dir/VVortex__verFiles.dat
@@ -2,28 +2,30 @@
 C "-Wall -cc Vortex.v --exe test_bench.cpp"
 S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
 S      2785 12889457986  1554064009           0  1554064009           0 "VX_alu.v"
-S      3288 12890338917  1557354788           0  1557354788           0 "VX_context.v"
+S      3486 12890338917  1557473618           0  1557473618           0 "VX_context.v"
+S      4928 12890355578  1557474515           0  1557474515           0 "VX_context_slave.v"
 S      1495 12889457987  1554023089           0  1554023089           0 "VX_csr_handler.v"
 S      5512 12889457988  1557345046           0  1557345046           0 "VX_d_e_reg.v"
-S     12085 12890307904  1557354665           0  1557354665           0 "VX_decode.v"
+S     14563 12890307904  1557474495           0  1557474495           0 "VX_decode.v"
 S      1574 12890307906  1557343909           0  1557343909           0 "VX_define.v"
 S      4267 12889457992  1557345117           0  1557345117           0 "VX_e_m_reg.v"
-S      3405 12889457993  1557348460           0  1557348460           0 "VX_execute.v"
+S      3692 12889457993  1557447660           0  1557447660           0 "VX_execute.v"
 S      1751 12889457994  1557344924           0  1557344924           0 "VX_f_d_reg.v"
-S      2362 12890309989  1557358323           0  1557358323           0 "VX_fetch.v"
+S      4619 12890309989  1557474372           0  1557474372           0 "VX_fetch.v"
 S      6293 12889457996  1557348346           0  1557348346           0 "VX_forwarding.v"
 S      1866 12889457997  1557348551           0  1557348551           0 "VX_m_w_reg.v"
-S      3847 12890309990  1557348518           0  1557348518           0 "VX_memory.v"
-S      1118 12889457999  1557354753           0  1557354753           0 "VX_register_file.v"
-S      1428 12889458000  1557354772           0  1557354772           0 "VX_register_file_slave.v"
-S      1499 12890308905  1557267602           0  1557267602           0 "VX_warp.v"
+S      4352 12890309990  1557474440           0  1557474440           0 "VX_memory.v"
+S      1249 12889457999  1557474005           0  1557474005           0 "VX_register_file.v"
+S      1655 12890356143  1557474338           0  1557474338           0 "VX_register_file_master_slave.v"
+S      1599 12889458000  1557474345           0  1557474345           0 "VX_register_file_slave.v"
+S      1686 12890308905  1557474462           0  1557474462           0 "VX_warp.v"
 S      1568 12890307909  1557348531           0  1557348531           0 "VX_writeback.v"
-S     18244 12890307910  1557357447           0  1557357447           0 "Vortex.v"
-T    277561 12890339974  1557358338           0  1557358338           0 "obj_dir/VVortex.cpp"
-T     16771 12890339973  1557358338           0  1557358338           0 "obj_dir/VVortex.h"
-T      1800 12890339976  1557358338           0  1557358338           0 "obj_dir/VVortex.mk"
-T       530 12890339972  1557358338           0  1557358338           0 "obj_dir/VVortex__Syms.cpp"
-T       711 12890339971  1557358338           0  1557358338           0 "obj_dir/VVortex__Syms.h"
-T       512 12890339977  1557358338           0  1557358338           0 "obj_dir/VVortex__ver.d"
-T         0        0  1557358338           0  1557358338           0 "obj_dir/VVortex__verFiles.dat"
-T      1159 12890339975  1557358338           0  1557358338           0 "obj_dir/VVortex_classes.mk"
+S     18714 12890307910  1557368874           0  1557368874           0 "Vortex.v"
+T    451065 12890356589  1557474518           0  1557474518           0 "obj_dir/VVortex.cpp"
+T     20559 12890356588  1557474518           0  1557474518           0 "obj_dir/VVortex.h"
+T      1800 12890356591  1557474518           0  1557474518           0 "obj_dir/VVortex.mk"
+T       530 12890356587  1557474518           0  1557474518           0 "obj_dir/VVortex__Syms.cpp"
+T       711 12890356586  1557474518           0  1557474518           0 "obj_dir/VVortex__Syms.h"
+T       563 12890356592  1557474518           0  1557474518           0 "obj_dir/VVortex__ver.d"
+T         0        0  1557474518           0  1557474518           0 "obj_dir/VVortex__verFiles.dat"
+T      1159 12890356590  1557474518           0  1557474518           0 "obj_dir/VVortex_classes.mk"
diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
index f1593fc629774b1f6b9580f6195a6348fe065a00..05684420663e90c9797e241a14e86a9b1ee4ead8 100644
GIT binary patch
delta 534
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delta 517
zcmX@p#&V{OWy4NxMzzVixTi6yZ4Ts#Vg_>7@W%o<TmmyW83iUUkyK{nnS4TWgT4v_
zf6E^R1_qCA*Bc()9SjW&4BeqGI<IwyY}Dus{eUJUvw69c3L~S+<TKJzj53p-OXo0(
zOb(HW2a;Q4Jb>h185<yJC2Jui@=^lb*e9LWj=O9WncO35z$mhLudEi+<gfA~R+>O{
zh6g$heq;R)1dJWN=lENAfnv?JAU-Sq`~w}X=ek_anf&i?J>TVeegz|cD=Sd`<@(9$
z3gP;OmpU$dbA8R&;d++8g$*d)<@yT9?s7e=!q@>)#{e~$zeNPdnY>v+Lz4k$ut&Eo
zNYbO%bb~ts!wV3*yY!7m=W#F-NCRbRC$lKpZ1zyp@MC<ixiG(80!V#qpRZECQ<i~Y
z5d(wnY9KugNY4P$$AR=@AkECcAleC}UjzAdQ1MErcoC5P%)nq938ZBh7<&C6w5%(X
zwgA#VlxqZ`Wd(rrb)Y%#fQlCY>8C&%$d}YT3S=w<3d{x4K$P1HBtRNBYphiX0|0x(
Bp9=s0

diff --git a/rtl/results.txt b/rtl/results.txt
index dc381a3e..28b5491f 100644
--- a/rtl/results.txt
+++ b/rtl/results.txt
@@ -1,7 +1,7 @@
-# Dynamic Instructions: 122612
-# of total cycles:      122624
+# Dynamic Instructions: 222955
+# of total cycles:      222962
 # of forwarding stalls: 0
 # of branch stalls:     0
-# CPI:                  1.0001
+# CPI:                  1.00003
 # time to simulate:     6.95312e-310 milliseconds
-# GRADE:                Failed on test: 0
+# GRADE:                Failed on test: 4294967295
diff --git a/rtl/test_bench.h b/rtl/test_bench.h
index 7802293f..1d4790a6 100644
--- a/rtl/test_bench.h
+++ b/rtl/test_bench.h
@@ -326,11 +326,12 @@ bool Vortex::simulate(std::string file_to_simulate)
 
     bool istop;
     bool dstop;
-
+    bool cont = false;
     // for (int i = 0; i < 500; i++)
 
     // unsigned cycles;
-    while (this->stop && (!(stop && (counter > 5))))
+    counter = 0;
+    while (this->stop && ((counter < 5)))
     {
 
         // std::cout << "************* Cycle: " << cycle << "\n";
@@ -347,10 +348,12 @@ bool Vortex::simulate(std::string file_to_simulate)
         vortex->eval();
 
 
-        stop = istop && dstop;
+        // stop = istop && dstop;
+        stop = vortex->out_ebreak;
 
-        if (stop)
+        if (stop || cont)
         {
+            cont = true;
             counter++;
         } else
         {