From 48897d9778dfd9e83e85e740754379aa5543413e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 25 Oct 2020 18:29:25 -0700 Subject: [PATCH] minor update --- driver/opae/vlsim/opae_sim.cpp | 9 ++++----- hw/opae/vortex_afu.sv | 37 ++++++++++++++++------------------ 2 files changed, 21 insertions(+), 25 deletions(-) diff --git a/driver/opae/vlsim/opae_sim.cpp b/driver/opae/vlsim/opae_sim.cpp index 8190820f..dfddb482 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/driver/opae/vlsim/opae_sim.cpp @@ -206,11 +206,10 @@ void opae_sim::sRxPort_bus() { vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1; memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_rd_it->block.data(), CACHE_BLOCK_SIZE); vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; - printf("*** [vlsim] read-rsp: addr=%ld, mdata=%d, data=", cci_rd_it->addr, cci_rd_it->mdata); - for (int i = 0; i < CACHE_BLOCK_SIZE; ++i) { + /*printf("*** [vlsim] read-rsp: addr=%ld, mdata=%d, data=", cci_rd_it->addr, cci_rd_it->mdata); + for (int i = 0; i < CACHE_BLOCK_SIZE; ++i) printf("%02x", cci_rd_it->block[CACHE_BLOCK_SIZE-1-i]); - } - printf("\n"); + printf("\n");*/ fflush(stdout); cci_reads_.erase(cci_rd_it); } @@ -226,7 +225,7 @@ void opae_sim::sTxPort_bus() { cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata; auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); memcpy(cci_req.block.data(), host_ptr, CACHE_BLOCK_SIZE); - printf("*** [vlsim] read-req: addr=%ld, mdata=%d\n", vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); + //printf("*** [vlsim] read-req: addr=%ld, mdata=%d\n", vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); fflush(stdout); cci_reads_.emplace_back(cci_req); } diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index c019e54c..41110da1 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -746,7 +746,6 @@ always @(posedge clk) begin cci_rd_req_ctr <= cci_rd_req_ctr_next; if (cci_rd_req_tag == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin cci_rd_req_wait <= 1; // end current request batch - $display("*** %t: CCI Rd Rsp: STOP", $time); end `ifdef DBG_PRINT_OPAE $display("%t: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); @@ -757,7 +756,6 @@ always @(posedge clk) begin cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_RQ_TAGW'(1); if (cci_rd_rsp_ctr == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin cci_rd_req_wait <= 0; // restart new request batch - $display("*** %t: CCI Rd Rsp: START", $time); end `ifdef DBG_PRINT_OPAE $display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr); @@ -789,26 +787,25 @@ VX_generic_queue #( `UNUSED_PIN (size) ); -`DEBUG_BEGIN -reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; -always @(posedge clk) begin - if (reset) begin - dbg_cci_rd_rsp_mask <= 0; - end else begin - if (cci_rd_rsp_fire) begin - if (cci_rd_rsp_ctr == 0) begin - dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); - end else begin - if (dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] != 0) begin - $display("*** %t: Assert: CCI Rd Rsp: idx=%0d, ctr=%0d, mask=%0h, meta=%0h, data=%0h", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, dbg_cci_rd_rsp_mask, cp2af_sRxPort.c0.hdr.mdata, cp2af_sRxPort.c0.data); - assert(0); - end - dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1; - end +`ifdef VERILATOR +`DEBUG_BLOCK( + reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; + always @(posedge clk) begin + if (reset) begin + dbg_cci_rd_rsp_mask <= 0; + end else begin + if (cci_rd_rsp_fire) begin + if (cci_rd_rsp_ctr == 0) begin + dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); + end else begin + assert(!dbg_cci_rd_rsp_mask[cci_rd_rsp_tag]); + dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1; + end + end end end -end -`DEBUG_END +) +`endif // CCI-P Write Request //////////////////////////////////////////////////////////