diff --git a/sim/simx/core.cpp b/sim/simx/core.cpp
index ee0e49ae..6440d4ca 100644
--- a/sim/simx/core.cpp
+++ b/sim/simx/core.cpp
@@ -406,8 +406,8 @@ Word Core::icache_read(Addr addr, Size size) {
   return data;
 }
 
-DoubleWord Core::dcache_read(Addr addr, Size size) {  
-  DoubleWord data;
+DWord Core::dcache_read(Addr addr, Size size) {  
+  DWord data;
   auto type = get_addr_type(addr, size);
   if (type == AddrType::Shared) {
     smem_.read(&data, addr & (SMEM_SIZE-1), size);
@@ -417,7 +417,7 @@ DoubleWord Core::dcache_read(Addr addr, Size size) {
   return data;
 }
 
-void Core::dcache_write(Addr addr, DoubleWord data, Size size) {  
+void Core::dcache_write(Addr addr, DWord data, Size size) {  
   if (addr >= IO_COUT_ADDR 
    && addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
      this->writeToStdOut(addr, data);
diff --git a/sim/simx/core.h b/sim/simx/core.h
index 252f1e3e..1d5a71cf 100644
--- a/sim/simx/core.h
+++ b/sim/simx/core.h
@@ -109,9 +109,9 @@ public:
 
   Word icache_read(Addr, Size);
 
-  DoubleWord dcache_read(Addr, Size);
+  DWord dcache_read(Addr, Size);
 
-  void dcache_write(Addr, DoubleWord, Size);
+  void dcache_write(Addr, DWord, Size);
 
   Word tex_read(uint32_t unit, Word lod, Word u, Word v, std::vector<mem_addr_size_t>* mem_addrs);
 
diff --git a/sim/simx/decode.cpp b/sim/simx/decode.cpp
index c5b0d7e9..7c11ede3 100644
--- a/sim/simx/decode.cpp
+++ b/sim/simx/decode.cpp
@@ -52,7 +52,7 @@ static const char* op_string(const Instr &instr) {
   Word func3  = instr.getFunc3();
   Word func7  = instr.getFunc7();
   Word rs2    = instr.getRSrc(1);
-  DoubleWord imm    = instr.getImm();
+  DWord imm    = instr.getImm();
 
   switch (opcode) {
   case Opcode::NOP:        return "NOP";
@@ -517,7 +517,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
       instr->setSrcReg(rs2);
     }
     instr->setFunc3(func3);
-    DoubleWord imm = (func7 << reg_s_) | rd;
+    DWord imm = (func7 << reg_s_) | rd;
     instr->setImm(sext64(imm, 12));
   } break;
 
@@ -529,7 +529,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
     Word bits_4_1 = rd >> 1;
     Word bit_10_5 = func7 & 0x3f;
     Word bit_12   = func7 >> 6;
-    DoubleWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
+    DWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
     instr->setImm(sext64(imm, 13));
   } break;
 
@@ -545,7 +545,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
     Word bit_11 = (unordered >> 8) & 0x1;
     Word bits_10_1 = (unordered >> 9) & 0x3ff;
     Word bit_20 = (unordered >> 19) & 0x1;
-    DoubleWord imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
+    DWord imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
     if (bit_20) {
       imm |= ~j_imm_mask_;
     }
diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp
index 1cce3105..b591a1b2 100644
--- a/sim/simx/execute.cpp
+++ b/sim/simx/execute.cpp
@@ -16,7 +16,7 @@
 using namespace vortex;
 
 static bool HasDivergentThreads(const ThreadMask &thread_mask,                                
-                                const std::vector<std::vector<DoubleWord>> &reg_file,
+                                const std::vector<std::vector<DWord>> &reg_file,
                                 unsigned reg) {
   bool cond;
   size_t thread_idx = 0;
@@ -52,7 +52,7 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
 void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
   assert(tmask_.any());
 
-  DoubleWord nextPC = PC_ + core_->arch().wsize();
+  DWord nextPC = PC_ + core_->arch().wsize();
 
   Word func2  = instr.getFunc2();
   Word func3  = instr.getFunc3();
@@ -64,13 +64,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
   int rsrc0   = instr.getRSrc(0);
   int rsrc1   = instr.getRSrc(1);
   int rsrc2   = instr.getRSrc(2);
-  DoubleWord immsrc = instr.getImm();
+  DWord immsrc = instr.getImm();
   Word vmask  = instr.getVmask();
 
   int num_threads = core_->arch().num_threads();
 
-  std::vector<DoubleWord[3]> rsdata(num_threads);
-  std::vector<DoubleWord> rddata(num_threads);
+  std::vector<DWord[3]> rsdata(num_threads);
+  std::vector<DWord> rddata(num_threads);
   
   int num_rsrcs = instr.getNRSrc();
   if (num_rsrcs) {              
@@ -149,7 +149,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         switch (func3) {
         case 0:
           // RV32M: MUL
-          rddata[t] = ((DoubleWordI)rsdata[t][0]) * ((DoubleWordI)rsdata[t][1]);
+          rddata[t] = ((DWordI)rsdata[t][0]) * ((DWordI)rsdata[t][1]);
           trace->alu.type = AluType::IMUL;
           break;
         case 1: {
@@ -175,11 +175,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 4: {
           // RV32M: DIV
-          DoubleWordI dividen = rsdata[t][0];
-          DoubleWordI divisor = rsdata[t][1];
+          DWordI dividen = rsdata[t][0];
+          DWordI divisor = rsdata[t][1];
           if (divisor == 0) {
             rddata[t] = -1;
-          } else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
+          } else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
             rddata[t] = dividen;
           } else {
             rddata[t] = dividen / divisor;
@@ -188,8 +188,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 5: {
           // RV32M: DIVU
-          DoubleWord dividen = rsdata[t][0];
-          DoubleWord divisor = rsdata[t][1];
+          DWord dividen = rsdata[t][0];
+          DWord divisor = rsdata[t][1];
           if (divisor == 0) {
             rddata[t] = -1;
           } else {
@@ -199,11 +199,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 6: {
           // RV32M: REM
-          DoubleWordI dividen = rsdata[t][0];
-          DoubleWordI divisor = rsdata[t][1];
+          DWordI dividen = rsdata[t][0];
+          DWordI divisor = rsdata[t][1];
           if (rsdata[t][1] == 0) {
             rddata[t] = dividen;
-          } else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
+          } else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
             rddata[t] = 0;
           } else {
             rddata[t] = dividen % divisor;
@@ -212,8 +212,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         } break;
         case 7: {
           // RV32M: REMU
-          DoubleWord dividen = rsdata[t][0];
-          DoubleWord divisor = rsdata[t][1];
+          DWord dividen = rsdata[t][0];
+          DWord divisor = rsdata[t][1];
           if (rsdata[t][1] == 0) {
             rddata[t] = dividen;
           } else {
@@ -241,11 +241,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           break;
         case 2:
           // RV32I: LT
-          rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1]));
+          rddata[t] = (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1]));
           break;
         case 3:
           // RV32I: LTU
-          rddata[t] = (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1]));
+          rddata[t] = (DWord(rsdata[t][0]) < DWord(rsdata[t][1]));
           break;
         case 4:
           // RV32I: XOR
@@ -254,10 +254,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         case 5:
           if (func7) {
             // RV32I: SRA
-            rddata[t] = DoubleWordI(rsdata[t][0]) >> DoubleWordI(rsdata[t][1]);
+            rddata[t] = DWordI(rsdata[t][0]) >> DWordI(rsdata[t][1]);
           } else {
             // RV32I: SHR
-            rddata[t] = DoubleWord(rsdata[t][0]) >> DoubleWord(rsdata[t][1]);
+            rddata[t] = DWord(rsdata[t][0]) >> DWord(rsdata[t][1]);
           }
           break;
         case 6:
@@ -293,7 +293,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         break;
       case 2:
         // RV32I: SLTI
-        rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(immsrc));
+        rddata[t] = (DWordI(rsdata[t][0]) < DWordI(immsrc));
         break;
       case 3: {
         // RV32I: SLTIU
@@ -306,11 +306,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       case 5:
         if (func7) {
           // RV32I: SRAI
-          DoubleWord result = DoubleWordI(rsdata[t][0]) >> immsrc;
+          DWord result = DWordI(rsdata[t][0]) >> immsrc;
           rddata[t] = result;
         } else {
           // RV32I: SRLI
-          DoubleWord result = rsdata[t][0] >> immsrc;
+          DWord result = rsdata[t][0] >> immsrc;
           rddata[t] = result;
         }
         break;
@@ -439,11 +439,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         case 5:
           if (func7) {
             // RV64I: SRAIW
-            DoubleWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
+            DWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
             rddata[t] = result;
           } else {
             // RV64I: SRLIW
-            DoubleWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
+            DWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
             rddata[t] = result;
           }
           break;
@@ -476,25 +476,25 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         break;
       case 4:
         // RV32I: BLT
-        if (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1])) {
+        if (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 5:
         // RV32I: BGE
-        if (DoubleWordI(rsdata[t][0]) >= DoubleWordI(rsdata[t][1])) {
+        if (DWordI(rsdata[t][0]) >= DWordI(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 6:
         // RV32I: BLTU
-        if (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1])) {
+        if (DWord(rsdata[t][0]) < DWord(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
       case 7:
         // RV32I: BGEU
-        if (DoubleWord(rsdata[t][0]) >= DoubleWord(rsdata[t][1])) {
+        if (DWord(rsdata[t][0]) >= DWord(rsdata[t][1])) {
           nextPC = PC_ + immsrc;
         }
         break;
@@ -542,9 +542,9 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       for (int t = 0; t < num_threads; ++t) {
         if (!tmask_.test(t))
           continue;
-        DoubleWord mem_addr  = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFF8); // double word aligned
-        DoubleWord shift_by  = ((rsdata[t][0] + immsrc) & 0x00000007) * 8;
-        DoubleWord data_read = core_->dcache_read(mem_addr, 8);
+        DWord mem_addr  = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFF8); // double word aligned
+        DWord shift_by  = ((rsdata[t][0] + immsrc) & 0x00000007) * 8;
+        DWord data_read = core_->dcache_read(mem_addr, 8);
         trace->mem_addrs.at(t).push_back({mem_addr, 8});
         DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << data_read);
         switch (func3) {
@@ -566,15 +566,15 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
           break;
         case 4:
           // RV32I: LBU
-          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFF);
+          rddata[t] = DWord((data_read >> shift_by) & 0xFF);
           break;
         case 5:
           // RV32I: LHU
-          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFF);
+          rddata[t] = DWord((data_read >> shift_by) & 0xFFFF);
           break; 
         case 6:
           // RV64I: LWU
-          rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFFFFFF);
+          rddata[t] = DWord((data_read >> shift_by) & 0xFFFFFFFF);
           break;
         default:
           std::abort();      
@@ -615,7 +615,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       for (int t = 0; t < num_threads; ++t) {
         if (!tmask_.test(t))
           continue;
-        DoubleWord mem_addr = rsdata[t][0] + immsrc;
+        DWord mem_addr = rsdata[t][0] + immsrc;
         trace->mem_addrs.at(t).push_back({mem_addr, (1u << func3)});
         DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr);
         switch (func3) {
diff --git a/sim/simx/instr.h b/sim/simx/instr.h
index 1d4c7699..37fa5d44 100644
--- a/sim/simx/instr.h
+++ b/sim/simx/instr.h
@@ -75,7 +75,7 @@ public:
   void setFunc2(Word func2) { func2_ = func2; }
   void setFunc3(Word func3) { func3_ = func3; }
   void setFunc7(Word func7) { func7_ = func7; }
-  void setImm(DoubleWord imm) { has_imm_ = true; imm_ = imm; }
+  void setImm(DWord imm) { has_imm_ = true; imm_ = imm; }
   void setVlsWidth(Word width) { vlsWidth_ = width; }
   void setVmop(Word mop) { vMop_ = mop; }
   void setVnf(Word nf) { vNf_ = nf; }
@@ -98,7 +98,7 @@ public:
   int getRDest() const { return rdest_; }  
   RegType getRDType() const { return rdest_type_; }  
   bool hasImm() const { return has_imm_; }
-  DoubleWord getImm() const { return imm_; }
+  DWord getImm() const { return imm_; }
   Word getVlsWidth() const { return vlsWidth_; }
   Word getVmop() const { return vMop_; }
   Word getvNf() const { return vNf_; }
@@ -118,7 +118,7 @@ private:
   int num_rsrcs_;
   bool has_imm_;
   RegType rdest_type_;
-  DoubleWord imm_;
+  DWord imm_;
   RegType rsrc_type_[MAX_REG_SOURCES];
   int rsrc_[MAX_REG_SOURCES];  
   int rdest_;
diff --git a/sim/simx/pipeline.h b/sim/simx/pipeline.h
index dbd1c972..28810c6c 100644
--- a/sim/simx/pipeline.h
+++ b/sim/simx/pipeline.h
@@ -18,7 +18,7 @@ struct pipeline_trace_t {
   int         cid;
   int         wid;  
   ThreadMask  tmask;
-  DoubleWord        PC;
+  DWord        PC;
 
   //--
   bool        fetch_stall;
diff --git a/sim/simx/types.h b/sim/simx/types.h
index 131f9ee3..1e612d07 100644
--- a/sim/simx/types.h
+++ b/sim/simx/types.h
@@ -13,8 +13,8 @@ namespace vortex {
 typedef uint8_t  Byte;
 typedef uint32_t Word;
 typedef int32_t  WordI;
-typedef uint64_t DoubleWord;
-typedef int64_t DoubleWordI;
+typedef uint64_t DWord;
+typedef int64_t DWordI;
 
 typedef uint64_t Addr;
 typedef uint32_t Size;
diff --git a/sim/simx/warp.cpp b/sim/simx/warp.cpp
index 9fca6595..c684a924 100644
--- a/sim/simx/warp.cpp
+++ b/sim/simx/warp.cpp
@@ -13,8 +13,8 @@ using namespace vortex;
 Warp::Warp(Core *core, Word id)
     : id_(id)
     , core_(core)
-    , ireg_file_(core->arch().num_threads(), std::vector<DoubleWord>(core->arch().num_regs()))
-    , freg_file_(core->arch().num_threads(), std::vector<DoubleWord>(core->arch().num_regs()))
+    , ireg_file_(core->arch().num_threads(), std::vector<DWord>(core->arch().num_regs()))
+    , freg_file_(core->arch().num_threads(), std::vector<DWord>(core->arch().num_regs()))
     , vreg_file_(core->arch().num_threads(), std::vector<Byte>(core->arch().vsize()))
 {
   this->clear();
diff --git a/sim/simx/warp.h b/sim/simx/warp.h
index cfed0933..2a25c92a 100644
--- a/sim/simx/warp.h
+++ b/sim/simx/warp.h
@@ -11,7 +11,7 @@ class Core;
 class Instr;
 class pipeline_trace_t;
 struct DomStackEntry {
-  DomStackEntry(const ThreadMask &tmask, DoubleWord PC) 
+  DomStackEntry(const ThreadMask &tmask, DWord PC) 
     : tmask(tmask)
     , PC(PC)
     , fallThrough(false)
@@ -26,7 +26,7 @@ struct DomStackEntry {
   {}
 
   ThreadMask tmask;
-  DoubleWord PC;
+  DWord PC;
   bool fallThrough;
   bool unanimous;
 };
@@ -66,11 +66,11 @@ public:
     return id_;
   }
 
-  DoubleWord getPC() const {
+  DWord getPC() const {
     return PC_;
   }
 
-  void setPC(DoubleWord PC) {
+  void setPC(DWord PC) {
     PC_ = PC;
   }
 
@@ -99,11 +99,11 @@ private:
   Core *core_;
   bool active_;
   
-  DoubleWord PC_;
+  DWord PC_;
   ThreadMask tmask_;  
   
-  std::vector<std::vector<DoubleWord>> ireg_file_;
-  std::vector<std::vector<DoubleWord>> freg_file_;
+  std::vector<std::vector<DWord>> ireg_file_;
+  std::vector<std::vector<DWord>> freg_file_;
   std::vector<std::vector<Byte>> vreg_file_;
   std::stack<DomStackEntry> dom_stack_;