From 505bbc20c8a15643b720e98cdbd491d4f47160b0 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 18 Oct 2019 02:01:39 -0400 Subject: [PATCH] Removed FWD --- rtl/VX_back_end.v | 86 --------- rtl/VX_decode.v | 56 ------ rtl/VX_execute_unit.v | 9 - rtl/VX_fetch.v | 3 +- rtl/VX_forwarding.v | 179 ------------------ rtl/VX_front_end.v | 10 +- rtl/VX_gpr_stage.v | 15 +- rtl/VX_gpr_wrapper.v | 8 +- rtl/VX_lsu.v | 12 -- rtl/VX_writeback.v | 8 - rtl/Vortex.v | 26 --- .../VX_forward_csr_response_inter.v | 14 -- rtl/interfaces/VX_forward_exe_inter.v | 19 -- rtl/interfaces/VX_forward_mem_inter.v | 20 -- rtl/interfaces/VX_forward_reqeust_inter.v | 18 -- rtl/interfaces/VX_forward_response_inter.v | 18 -- rtl/interfaces/VX_forward_wb_inter.v | 21 -- rtl/pipe_regs/VX_d_e_reg.v | 3 +- rtl/pipe_regs/VX_f_d_reg.v | 3 +- syn/syn.tcl | 2 +- 20 files changed, 9 insertions(+), 521 deletions(-) delete mode 100644 rtl/VX_forwarding.v delete mode 100644 rtl/interfaces/VX_forward_csr_response_inter.v delete mode 100644 rtl/interfaces/VX_forward_exe_inter.v delete mode 100644 rtl/interfaces/VX_forward_mem_inter.v delete mode 100644 rtl/interfaces/VX_forward_reqeust_inter.v delete mode 100644 rtl/interfaces/VX_forward_response_inter.v delete mode 100644 rtl/interfaces/VX_forward_wb_inter.v diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index f401d07e..b0a64d33 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -6,7 +6,6 @@ module VX_back_end ( input wire[31:0] csr_decode_csr_data, output wire execute_branch_stall, - input wire in_fwd_stall, output wire out_mem_delay, output wire out_gpr_stall, @@ -23,13 +22,6 @@ module VX_back_end ( VX_dcache_response_inter VX_dcache_rsp, VX_dcache_request_inter VX_dcache_req, - VX_forward_reqeust_inter VX_fwd_req_de, - VX_forward_response_inter VX_fwd_rsp, - - VX_forward_exe_inter VX_fwd_exe, - VX_forward_mem_inter VX_fwd_mem, - VX_forward_wb_inter VX_fwd_wb, - VX_csr_write_request_inter VX_csr_w_req ); @@ -74,13 +66,10 @@ VX_gpr_stage VX_gpr_stage( .clk (clk), .schedule_delay (schedule_delay), .VX_writeback_inter(VX_writeback_inter), - .VX_fwd_rsp (VX_fwd_rsp), - .in_fwd_stall (in_fwd_stall), .VX_bckE_req (VX_bckE_req), .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req_out (VX_bckE_req_out), .VX_gpr_data (VX_gpr_data), - .VX_fwd_req_de (VX_fwd_req_de), .out_gpr_stall (out_gpr_stall) ); @@ -97,7 +86,6 @@ VX_lsu load_store_unit( // .clk (clk), .VX_lsu_req (VX_lsu_req), .VX_mem_wb (VX_mem_wb), - .VX_fwd_mem (VX_fwd_mem), .VX_dcache_rsp(VX_dcache_rsp), .VX_dcache_req(VX_dcache_req), .out_delay (memory_delay) @@ -111,7 +99,6 @@ VX_execute_unit VX_execUnit( .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), - .VX_fwd_exe (VX_fwd_exe), .in_csr_data (csr_decode_csr_data), .out_csr_address (VX_csr_w_req.csr_address), .out_is_csr (VX_csr_w_req.is_csr), @@ -123,80 +110,7 @@ VX_writeback VX_wb( .VX_mem_wb (VX_mem_wb), .VX_inst_exec_wb (VX_inst_exec_wb), - .VX_fwd_wb (VX_fwd_wb), .VX_writeback_inter(VX_writeback_inter) ); -// VX_execute vx_execute( -// .VX_bckE_req (VX_bckE_req_out), -// .VX_gpr_data (VX_gpr_data), -// .VX_fwd_exe (VX_fwd_exe), -// .in_csr_data (csr_decode_csr_data), - -// .VX_exe_mem_req (VX_exe_mem_req), -// .out_csr_address (execute_csr_address), -// .out_is_csr (execute_is_csr), -// .out_csr_result (execute_csr_result), -// .out_jal (execute_jal), -// .out_jal_dest (execute_jal_dest), -// .out_branch_stall (execute_branch_stall) -// ); - - -// assign VX_jal_rsp.jal_warp_num = VX_mem_req.warp_num; - -// VX_e_m_reg vx_e_m_reg( -// .clk (clk), -// .reset (reset), -// .in_csr_address (execute_csr_address), -// .in_is_csr (execute_is_csr), -// .in_csr_result (execute_csr_result), -// .in_jal (execute_jal), -// .in_jal_dest (execute_jal_dest), -// .in_freeze (total_freeze), -// .VX_exe_mem_req (VX_exe_mem_req), - -// .VX_mem_req (VX_mem_req), -// .out_csr_address (VX_csr_w_req.csr_address), -// .out_is_csr (VX_csr_w_req.is_csr), -// .out_csr_result (VX_csr_w_req.csr_result), -// .out_jal (VX_jal_rsp.jal), -// .out_jal_dest (VX_jal_rsp.jal_dest) -// ); - -// VX_memory vx_memory( -// .VX_mem_req (VX_mem_req), -// .VX_mem_wb (VX_mem_wb), -// .VX_fwd_mem (VX_fwd_mem), -// .out_delay (memory_delay), - -// .VX_branch_rsp (VX_branch_rsp), - -// .VX_dcache_rsp(VX_dcache_rsp), -// .VX_dcache_req (VX_dcache_req) -// ); - -// // VX_m_w_reg vx_m_w_reg( -// // .clk (clk), -// // .reset (reset), -// // .in_freeze (total_freeze), -// // .VX_mem_wb (VX_mem_wb), -// // .VX_mw_wb (VX_mw_wb) -// // ); - -// assign VX_mw_wb.alu_result = VX_mem_wb.alu_result; -// assign VX_mw_wb.mem_result = VX_mem_wb.mem_result; -// assign VX_mw_wb.rd = VX_mem_wb.rd; -// assign VX_mw_wb.wb = VX_mem_wb.wb; -// assign VX_mw_wb.PC_next = VX_mem_wb.PC_next; -// assign VX_mw_wb.valid = VX_mem_wb.valid; -// assign VX_mw_wb.warp_num = VX_mem_wb.warp_num; - - -// VX_writeback vx_writeback( -// .VX_mw_wb (VX_mw_wb), -// .VX_fwd_wb (VX_fwd_wb), -// .VX_writeback_inter(VX_writeback_inter) -// ); - endmodule \ No newline at end of file diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index d14b82b8..01a717a0 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -5,18 +5,6 @@ module VX_decode( // Fetch Inputs VX_inst_meta_inter fd_inst_meta_de, - // WriteBack inputs - // VX_wb_inter VX_writeback_inter, - - - // Fwd Request - // VX_forward_reqeust_inter VX_fwd_req_de, - - // FORWARDING INPUTS - // VX_forward_response_inter VX_fwd_rsp, - - // input wire[`NW_M1:0] in_which_wspawn, - // Outputs VX_frE_to_bckE_req_inter VX_frE_to_bckE_req, output reg out_gpr_stall, @@ -91,50 +79,6 @@ module VX_decode( reg[4:0] mul_alu; - - // assign VX_fwd_req_de.src1 = VX_frE_to_bckE_req.rs1; - // assign VX_fwd_req_de.src2 = VX_frE_to_bckE_req.rs2; - // assign VX_fwd_req_de.warp_num = VX_frE_to_bckE_req.warp_num; - - - // VX_gpr_read_inter VX_gpr_read(); - // assign VX_gpr_read.rs1 = VX_frE_to_bckE_req.rs1; - // assign VX_gpr_read.rs2 = VX_frE_to_bckE_req.rs2; - // assign VX_gpr_read.warp_num = VX_frE_to_bckE_req.warp_num; - - // VX_gpr_jal_inter VX_gpr_jal(); - // assign VX_gpr_jal.is_jal = is_jal; - // assign VX_gpr_jal.curr_PC = in_curr_PC; - - - // VX_gpr_clone_inter VX_gpr_clone(); - // assign VX_gpr_clone.is_clone = is_clone; - // assign VX_gpr_clone.warp_num = VX_frE_to_bckE_req.warp_num; - - - // VX_gpr_wspawn_inter VX_gpr_wspawn(); - // assign VX_gpr_wspawn.is_wspawn = is_wspawn; - // assign VX_gpr_wspawn.which_wspawn = in_which_wspawn; - // // assign VX_gpr_wspawn.warp_num = VX_frE_to_bckE_req.warp_num; - - // VX_gpr_wrapper vx_grp_wrapper( - // .clk (clk), - // .VX_writeback_inter(VX_writeback_inter), - // .VX_fwd_rsp (VX_fwd_rsp), - // .VX_gpr_read (VX_gpr_read), - // .VX_gpr_jal (VX_gpr_jal), - // .VX_gpr_clone (VX_gpr_clone), - // .VX_gpr_wspawn (VX_gpr_wspawn), - - // .out_a_reg_data (VX_frE_to_bckE_req.a_reg_data), - // .out_b_reg_data (VX_frE_to_bckE_req.b_reg_data), - // .out_gpr_stall(out_gpr_stall) - // ); - - - - - assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid; assign VX_frE_to_bckE_req.warp_num = in_warp_num; diff --git a/rtl/VX_execute_unit.v b/rtl/VX_execute_unit.v index a2929235..e4ac5bf2 100644 --- a/rtl/VX_execute_unit.v +++ b/rtl/VX_execute_unit.v @@ -11,9 +11,6 @@ module VX_execute_unit ( VX_jal_response_inter VX_jal_rsp, // Branch Response VX_branch_response_inter VX_branch_rsp, - // Forward data - VX_forward_exe_inter VX_fwd_exe, - input wire[31:0] in_csr_data, output wire[11:0] out_csr_address, @@ -24,12 +21,6 @@ module VX_execute_unit ( ); - assign VX_fwd_exe.dest = 0; - assign VX_fwd_exe.wb = 0; - assign VX_fwd_exe.alu_result = 0; - assign VX_fwd_exe.PC_next = 0; - assign VX_fwd_exe.warp_num = 0; - wire[`NT_M1:0][31:0] in_a_reg_data; diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index f5525be6..676edd94 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -5,7 +5,6 @@ module VX_fetch ( input wire clk, input wire in_memory_delay, input wire in_branch_stall, - input wire in_fwd_stall, input wire in_branch_stall_exe, input wire in_gpr_stall, input wire schedule_delay, @@ -29,7 +28,7 @@ module VX_fetch ( wire warp_stall; - assign pipe_stall = in_gpr_stall || in_fwd_stall || in_freeze || schedule_delay; + assign pipe_stall = in_gpr_stall || in_freeze || schedule_delay; assign warp_stall = in_branch_stall || (in_branch_stall_exe && 0); diff --git a/rtl/VX_forwarding.v b/rtl/VX_forwarding.v deleted file mode 100644 index 3d84e7f6..00000000 --- a/rtl/VX_forwarding.v +++ /dev/null @@ -1,179 +0,0 @@ - -`include "VX_define.v" - -module VX_forwarding ( - // INFO FROM DECODE - VX_forward_reqeust_inter VX_fwd_req_de, - VX_forward_exe_inter VX_fwd_exe, - VX_forward_mem_inter VX_fwd_mem, - VX_forward_wb_inter VX_fwd_wb, - - VX_forward_response_inter VX_fwd_rsp, - output wire out_fwd_stall - ); - - - wire[4:0] in_decode_src1 = VX_fwd_req_de.src1; - wire[4:0] in_decode_src2 = VX_fwd_req_de.src2; - wire[`NW_M1:0] in_decode_warp_num = VX_fwd_req_de.warp_num; - - wire[4:0] in_execute_dest = VX_fwd_exe.dest; - wire[1:0] in_execute_wb = VX_fwd_exe.wb; - wire[`NT_M1:0][31:0] in_execute_alu_result = VX_fwd_exe.alu_result; - wire[31:0] in_execute_PC_next = VX_fwd_exe.PC_next; - wire[`NW_M1:0] in_execute_warp_num = VX_fwd_exe.warp_num; - - wire[4:0] in_memory_dest = VX_fwd_mem.dest; - wire[1:0] in_memory_wb = VX_fwd_mem.wb; - wire[`NT_M1:0][31:0] in_memory_alu_result = VX_fwd_mem.alu_result; - wire[`NT_M1:0][31:0] in_memory_mem_data = VX_fwd_mem.mem_data; - wire[31:0] in_memory_PC_next = VX_fwd_mem.PC_next; - wire[`NW_M1:0] in_memory_warp_num = VX_fwd_mem.warp_num; - - wire[4:0] in_writeback_dest = VX_fwd_wb.dest; - wire[1:0] in_writeback_wb = VX_fwd_wb.wb; - wire[`NT_M1:0][31:0] in_writeback_alu_result = VX_fwd_wb.alu_result; - wire[`NT_M1:0][31:0] in_writeback_mem_data = VX_fwd_wb.mem_data; - wire[31:0] in_writeback_PC_next = VX_fwd_wb.PC_next; - wire[`NW_M1:0] in_writeback_warp_num = VX_fwd_wb.warp_num; - - - wire out_src1_fwd; - wire out_src2_fwd; - wire[`NT_M1:0][31:0] out_src1_fwd_data; - wire[`NT_M1:0][31:0] out_src2_fwd_data; - - - assign VX_fwd_rsp.src1_fwd = out_src1_fwd; - assign VX_fwd_rsp.src2_fwd = out_src2_fwd; - assign VX_fwd_rsp.src1_fwd_data = out_src1_fwd_data; - assign VX_fwd_rsp.src2_fwd_data = out_src2_fwd_data; - - - - - wire exe_mem_read; - wire mem_mem_read; - wire wb_mem_read ; - wire exe_jal; - wire mem_jal; - wire wb_jal ; - wire src1_exe_fwd; - wire src1_mem_fwd; - wire src1_wb_fwd; - wire src2_exe_fwd; - wire src2_mem_fwd; - wire src2_wb_fwd; - - wire[`NT_M1:0][31:0] use_execute_PC_next; - wire[`NT_M1:0][31:0] use_memory_PC_next; - wire[`NT_M1:0][31:0] use_writeback_PC_next; - - - genvar index; - generate - for (index=0; index < `NT; index=index+1) - begin: gen_code_label - assign use_execute_PC_next[index] = in_execute_PC_next; - assign use_memory_PC_next[index] = in_memory_PC_next; - assign use_writeback_PC_next[index] = in_writeback_PC_next; - end - endgenerate - - - assign exe_mem_read = (in_execute_wb == `WB_MEM); - assign mem_mem_read = (in_memory_wb == `WB_MEM); - assign wb_mem_read = (in_writeback_wb == `WB_MEM); - - assign exe_jal = (in_execute_wb == `WB_JAL); - assign mem_jal = (in_memory_wb == `WB_JAL); - assign wb_jal = (in_writeback_wb == `WB_JAL); - - - - // SRC1 - assign src1_exe_fwd = ((in_decode_src1 == in_execute_dest) && - (in_decode_src1 != `ZERO_REG) && - (in_execute_wb != `NO_WB)) && - (in_decode_warp_num == in_execute_warp_num); - - assign src1_mem_fwd = ((in_decode_src1 == in_memory_dest) && - (in_decode_src1 != `ZERO_REG) && - (in_memory_wb != `NO_WB) && - (!src1_exe_fwd)) && - (in_decode_warp_num == in_memory_warp_num); - - assign src1_wb_fwd = ((in_decode_src1 == in_writeback_dest) && - (in_decode_src1 != `ZERO_REG) && - (in_writeback_wb != `NO_WB) && - (in_writeback_warp_num == in_decode_warp_num) && - (!src1_exe_fwd) && - (!src1_mem_fwd)); - - - // assign out_src1_fwd = src1_exe_fwd || src1_mem_fwd || (src1_wb_fwd && 0); - assign out_src1_fwd = 0; - - - - - - // SRC2 - assign src2_exe_fwd = ((in_decode_src2 == in_execute_dest) && - (in_decode_src2 != `ZERO_REG) && - (in_execute_wb != `NO_WB)) && - (in_decode_warp_num == in_execute_warp_num); - - assign src2_mem_fwd = ((in_decode_src2 == in_memory_dest) && - (in_decode_src2 != `ZERO_REG) && - (in_memory_wb != `NO_WB) && - (!src2_exe_fwd)) && - (in_decode_warp_num == in_memory_warp_num); - - assign src2_wb_fwd = ((in_decode_src2 == in_writeback_dest) && - (in_decode_src2 != `ZERO_REG) && - (in_writeback_wb != `NO_WB) && - (!src2_exe_fwd) && - (!src2_mem_fwd)) && - (in_writeback_warp_num == in_decode_warp_num); - - - // assign out_src2_fwd = src2_exe_fwd || src2_mem_fwd || (src2_wb_fwd && 0); - assign out_src2_fwd = 0; - - - - - // wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL; - // wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL; - wire exe_mem_read_stall = `NO_STALL; - wire mem_mem_read_stall = `NO_STALL; - - // assign out_fwd_stall = exe_mem_read_stall || mem_mem_read_stall; - assign out_fwd_stall = 0; - - // always @(*) begin - // if (out_fwd_stall) $display("FWD STALL"); - // end - - assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) : - (src1_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : - ( src1_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : - in_execute_alu_result; // last one should be deadbeef - - assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? use_execute_PC_next : in_execute_alu_result) : - (src2_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : - ( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) : - in_execute_alu_result; // last one should be deadbeef - - - - -endmodule // VX_forwarding - - - - - - - diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index 60f26ea0..01aa9e81 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -4,7 +4,6 @@ module VX_front_end ( input wire clk, input wire reset, - input wire forwarding_fwd_stall, input wire memory_delay, input wire execute_branch_stall, @@ -48,7 +47,6 @@ VX_fetch vx_fetch( .clk (clk), .in_memory_delay (memory_delay), .in_branch_stall (decode_branch_stall), - .in_fwd_stall (forwarding_fwd_stall), .schedule_delay (schedule_delay), .in_branch_stall_exe(execute_branch_stall), .in_gpr_stall (decode_gpr_stall), @@ -66,7 +64,6 @@ VX_fetch vx_fetch( VX_f_d_reg vx_f_d_reg( .clk (clk), .reset (reset), - .in_fwd_stall (forwarding_fwd_stall), .in_freeze (total_freeze), .in_gpr_stall (decode_gpr_stall), .fe_inst_meta_fd(fe_inst_meta_fd), @@ -82,16 +79,11 @@ VX_decode vx_decode( .out_ebreak (fetch_ebreak) ); -wire special_what = total_freeze || forwarding_fwd_stall; - -wire temp_fwd_stall = 0; - VX_d_e_reg vx_d_e_reg( .clk (clk), .reset (reset), - .in_fwd_stall (temp_fwd_stall), .in_branch_stall(execute_branch_stall), - .in_freeze (special_what), + .in_freeze (total_freeze), .in_gpr_stall (decode_gpr_stall), .VX_frE_to_bckE_req(VX_frE_to_bckE_req), .VX_bckE_req (VX_bckE_req) diff --git a/rtl/VX_gpr_stage.v b/rtl/VX_gpr_stage.v index 549c33f4..43fbe717 100644 --- a/rtl/VX_gpr_stage.v +++ b/rtl/VX_gpr_stage.v @@ -1,21 +1,16 @@ module VX_gpr_stage ( input wire clk, - input wire in_fwd_stall, input wire schedule_delay, // inputs // Instruction Information VX_frE_to_bckE_req_inter VX_bckE_req, // WriteBack inputs VX_wb_inter VX_writeback_inter, - // FORWARDING INPUTS - VX_forward_response_inter VX_fwd_rsp, // Outputs - // Fwd Request - VX_forward_reqeust_inter VX_fwd_req_de, // Warp Control VX_warp_ctl_inter VX_warp_ctl, // Original Request 1 cycle later @@ -32,11 +27,6 @@ module VX_gpr_stage ( wire jalQual = VX_bckE_req.jalQual; - - assign VX_fwd_req_de.src1 = VX_bckE_req.rs1; - assign VX_fwd_req_de.src2 = VX_bckE_req.rs2; - assign VX_fwd_req_de.warp_num = VX_bckE_req.warp_num; - VX_gpr_read_inter VX_gpr_read(); assign VX_gpr_read.rs1 = VX_bckE_req.rs1; assign VX_gpr_read.rs2 = VX_bckE_req.rs2; @@ -53,7 +43,6 @@ module VX_gpr_stage ( VX_gpr_wrapper vx_grp_wrapper( .clk (clk), .VX_writeback_inter(VX_writeback_inter), - .VX_fwd_rsp (VX_fwd_rsp), .VX_gpr_read (VX_gpr_read), .VX_gpr_jal (VX_gpr_jal), @@ -77,13 +66,11 @@ module VX_gpr_stage ( .out ({VX_gpr_data.a_reg_data, VX_gpr_data.b_reg_data}) ); - wire stall = in_fwd_stall || schedule_delay; VX_d_e_reg gpr_stage_reg( .clk (clk), .reset (zero_temp), - .in_fwd_stall (stall), - .in_branch_stall (zero_temp), + .in_branch_stall (schedule_delay), .in_freeze (zero_temp), .in_gpr_stall (out_gpr_stall), .VX_frE_to_bckE_req(VX_bckE_req), diff --git a/rtl/VX_gpr_wrapper.v b/rtl/VX_gpr_wrapper.v index 3f752925..47c666c6 100644 --- a/rtl/VX_gpr_wrapper.v +++ b/rtl/VX_gpr_wrapper.v @@ -3,9 +3,7 @@ module VX_gpr_wrapper ( input wire clk, VX_gpr_read_inter VX_gpr_read, - VX_wb_inter VX_writeback_inter, - VX_forward_response_inter VX_fwd_rsp, - + VX_wb_inter VX_writeback_inter, VX_gpr_jal_inter VX_gpr_jal, output wire[`NT_M1:0][31:0] out_a_reg_data, @@ -22,8 +20,8 @@ module VX_gpr_wrapper ( for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC; - assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (VX_fwd_rsp.src1_fwd ? VX_fwd_rsp.src1_fwd_data : temp_a_reg_data[VX_gpr_read.warp_num])); - assign out_b_reg_data = (VX_fwd_rsp.src2_fwd ? VX_fwd_rsp.src2_fwd_data : temp_b_reg_data[VX_gpr_read.warp_num]); + assign out_a_reg_data = (VX_gpr_jal.is_jal ? jal_data : (temp_a_reg_data[VX_gpr_read.warp_num])); + assign out_b_reg_data = (temp_b_reg_data[VX_gpr_read.warp_num]); genvar warp_index; generate diff --git a/rtl/VX_lsu.v b/rtl/VX_lsu.v index 82e0c586..fdd1afb5 100644 --- a/rtl/VX_lsu.v +++ b/rtl/VX_lsu.v @@ -9,10 +9,6 @@ module VX_lsu ( // Write back to GPR VX_inst_mem_wb_inter VX_mem_wb, - // FWD info - VX_forward_mem_inter VX_fwd_mem, - - VX_dcache_response_inter VX_dcache_rsp, VX_dcache_request_inter VX_dcache_req, output wire out_delay @@ -64,14 +60,6 @@ module VX_lsu ( // .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num }) // ); - // Delete - assign VX_fwd_mem.dest = 0; - assign VX_fwd_mem.wb = 0; - assign VX_fwd_mem.alu_result = 0; - assign VX_fwd_mem.mem_data = 0; - assign VX_fwd_mem.PC_next = 0; - assign VX_fwd_mem.warp_num = 0; - endmodule // Memory diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v index b7793bd3..2d0e2b6d 100644 --- a/rtl/VX_writeback.v +++ b/rtl/VX_writeback.v @@ -8,18 +8,10 @@ module VX_writeback ( // EXEC Unit WB info VX_inst_exec_wb_inter VX_inst_exec_wb, - VX_forward_wb_inter VX_fwd_wb, // Actual WB to GPR VX_wb_inter VX_writeback_inter ); - assign VX_fwd_wb.dest = 0; - assign VX_fwd_wb.wb = 0; - assign VX_fwd_wb.alu_result = 0; - assign VX_fwd_wb.mem_data = 0; - assign VX_fwd_wb.PC_next = 0; - assign VX_fwd_wb.warp_num = 0; - wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid); diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 73281b14..63de5349 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -53,16 +53,6 @@ VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch wire execute_branch_stall; wire memory_delay; -// Forwarding Buses -VX_forward_reqeust_inter VX_fwd_req_de(); // Forward request -VX_forward_response_inter VX_fwd_rsp(); // Forward Response -VX_forward_exe_inter VX_fwd_exe(); // Data available in EXE -VX_forward_mem_inter VX_fwd_mem(); // Data available in MEM -VX_forward_wb_inter VX_fwd_wb(); // Data available in WB -wire forwarding_fwd_stall; - - - // CSR Buses VX_csr_write_request_inter VX_csr_w_req(); wire[31:0] csr_decode_csr_data; @@ -80,7 +70,6 @@ VX_front_end vx_front_end( .clk (clk), .reset (reset), .VX_warp_ctl (VX_warp_ctl), - .forwarding_fwd_stall(forwarding_fwd_stall), .execute_branch_stall(execute_branch_stall), .VX_bckE_req (VX_bckE_req), .decode_csr_address (decode_csr_address), @@ -107,35 +96,20 @@ VX_back_end vx_back_end( .reset (reset), .schedule_delay (schedule_delay), .fetch_delay (fetch_delay), - .in_fwd_stall (forwarding_fwd_stall), - .VX_fwd_req_de (VX_fwd_req_de), - .VX_fwd_rsp (VX_fwd_rsp), .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req (VX_bckE_req), - .VX_fwd_exe (VX_fwd_exe), .csr_decode_csr_data (csr_decode_csr_data), .execute_branch_stall(execute_branch_stall), .VX_jal_rsp (VX_jal_rsp), .VX_branch_rsp (VX_branch_rsp), .VX_dcache_rsp (VX_dcache_rsp), .VX_dcache_req (VX_dcache_req), - .VX_fwd_mem (VX_fwd_mem), - .VX_fwd_wb (VX_fwd_wb), .VX_csr_w_req (VX_csr_w_req), .VX_writeback_inter (VX_writeback_inter), .out_mem_delay (memory_delay), .out_gpr_stall (out_gpr_stall) ); -VX_forwarding vx_forwarding( - .VX_fwd_req_de(VX_fwd_req_de), - .VX_fwd_exe (VX_fwd_exe), - .VX_fwd_mem (VX_fwd_mem), - .VX_fwd_wb (VX_fwd_wb), - .VX_fwd_rsp (VX_fwd_rsp), - .out_fwd_stall(forwarding_fwd_stall) - ); - VX_csr_handler vx_csr_handler( .clk (clk), .in_decode_csr_address(decode_csr_address), diff --git a/rtl/interfaces/VX_forward_csr_response_inter.v b/rtl/interfaces/VX_forward_csr_response_inter.v deleted file mode 100644 index 8f196acb..00000000 --- a/rtl/interfaces/VX_forward_csr_response_inter.v +++ /dev/null @@ -1,14 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_CSR_RSP - -`define VX_FWD_CSR_RSP - -interface VX_forward_csr_response_inter (); - wire csr_fwd; - wire[31:0] csr_fwd_data; -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_forward_exe_inter.v b/rtl/interfaces/VX_forward_exe_inter.v deleted file mode 100644 index 7a68b69f..00000000 --- a/rtl/interfaces/VX_forward_exe_inter.v +++ /dev/null @@ -1,19 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_EXE - -`define VX_FWD_EXE - -interface VX_forward_exe_inter (); - - wire[4:0] dest; - wire[1:0] wb; - wire[`NT_M1:0][31:0] alu_result; - wire[31:0] PC_next; - wire[`NW_M1:0] warp_num; - -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_forward_mem_inter.v b/rtl/interfaces/VX_forward_mem_inter.v deleted file mode 100644 index 1241fd8d..00000000 --- a/rtl/interfaces/VX_forward_mem_inter.v +++ /dev/null @@ -1,20 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_MEM - -`define VX_FWD_MEM - -interface VX_forward_mem_inter (); - - wire[4:0] dest; - wire[1:0] wb; - wire[`NT_M1:0][31:0] alu_result; - wire[`NT_M1:0][31:0] mem_data; - wire[31:0] PC_next; - wire[`NW_M1:0] warp_num; - -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_forward_reqeust_inter.v b/rtl/interfaces/VX_forward_reqeust_inter.v deleted file mode 100644 index ddb6bb82..00000000 --- a/rtl/interfaces/VX_forward_reqeust_inter.v +++ /dev/null @@ -1,18 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_REQ - -`define VX_FWD_REQ - -interface VX_forward_reqeust_inter (); - - wire[4:0] src1; - wire[4:0] src2; - wire[`NW_M1:0] warp_num; - - -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_forward_response_inter.v b/rtl/interfaces/VX_forward_response_inter.v deleted file mode 100644 index a2170b99..00000000 --- a/rtl/interfaces/VX_forward_response_inter.v +++ /dev/null @@ -1,18 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_RSP - -`define VX_FWD_RSP - -interface VX_forward_response_inter (); - - wire src1_fwd; - wire src2_fwd; - wire[`NT_M1:0][31:0] src1_fwd_data; - wire[`NT_M1:0][31:0] src2_fwd_data; - -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/interfaces/VX_forward_wb_inter.v b/rtl/interfaces/VX_forward_wb_inter.v deleted file mode 100644 index 8e6307fc..00000000 --- a/rtl/interfaces/VX_forward_wb_inter.v +++ /dev/null @@ -1,21 +0,0 @@ - -`include "../VX_define.v" - -`ifndef VX_FWD_WB - -`define VX_FWD_WB - -interface VX_forward_wb_inter (); - - wire[4:0] dest; - wire[1:0] wb; - wire[`NT_M1:0][31:0] alu_result; - wire[`NT_M1:0][31:0] mem_data; - wire[31:0] PC_next; - wire[`NW_M1:0] warp_num; - - -endinterface - - -`endif \ No newline at end of file diff --git a/rtl/pipe_regs/VX_d_e_reg.v b/rtl/pipe_regs/VX_d_e_reg.v index da1999fa..89f11eee 100644 --- a/rtl/pipe_regs/VX_d_e_reg.v +++ b/rtl/pipe_regs/VX_d_e_reg.v @@ -5,7 +5,6 @@ module VX_d_e_reg ( input wire clk, input wire reset, - input wire in_fwd_stall, input wire in_branch_stall, input wire in_freeze, input wire in_gpr_stall, @@ -17,7 +16,7 @@ module VX_d_e_reg ( wire stall = in_freeze; - wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_gpr_stall == `STALL); + wire flush = (in_branch_stall == `STALL) || (in_gpr_stall == `STALL); VX_generic_register #(.N(237)) d_e_reg diff --git a/rtl/pipe_regs/VX_f_d_reg.v b/rtl/pipe_regs/VX_f_d_reg.v index ed6888a9..8d802268 100644 --- a/rtl/pipe_regs/VX_f_d_reg.v +++ b/rtl/pipe_regs/VX_f_d_reg.v @@ -3,7 +3,6 @@ module VX_f_d_reg ( input wire clk, input wire reset, - input wire in_fwd_stall, input wire in_freeze, input wire in_gpr_stall, @@ -13,7 +12,7 @@ module VX_f_d_reg ( ); wire flush = 1'b0; - wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_gpr_stall; + wire stall = in_freeze == 1'b1 || in_gpr_stall; diff --git a/syn/syn.tcl b/syn/syn.tcl index 0b224cab..e6046856 100755 --- a/syn/syn.tcl +++ b/syn/syn.tcl @@ -3,7 +3,7 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_ set symbol_library {} set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] -set verilog_files [ list VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_forwarding.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_csr_write_request_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_forward_csr_response_inter.v VX_forward_exe_inter.v VX_forward_mem_inter.v VX_forward_reqeust_inter.v VX_forward_response_inter.v VX_forward_wb_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ +set verilog_files [ list VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp.v VX_warp_scheduler.v VX_writeback.v Vortex.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_csr_write_request_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ ] analyze -format sverilog $verilog_files