diff --git a/Makefile b/Makefile index 6ce9408d..859c597d 100644 --- a/Makefile +++ b/Makefile @@ -1,14 +1,13 @@ - all: $(MAKE) -C hw + $(MAKE) -C sim $(MAKE) -C driver $(MAKE) -C runtime - $(MAKE) -C simX $(MAKE) -C tests clean: $(MAKE) -C hw clean + $(MAKE) -C sim clean $(MAKE) -C driver clean - $(MAKE) -C simX clean $(MAKE) -C runtime clean $(MAKE) -C tests clean \ No newline at end of file diff --git a/README.md b/README.md index 4f2c5eff..76bbd380 100644 --- a/README.md +++ b/README.md @@ -24,11 +24,11 @@ Vortex is a full-system RISCV-based GPGPU processor. - `hw`: Hardware sources. -- `driver`: Host driver software. +- `driver`: Host drivers repository. - `runtime`: Kernel Runtime software. -- `simX`: Cycle-approximate simulator. +- `sim`: Simulators repository. - `tests`: Tests repository. diff --git a/ci/blackbox.sh b/ci/blackbox.sh index be5ce2a4..38bc5405 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -88,28 +88,18 @@ done case $DRIVER in rtlsim) DRIVER_PATH=$VORTEX_HOME/driver/rtlsim - DRIVER_EXTRA= - CLEAN_TOKEN=clean ;; vlsim) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=vlsim - CLEAN_TOKEN=clean-vlsim + DRIVER_PATH=$VORTEX_HOME/driver/vlsim ;; asesim) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=asesim - CLEAN_TOKEN=clean-asesim + DRIVER_PATH=$VORTEX_HOME/driver/asesim ;; fpga) - DRIVER_PATH=$VORTEX_HOME/driver/opae - DRIVER_EXTRA=fpga - CLEAN_TOKEN=clean-fpga + DRIVER_PATH=$VORTEX_HOME/driver/fpga ;; simx) DRIVER_PATH=$VORTEX_HOME/driver/simx - DRIVER_EXTRA= - CLEAN_TOKEN=clean ;; *) echo "invalid driver: $DRIVER" @@ -132,7 +122,7 @@ CONFIGS="-DNUM_CLUSTERS=$CLUSTERS -DNUM_CORES=$CORES -DNUM_WARPS=$WARPS -DNUM_TH echo "CONFIGS=$CONFIGS" -make -C $DRIVER_PATH $CLEAN_TOKEN +make -C $DRIVER_PATH clean status=0 @@ -140,9 +130,9 @@ if [ $DEBUG -eq 1 ] then if [ $SCOPE -eq 1 ] then - DEBUG=1 SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + DEBUG=1 SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH else - DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + DEBUG=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH fi if [ $HAS_ARGS -eq 1 ] @@ -161,9 +151,9 @@ then else if [ $SCOPE -eq 1 ] then - SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + SCOPE=1 CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH else - CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH $DRIVER_EXTRA + CONFIGS="$CONFIGS" make -s -C $DRIVER_PATH fi if [ $HAS_ARGS -eq 1 ] diff --git a/doc/codebase.md b/doc/codebase.md index 4f4db1fc..5a33920f 100644 --- a/doc/codebase.md +++ b/doc/codebase.md @@ -7,25 +7,30 @@ The directory/file layout of the Vortex codebase is as followed: - `cache`: cache subsystem code - `fp_cores`: floating point unit code - `interfaces`: interfaces for inter-module communication - - `libs`: general-purpose modules (i.e., encoder, arbiter, ...) + - `libs`: general-purpose RTL modules - `syn`: synthesis directory - `opae`: OPAE synthesis scripts - `quartus`: Quartus synthesis scripts - `synopsys`: Synopsys synthesis scripts + - `modelsim`: Modelsim synthesis scripts - `yosys`: Yosys synthesis scripts - - `simulate`: baseline RTL simulator (used by RTLSIM) - `unit_tests`: unit tests for some hardware components -- `driver`: Host driver software +- `driver`: host drivers repository - `include`: Vortex driver public headers - - `opae`: software driver that uses Intel OPAE - - `vlsim`: software driver that simulates Full RTL (include AFU) - - `rtlsim`: software driver that simulates processor RTL + - `stub`: Vortex stub driver library + - `fpga`: software driver that uses Intel OPAE FPGA + - `asesim`: software driver that uses Intel ASE simulator + - `vlsim`: software driver that uses vlsim simulator + - `rtlsim`: software driver that uses rtlsim simulator - `simx`: software driver that uses simX simulator -- `runtime`: Kernel runtime software +- `runtime`: kernel runtime software - `include`: Vortex runtime public headers - `linker`: linker file for compiling kernels - `src`: runtime implementation -- `simX`: cycle approximate simulator for vortex +- `sim`: + - `vlsim`: AFU RTL simulator + - `rtlsim`: processor RTL simulator + - `simX`: cycle approximate simulator for vortex - `tests`: tests repository. - `runtime`: runtime tests - `regression`: regression tests diff --git a/driver/Makefile b/driver/Makefile index 58de93a2..8899c0cc 100644 --- a/driver/Makefile +++ b/driver/Makefile @@ -1,10 +1,16 @@ -all: stub rtlsim simx opae +all: stub rtlsim simx vlsim stub: $(MAKE) -C stub -opae: - $(MAKE) -C opae +fpga: + $(MAKE) -C fpga + +asesim: + $(MAKE) -C asesim + +vlsim: + $(MAKE) -C vlsim rtlsim: $(MAKE) -C rtlsim @@ -14,8 +20,10 @@ simx: clean: $(MAKE) clean -C stub - $(MAKE) clean -C opae + $(MAKE) clean -C fpga + $(MAKE) clean -C asesim + $(MAKE) clean -C vlsim $(MAKE) clean -C rtlsim $(MAKE) clean -C simx -.PHONY: all stub opae rtlsim simx clean \ No newline at end of file +.PHONY: all stub fpga asesim vlsim rtlsim simx clean \ No newline at end of file diff --git a/driver/asesim/Makefile b/driver/asesim/Makefile new file mode 100644 index 00000000..23f80bb4 --- /dev/null +++ b/driver/asesim/Makefile @@ -0,0 +1,75 @@ +OPAE_HOME ?= /tools/opae/1.4.0 + +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../include -I../../hw -I$(OPAE_HOME)/include + +LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c-ase + +# stack execution protection +LDFLAGS +=-z noexecstack + +# data relocation and projection +LDFLAGS +=-z relro -z now + +# stack buffer overrun detection +CXXFLAGS +=-fstack-protector + +# Position independent code +CXXFLAGS += -fPIC + +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + +LDFLAGS += -shared + +RTL_DIR=../../hw/rtl + +SCRIPT_DIR=../../hw/scripts + +PROJECT = libvortex.so + +AFU_JSON_INFO = vortex_afu.h + +SRCS = ../common/opae.cpp ../common/vx_utils.cpp + +# Enable scope analyzer +ifdef SCOPE + CXXFLAGS += -DSCOPE + SRCS += ../common/vx_scope.cpp + SCOPE_H = scope-defs.h +endif + +# Enable perf counters +ifdef PERF + CXXFLAGS += -DPERF_ENABLE +endif + +all: $(PROJECT) + +# AFU info from JSON file, including AFU UUID +json: ../../hw/opae/vortex_afu.json + afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ + +scope-defs.h: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json + +# generate scope data +scope: scope-defs.h + +$(PROJECT): $(SRCS) $(SCOPE_H) + $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) -o $(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + rm -rf $(PROJECT) *.o .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/driver/opae/vortex.cpp b/driver/common/opae.cpp similarity index 99% rename from driver/opae/vortex.cpp rename to driver/common/opae.cpp index 2cd12516..de6e0fbb 100755 --- a/driver/opae/vortex.cpp +++ b/driver/common/opae.cpp @@ -14,7 +14,7 @@ #include #include #elif defined(USE_VLSIM) -#include "vlsim/fpga.h" +#include #endif #include diff --git a/driver/opae/vx_scope.cpp b/driver/common/vx_scope.cpp similarity index 100% rename from driver/opae/vx_scope.cpp rename to driver/common/vx_scope.cpp diff --git a/driver/opae/vx_scope.h b/driver/common/vx_scope.h similarity index 100% rename from driver/opae/vx_scope.h rename to driver/common/vx_scope.h diff --git a/driver/opae/Makefile b/driver/fpga/Makefile similarity index 57% rename from driver/opae/Makefile rename to driver/fpga/Makefile index 936bd068..ba3d7ddf 100644 --- a/driver/opae/Makefile +++ b/driver/fpga/Makefile @@ -5,7 +5,7 @@ CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors CXXFLAGS += -I../include -I$(OPAE_HOME)/include -I../../hw -LDFLAGS += -L$(OPAE_HOME)/lib +LDFLAGS += -L$(OPAE_HOME)/lib -luuid -lopae-c #SCOPE=1 @@ -29,45 +29,29 @@ CXXFLAGS += -DDUMP_PERF_STATS LDFLAGS += -shared -FPGA_LIBS += -luuid -lopae-c - -ASE_LIBS += -luuid -lopae-c-ase - -VLSIM_LIBS += -lopae-c-vlsim - -ASE_DIR = ase - -VLSIM_DIR = vlsim - RTL_DIR=../../hw/rtl SCRIPT_DIR=../../hw/scripts PROJECT = libvortex.so -PROJECT_ASE = $(ASE_DIR)/libvortex.so - -PROJECT_VLSIM = $(VLSIM_DIR)/libvortex.so - AFU_JSON_INFO = vortex_afu.h -SRCS = vortex.cpp ../common/vx_utils.cpp +SRCS = ../common/opae.cpp ../common/vx_utils.cpp # Enable scope analyzer ifdef SCOPE CXXFLAGS += -DSCOPE - SRCS += vx_scope.cpp - SCOPE_ENABLE = SCOPE=1 + SRCS += ../common/vx_scope.cpp SCOPE_H = scope-defs.h endif # Enable perf counters ifdef PERF CXXFLAGS += -DPERF_ENABLE - PERF_ENABLE = PERF=1 endif -all: vlsim +all: $(PROJECT) # AFU info from JSON file, including AFU UUID json: ../../hw/opae/vortex_afu.json @@ -79,38 +63,15 @@ scope-defs.h: $(SCRIPT_DIR)/scope.json # generate scope data scope: scope-defs.h -vlsim-hw: $(SCOPE_H) - $(SCOPE_ENABLE) $(PERF_ENABLE) $(MAKE) -C vlsim - -fpga: $(SRCS) $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT) - -asesim: $(SRCS) $(ASE_DIR) $(SCOPE_H) - $(CXX) $(CXXFLAGS) -DUSE_ASE $(SRCS) $(LDFLAGS) $(ASE_LIBS) -o $(PROJECT_ASE) - -vlsim: $(SRCS) vlsim-hw - $(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -L./vlsim $(VLSIM_LIBS) -o $(PROJECT_VLSIM) - -vortex.o: vortex.cpp - $(CXX) $(CXXFLAGS) -c vortex.cpp -o $@ - -$(ASE_DIR): - mkdir -p ase +$(PROJECT): $(SRCS) $(SCOPE_H) + $(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) -o $(PROJECT) .depend: $(SRCS) $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; -clean-fpga: +clean: rm -rf $(PROJECT) *.o .depend -clean-asesim: - rm -rf $(PROJECT_ASE) *.o .depend - -clean-vlsim: - $(MAKE) -C vlsim clean - -clean: clean-fpga clean-asesim clean-vlsim - ifneq ($(MAKECMDGOALS),clean) -include .depend endif diff --git a/driver/opae/vlsim/ram.h b/driver/opae/vlsim/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/driver/opae/vlsim/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/driver/opae/vortex_afu.h b/driver/opae/vortex_afu.h deleted file mode 100644 index 40836450..00000000 --- a/driver/opae/vortex_afu.h +++ /dev/null @@ -1,24 +0,0 @@ -// -// Generated by afu_json_mgr from ../../hw/opae/vortex_afu.json -// - -#ifndef __AFU_JSON_INFO__ -#define __AFU_JSON_INFO__ - -#define AFU_ACCEL_NAME "vortex_afu" -#define AFU_ACCEL_UUID "35F9452B-25C2-434C-93D5-6F8C60DB361C" -#define AFU_IMAGE_CMD_MEM_READ 1 -#define AFU_IMAGE_CMD_MEM_WRITE 2 -#define AFU_IMAGE_CMD_RUN 3 -#define AFU_IMAGE_MMIO_CMD_TYPE 10 -#define AFU_IMAGE_MMIO_DATA_SIZE 16 -#define AFU_IMAGE_MMIO_IO_ADDR 12 -#define AFU_IMAGE_MMIO_MEM_ADDR 14 -#define AFU_IMAGE_MMIO_SCOPE_READ 20 -#define AFU_IMAGE_MMIO_SCOPE_WRITE 22 -#define AFU_IMAGE_MMIO_DEV_CAPS 24 -#define AFU_IMAGE_MMIO_STATUS 18 -#define AFU_IMAGE_POWER 0 -#define AFU_TOP_IFC "ccip_std_afu_avalon_mm" - -#endif // __AFU_JSON_INFO__ diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index c5972a48..21cf4b9d 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -1,90 +1,38 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors +RTLSIM_DIR = ../../sim/rtlsim -CFLAGS += -DUSE_RTLSIM -fPIC -Wno-maybe-uninitialized -CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE +CXXFLAGS += -I../include -I../../hw -I$(RTLSIM_DIR) -I$(RTLSIM_DIR)/../common -DBG_FLAGS += $(DBG_PRINT_FLAGS) -DBG_FLAGS += -DDBG_CACHE_REQ_INFO +LDFLAGS += $(RTLSIM_DIR)/librtlsim.a -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 +# Position independent code +CXXFLAGS += -fPIC -CFLAGS += $(CONFIGS) -CFLAGS += -DDUMP_PERF_STATS +# Add external configuration +CXXFLAGS += $(CONFIGS) -LDFLAGS += -shared -pthread -#LDFLAGS += -dynamiclib -pthread +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS -ifdef AXI_BUS - TOP = Vortex_axi - CFLAGS += -DAXI_BUS -else - TOP = Vortex -endif +LDFLAGS += -shared -RTL_DIR = ../../hw/rtl -DPI_DIR = ../../hw/dpi - -SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) - -VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -VL_FLAGS += --x-initial unique --x-assign unique -VL_FLAGS += verilator.vlt -VL_FLAGS += $(CONFIGS) - -# Enable Verilator multithreaded simulation -#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') -#VL_FLAGS += --threads $(THREADS) - -# Debugigng -ifdef DEBUG - VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) - CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) -else - VL_FLAGS += -DNDEBUG - CFLAGS += -DNDEBUG -endif +SRCS = vortex.cpp ../common/vx_utils.cpp # Enable perf counters ifdef PERF - VL_FLAGS += -DPERF_ENABLE - CFLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE endif -# ALU backend -VL_FLAGS += -DIMUL_DPI -VL_FLAGS += -DIDIV_DPI - -# FPU backend -FPU_CORE ?= FPU_DPI -VL_FLAGS += -D$(FPU_CORE) - PROJECT = libvortex.so -# PROJECT = libvortex.dylib all: $(PROJECT) $(PROJECT): $(SRCS) - verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) - make -j -C obj_dir -f V$(TOP).mk + $(MAKE) -C $(RTLSIM_DIR) static + $(CXX) $(CXXFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT) clean: - rm -rf $(PROJECT) obj_dir + $(MAKE) -C $(RTLSIM_DIR) clean-objdir + rm -rf $(PROJECT) *.o .depend \ No newline at end of file diff --git a/driver/rtlsim/ram.h b/driver/rtlsim/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/driver/rtlsim/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index de52ba63..64fcd72e 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -8,15 +8,11 @@ #include #include -#include +#include +#include #include -/////////////////////////////////////////////////////////////////////////////// - -inline size_t align_size(size_t size, size_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return (size + alignment - 1) & ~(alignment - 1); -} +using namespace vortex; /////////////////////////////////////////////////////////////////////////////// @@ -58,7 +54,7 @@ private: class vx_device { public: - vx_device() { + vx_device() : ram_((1<<12), (1<<20)) { mem_allocation_ = ALLOC_BASE_ADDR; } @@ -92,7 +88,7 @@ public: } printf("\n");*/ - ram_.write(dest_addr, asize, (const uint8_t*)src + src_offset); + ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); return 0; } @@ -101,7 +97,7 @@ public: if (src_addr + asize > ram_.size()) return -1; - ram_.read(src_addr, asize, (uint8_t*)dest + dest_offset); + ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); /*printf("VXDRV: download %ld bytes to 0x%lx:", size, uintptr_t((uint8_t*)dest + dest_offset)); for (int i = 0; i < (asize / CACHE_BLOCK_SIZE); ++i) { diff --git a/driver/simx/Makefile b/driver/simx/Makefile index 1a7cf33e..c2dae7d0 100644 --- a/driver/simx/Makefile +++ b/driver/simx/Makefile @@ -1,37 +1,29 @@ PROJECT = libvortex.so -#PROJECT = libvortex.dylib -SIMX_DIR = ../../simX +SIMX_DIR = ../../sim/simX CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors #CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors -CXXFLAGS += -DUSE_SIMX -fPIC -Wno-maybe-uninitialized -CXXFLAGS += -I../include -I../../hw -I$(SIMX_DIR) - -CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 - +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I../include -I../../hw -I$(SIMX_DIR) -I$(SIMX_DIR)/../common CXXFLAGS += $(CONFIGS) CXXFLAGS += -DDUMP_PERF_STATS LDFLAGS += -shared -pthread -#LDFLAGS += -dynamiclib -pthread +LDFLAGS += $(SIMX_DIR)/libsimX.a SRCS = vortex.cpp ../common/vx_utils.cpp -SRCS += $(SIMX_DIR)/util.cpp $(SIMX_DIR)/args.cpp $(SIMX_DIR)/mem.cpp $(SIMX_DIR)/pipeline.cpp $(SIMX_DIR)/warp.cpp $(SIMX_DIR)/core.cpp $(SIMX_DIR)/decode.cpp $(SIMX_DIR)/execute.cpp - -# Debugigng -ifndef DEBUG - CXXFLAGS += -DNDEBUG -endif all: $(PROJECT) $(PROJECT): $(SRCS) + $(MAKE) -C $(SIMX_DIR) static $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ .depend: $(SRCS) $(CXX) $(CXXFLAGS) -MM $^ > .depend; clean: + $(MAKE) -C $(SIMX_DIR) clean-objdir rm -rf $(PROJECT) *.o .depend \ No newline at end of file diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index 10a0143f..5ad4242b 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -10,15 +10,11 @@ #include #include #include +#include -#define PAGE_SIZE 4096 +#define PAGE_SIZE 4096 -/////////////////////////////////////////////////////////////////////////////// - -inline size_t align_size(size_t size, size_t alignment) { - assert(0 == (alignment & (alignment - 1))); - return (size + alignment - 1) & ~(alignment - 1); -} +using namespace vortex; /////////////////////////////////////////////////////////////////////////////// @@ -74,7 +70,7 @@ public: mem_allocation_ = ALLOC_BASE_ADDR; mmu_.attach(ram_, 0, 0xffffffff); for (int i = 0; i < arch_.num_cores(); ++i) { - cores_[i] = std::make_shared(arch_, decoder_, mmu_, i); + cores_[i] = std::make_shared(arch_, decoder_, mmu_, i); } } @@ -101,7 +97,7 @@ public: if (dest_addr + asize > ram_.size()) return -1; - ram_.write(dest_addr, (const uint8_t*)src + src_offset, asize); + ram_.write((const uint8_t*)src + src_offset, dest_addr, asize); /*printf("VXDRV: upload %d bytes to 0x%x\n", size, dest_addr); for (int i = 0; i < size; i += 4) { @@ -116,7 +112,7 @@ public: if (src_addr + asize > ram_.size()) return -1; - ram_.read(src_addr, (uint8_t*)dest + dest_offset, asize); + ram_.read((uint8_t*)dest + dest_offset, src_addr, asize); /*printf("VXDRV: download %d bytes from 0x%x\n", size, src_addr); for (int i = 0; i < size; i += 4) { @@ -209,15 +205,15 @@ private: device->thread_proc(); } - vortex::ArchDef arch_; - vortex::Decoder decoder_; - vortex::MemoryUnit mmu_; - std::vector> cores_; + ArchDef arch_; + Decoder decoder_; + MemoryUnit mmu_; + std::vector> cores_; bool is_done_; bool is_running_; size_t mem_allocation_; std::thread thread_; - vortex::RAM ram_; + RAM ram_; std::mutex mutex_; }; diff --git a/driver/vlsim/Makefile b/driver/vlsim/Makefile new file mode 100644 index 00000000..4ad14bc5 --- /dev/null +++ b/driver/vlsim/Makefile @@ -0,0 +1,64 @@ +VLSIM_DIR = ../../sim/vlsim + +CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors +#CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors + +CXXFLAGS += -I../include -I../../hw -I$(VLSIM_DIR) + +LDFLAGS += $(VLSIM_DIR)/libopae-c-vlsim.a + +# Position independent code +CXXFLAGS += -fPIC + +# Add external configuration +CXXFLAGS += $(CONFIGS) + +# Dump perf stats +CXXFLAGS += -DDUMP_PERF_STATS + +LDFLAGS += -shared + +RTL_DIR=../../hw/rtl + +SCRIPT_DIR=../../hw/scripts + +AFU_JSON_INFO = vortex_afu.h + +SRCS = ../common/opae.cpp ../common/vx_utils.cpp + +# Enable scope analyzer +ifdef SCOPE + CXXFLAGS += -DSCOPE + SRCS += ../common/vx_scope.cpp + SCOPE_H = scope-defs.h +endif + +# Enable perf counters +ifdef PERF + CXXFLAGS += -DPERF_ENABLE +endif + +PROJECT = libvortex.so + +all: $(PROJECT) + +scope-defs.h: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json + +# generate scope data +scope: scope-defs.h + +$(PROJECT): $(SRCS) $(SCOPE_H) + $(SCOPE_ENABLE) $(PERF_ENABLE) $(MAKE) -C $(VLSIM_DIR) static + $(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -o $(PROJECT) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $(SRCS) > .depend; + +clean: + $(MAKE) -C $(VLSIM_DIR) clean-objdir + rm -rf $(PROJECT) *.o .depend + +ifneq ($(MAKECMDGOALS),clean) + -include .depend +endif diff --git a/hw/Makefile b/hw/Makefile index 425e58d9..9a44dc2f 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,9 +1,16 @@ -.PHONY: build_config +RTL_DIR=./rtl +SCRIPT_DIR=./scripts +DESTDIR ?= . -build_config: ./rtl/VX_config.vh - ./scripts/gen_config.py -i ./rtl/VX_config.vh -o ./VX_config.h - $(MAKE) -C simulate +all: VX_config.h vortex_afu.h + +VX_config.h: $(RTL_DIR)/VX_config.vh + $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/VX_config.vh -o $(DESTDIR)/VX_config.h + +vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh + $(SCRIPT_DIR)/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o $(DESTDIR)/vortex_afu.h clean: - rm -f ./VX_config.h - $(MAKE) -C simulate clean \ No newline at end of file + rm -f $(DESTDIR)/VX_config.h $(DESTDIR)/vortex_afu.h + +.PHONY: VX_config.h vortex_afu.h \ No newline at end of file diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile deleted file mode 100644 index b43b0d4c..00000000 --- a/hw/simulate/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors - -CFLAGS += -Wno-maybe-uninitialized - -CFLAGS += -I../.. - -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE - -DBG_FLAGS += $(DBG_PRINT_FLAGS) -DBG_FLAGS += -DDBG_CACHE_REQ_INFO - -SINGLECORE = -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 - -#MULTICORE = -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -#MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 - -SINGLECORE += $(CONFIGS) -MULTICORE += $(CONFIGS) - -TOP = Vortex - -RTL_DIR=../rtl -DPI_DIR=../dpi - -FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src -RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) - -SRCS = simulator.cpp main.cpp -SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp - -VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic -VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO -VL_FLAGS += --x-initial unique --x-assign unique -VL_FLAGS += verilator.vlt - -VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE) -VL_FLAGS += --cc $(TOP) --top-module $(TOP) - -# FPU backend -FPU_CORE ?= FPU_FPNEW -VL_FLAGS += -D$(FPU_CORE) - -DBG_FLAGS += -DVCD_OUTPUT - -THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') - -all: build-s - -gen-s: - verilator $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)' - -gen-sd: - verilator $(VL_FLAGS) $(SINGLECORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS) - -gen-st: - verilator $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS) - -gen-m: - verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)' - -gen-md: - verilator $(VL_FLAGS) $(MULTICORE) -CFLAGS '$(CFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS) - -gen-mt: - verilator $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS) - -build-s: gen-s - make -j -C obj_dir -f VVortex.mk - -build-sd: gen-sd - make -j -C obj_dir -f VVortex.mk - -build-st: gen-st - make -j -C obj_dir -f VVortex.mk - -build-m: gen-m - make -j -C obj_dir -f VVortex.mk - -build-md: gen-md - make -j -C obj_dir -f VVortex.mk - -build-mt: gen-mt - make -j -C obj_dir -f VVortex.mk - -clean: - rm -rf obj_dir diff --git a/hw/simulate/ram.h b/hw/simulate/ram.h deleted file mode 100644 index 0ddd3e47..00000000 --- a/hw/simulate/ram.h +++ /dev/null @@ -1,64 +0,0 @@ -#pragma once - -#include -#include - -class RAM { -private: - - mutable uint8_t *mem_[(1 << 12)]; - - uint8_t *get(uint32_t address) const { - uint32_t block_addr = address >> 20; - uint32_t block_offset = address & 0x000FFFFF; - if (mem_[block_addr] == NULL) { - mem_[block_addr] = new uint8_t[(1 << 20)]; - } - return mem_[block_addr] + block_offset; - } - -public: - - RAM() { - for (uint32_t i = 0; i < (1 << 12); i++) { - mem_[i] = NULL; - } - } - - ~RAM() { - this->clear(); - } - - size_t size() const { - return (1ull << 32); - } - - void clear() { - for (uint32_t i = 0; i < (1 << 12); i++) { - if (mem_[i]) { - delete [] mem_[i]; - mem_[i] = NULL; - } - } - } - - void read(uint32_t address, uint32_t length, uint8_t *data) const { - for (unsigned i = 0; i < length; i++) { - data[i] = *this->get(address + i); - } - } - - void write(uint32_t address, uint32_t length, const uint8_t *data) { - for (unsigned i = 0; i < length; i++) { - *this->get(address + i) = data[i]; - } - } - - uint8_t& operator[](uint32_t address) { - return *get(address); - } - - const uint8_t& operator[](uint32_t address) const { - return *get(address); - } -}; \ No newline at end of file diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt deleted file mode 100644 index dd69f119..00000000 --- a/hw/simulate/verilator.vlt +++ /dev/null @@ -1,10 +0,0 @@ -`verilator_config - -lint_off -rule BLKANDNBLK -file "../rtl/fp_cores/fpnew/*" -lint_off -rule UNOPTFLAT -file "../rtl/fp_cores/fpnew/*" -lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" -lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" -lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" -lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" -lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/syn/opae/run_ase.sh b/hw/syn/opae/run_ase.sh index 9d7d6360..86b74121 100755 --- a/hw/syn/opae/run_ase.sh +++ b/hw/syn/opae/run_ase.sh @@ -35,5 +35,5 @@ done # run application pushd $PROGRAM_DIR echo " [DBG] running ./$PROGRAM $*" -ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $* +ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH/lib:$VORTEX_DRV_PATH/asesim:$LD_LIBRARY_PATH ./$PROGRAM $* popd \ No newline at end of file diff --git a/sim/Makefile b/sim/Makefile new file mode 100644 index 00000000..e0361709 --- /dev/null +++ b/sim/Makefile @@ -0,0 +1,9 @@ +all: + $(MAKE) -C simX + $(MAKE) -C rtlsim + $(MAKE) -C vlsim + +clean: + $(MAKE) -C simX clean + $(MAKE) -C rtlsim clean + $(MAKE) -C vlsim clean \ No newline at end of file diff --git a/simX/mem.cpp b/sim/common/mem.cpp similarity index 65% rename from simX/mem.cpp rename to sim/common/mem.cpp index 4ce4841e..6c4b94de 100644 --- a/simX/mem.cpp +++ b/sim/common/mem.cpp @@ -1,21 +1,13 @@ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "debug.h" -#include "types.h" -#include "util.h" #include "mem.h" -#include "core.h" +#include +#include +#include +#include +#include "util.h" using namespace vortex; -RamMemDevice::RamMemDevice(const char *filename, Size wordSize) +RamMemDevice::RamMemDevice(const char *filename, uint32_t wordSize) : wordSize_(wordSize) { std::ifstream input(filename); @@ -32,12 +24,12 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize) contents_.push_back(0x00); } -RamMemDevice::RamMemDevice(Size size, Size wordSize) +RamMemDevice::RamMemDevice(uint64_t size, uint32_t wordSize) : contents_(size) , wordSize_(wordSize) {} -void RamMemDevice::read(Addr addr, void *data, Size size) { +void RamMemDevice::read(void *data, uint64_t addr, uint64_t size) { auto addr_end = addr + size; if ((addr & (wordSize_-1)) || (addr_end & (wordSize_-1)) @@ -46,13 +38,13 @@ void RamMemDevice::read(Addr addr, void *data, Size size) { throw BadAddress(); } - const Byte *s = contents_.data() + addr; - for (Byte *d = (Byte*)data, *de = d + size; d != de;) { + const uint8_t *s = contents_.data() + addr; + for (uint8_t *d = (uint8_t*)data, *de = d + size; d != de;) { *d++ = *s++; } } -void RamMemDevice::write(Addr addr, const void *data, Size size) { +void RamMemDevice::write(const void *data, uint64_t addr, uint64_t size) { auto addr_end = addr + size; if ((addr & (wordSize_-1)) || (addr_end & (wordSize_-1)) @@ -61,23 +53,23 @@ void RamMemDevice::write(Addr addr, const void *data, Size size) { throw BadAddress(); } - const Byte *s = (const Byte*)data; - for (Byte *d = contents_.data() + addr, *de = d + size; d != de;) { + const uint8_t *s = (const uint8_t*)data; + for (uint8_t *d = contents_.data() + addr, *de = d + size; d != de;) { *d++ = *s++; } } /////////////////////////////////////////////////////////////////////////////// -void RomMemDevice::write(Addr /*addr*/, const void* /*data*/, Size /*size*/) { +void RomMemDevice::write(const void* /*data*/, uint64_t /*addr*/, uint64_t /*size*/) { std::cout << "attempt to write to ROM.\n"; std::abort(); } /////////////////////////////////////////////////////////////////////////////// -bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) { - Addr e = a + (wordSize - 1); +bool MemoryUnit::ADecoder::lookup(uint64_t a, uint32_t wordSize, mem_accessor_t* ma) { + uint64_t e = a + (wordSize - 1); assert(e >= a); for (auto iter = entries_.rbegin(), iterE = entries_.rend(); iter != iterE; ++iter) { if (a >= iter->start && e <= iter->end) { @@ -89,89 +81,87 @@ bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) { return false; } -void MemoryUnit::ADecoder::map(Addr a, Addr e, MemDevice &m) { +void MemoryUnit::ADecoder::map(uint64_t a, uint64_t e, MemDevice &m) { assert(e >= a); entry_t entry{&m, a, e}; entries_.emplace_back(entry); } -void MemoryUnit::ADecoder::read(Addr addr, void *data, Size size) { +void MemoryUnit::ADecoder::read(void *data, uint64_t addr, uint64_t size) { mem_accessor_t ma; if (!this->lookup(addr, size, &ma)) { std::cout << "lookup of 0x" << std::hex << addr << " failed.\n"; throw BadAddress(); } - ma.md->read(ma.addr, data, size); + ma.md->read(data, ma.addr, size); } -void MemoryUnit::ADecoder::write(Addr addr, const void *data, Size size) { +void MemoryUnit::ADecoder::write(const void *data, uint64_t addr, uint64_t size) { mem_accessor_t ma; if (!this->lookup(addr, size, &ma)) { std::cout << "lookup of 0x" << std::hex << addr << " failed.\n"; throw BadAddress(); } - ma.md->write(ma.addr, data, size); + ma.md->write(data, ma.addr, size); } /////////////////////////////////////////////////////////////////////////////// -MemoryUnit::MemoryUnit(Size pageSize, Size addrBytes, bool disableVm) +MemoryUnit::MemoryUnit(uint64_t pageSize, uint64_t addrBytes, bool disableVm) : pageSize_(pageSize) , addrBytes_(addrBytes) - , disableVm_(disableVm) { + , disableVM_(disableVm) { if (!disableVm) { tlb_[0] = TLBEntry(0, 077); } } -void MemoryUnit::attach(MemDevice &m, Addr start, Addr end) { +void MemoryUnit::attach(MemDevice &m, uint64_t start, uint64_t end) { decoder_.map(start, end, m); } -MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) { +MemoryUnit::TLBEntry MemoryUnit::tlbLookup(uint64_t vAddr, uint32_t flagMask) { auto iter = tlb_.find(vAddr / pageSize_); if (iter != tlb_.end()) { if (iter->second.flags & flagMask) return iter->second; else { - D(3, "*** Page fault on addr 0x" << std::hex << vAddr << "(bad flags)"); throw PageFault(vAddr, false); } } else { - D(3, "*** Page fault on addr 0x" << std::hex << vAddr << "(not in TLB)"); throw PageFault(vAddr, true); } } -void MemoryUnit::read(Addr addr, void *data, Size size, bool sup) { - Addr pAddr; - if (disableVm_) { +void MemoryUnit::read(void *data, uint64_t addr, uint64_t size, bool sup) { + uint64_t pAddr; + if (disableVM_) { pAddr = addr; } else { - Word flagMask = sup ? 8 : 1; + uint32_t flagMask = sup ? 8 : 1; TLBEntry t = this->tlbLookup(addr, flagMask); pAddr = t.pfn * pageSize_ + addr % pageSize_; } - return decoder_.read(pAddr, data, size); + return decoder_.read(data, pAddr, size); } -void MemoryUnit::write(Addr addr, const void *data, Size size, bool sup) { - Addr pAddr; - if (disableVm_) { +void MemoryUnit::write(const void *data, uint64_t addr, uint64_t size, bool sup) { + uint64_t pAddr; + if (disableVM_) { pAddr = addr; } else { - Word flagMask = sup ? 16 : 2; + uint32_t flagMask = sup ? 16 : 2; TLBEntry t = tlbLookup(addr, flagMask); pAddr = t.pfn * pageSize_ + addr % pageSize_; } - decoder_.write(pAddr, data, size); + decoder_.write(data, pAddr, size); } -void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) { +void MemoryUnit::tlbAdd(uint64_t virt, uint64_t phys, uint32_t flags) { tlb_[virt / pageSize_] = TLBEntry(phys / pageSize_, flags); } -void MemoryUnit::tlbRm(Addr va) { +void MemoryUnit::tlbRm(uint64_t va) { if (tlb_.find(va / pageSize_) != tlb_.end()) tlb_.erase(tlb_.find(va / pageSize_)); } @@ -182,8 +172,7 @@ RAM::RAM(uint32_t num_pages, uint32_t page_size) : page_bits_(log2ceil(page_size)) { assert(ispow2(page_size)); mem_.resize(num_pages, NULL); - uint64_t sizel = uint64_t(mem_.size()) << page_bits_; - size_ = (sizel <= 0xFFFFFFFF) ? sizel : 0xffffffff; + size_ = uint64_t(mem_.size()) << page_bits_; } RAM::~RAM() { @@ -197,16 +186,16 @@ void RAM::clear() { } } -Size RAM::size() const { +uint64_t RAM::size() const { return size_; } -uint8_t *RAM::get(uint32_t address) { +uint8_t *RAM::get(uint32_t address) const { uint32_t page_size = 1 << page_bits_; uint32_t page_index = address >> page_bits_; uint32_t byte_offset = address & ((1 << page_bits_) - 1); - uint8_t* &page = mem_.at(page_index); + auto &page = mem_.at(page_index); if (page == NULL) { uint8_t *ptr = new uint8_t[page_size]; // set uninitialized data to "baadf00d" @@ -218,37 +207,37 @@ uint8_t *RAM::get(uint32_t address) { return page + byte_offset; } -void RAM::read(Addr addr, void *data, Size size) { - Byte* d = (Byte*)data; - for (unsigned i = 0; i < size; i++) { +void RAM::read(void *data, uint64_t addr, uint64_t size) { + uint8_t* d = (uint8_t*)data; + for (uint64_t i = 0; i < size; i++) { d[i] = *this->get(addr + i); } } -void RAM::write(Addr addr, const void *data, Size size) { - const Byte* s = (const Byte*)data; - for (unsigned i = 0; i < size; i++) { +void RAM::write(const void *data, uint64_t addr, uint64_t size) { + const uint8_t* s = (const uint8_t*)data; + for (uint64_t i = 0; i < size; i++) { *this->get(addr + i) = s[i]; } } -void RAM::loadBinImage(const char* path) { - std::ifstream ifs(path); +void RAM::loadBinImage(const char* filename, uint64_t destination) { + std::ifstream ifs(filename); if (!ifs) { - std::cout << "error: " << path << " not found" << std::endl; + std::cout << "error: " << filename << " not found" << std::endl; } ifs.seekg(0, ifs.end); - auto size = ifs.tellg(); + size_t size = ifs.tellg(); std::vector content(size); ifs.seekg(0, ifs.beg); ifs.read((char*)content.data(), size); this->clear(); - this->write(STARTUP_ADDR, content.data(), size); + this->write(content.data(), destination, size); } -void RAM::loadHexImage(const char* path) { +void RAM::loadHexImage(const char* filename) { auto hti = [&](char c)->uint32_t { if (c >= 'A' && c <= 'F') return c - 'A' + 10; @@ -265,13 +254,13 @@ void RAM::loadHexImage(const char* path) { return value; }; - std::ifstream ifs(path); + std::ifstream ifs(filename); if (!ifs) { - std::cout << "error: " << path << " not found" << std::endl; + std::cout << "error: " << filename << " not found" << std::endl; } ifs.seekg(0, ifs.end); - uint32_t size = ifs.tellg(); + size_t size = ifs.tellg(); std::vector content(size); ifs.seekg(0, ifs.beg); ifs.read(content.data(), size); diff --git a/sim/common/mem.h b/sim/common/mem.h new file mode 100644 index 00000000..8929b4d9 --- /dev/null +++ b/sim/common/mem.h @@ -0,0 +1,163 @@ +#pragma once + +#include +#include + +namespace vortex { +struct BadAddress {}; + +class MemDevice { +public: + virtual ~MemDevice() {} + virtual uint64_t size() const = 0; + virtual void read(void *data, uint64_t addr, uint64_t size) = 0; + virtual void write(const void *data, uint64_t addr, uint64_t size) = 0; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RamMemDevice : public MemDevice { +public: + RamMemDevice(uint64_t size, uint32_t wordSize); + RamMemDevice(const char *filename, uint32_t wordSize); + ~RamMemDevice() {} + + void read(void *data, uint64_t addr, uint64_t size) override; + void write(const void *data, uint64_t addr, uint64_t size) override; + + virtual uint64_t size() const { + return contents_.size(); + }; + +protected: + std::vector contents_; + uint32_t wordSize_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RomMemDevice : public RamMemDevice { +public: + RomMemDevice(const char *filename, uint32_t wordSize) + : RamMemDevice(filename, wordSize) + {} + + RomMemDevice(uint64_t size, uint32_t wordSize) + : RamMemDevice(size, wordSize) + {} + + ~RomMemDevice(); + + void write(const void *data, uint64_t addr, uint64_t size) override; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class MemoryUnit { +public: + + struct PageFault { + PageFault(uint64_t a, bool nf) + : faultAddr(a) + , notFound(nf) + {} + uint64_t faultAddr; + bool notFound; + }; + + MemoryUnit(uint64_t pageSize, uint64_t addrBytes, bool disableVm = false); + + void attach(MemDevice &m, uint64_t start, uint64_t end); + + void read(void *data, uint64_t addr, uint64_t size, bool sup); + void write(const void *data, uint64_t addr, uint64_t size, bool sup); + + void tlbAdd(uint64_t virt, uint64_t phys, uint32_t flags); + void tlbRm(uint64_t va); + void tlbFlush() { + tlb_.clear(); + } +private: + + class ADecoder { + public: + ADecoder() {} + + void read(void *data, uint64_t addr, uint64_t size); + void write(const void *data, uint64_t addr, uint64_t size); + + void map(uint64_t start, uint64_t end, MemDevice &md); + + private: + + struct mem_accessor_t { + MemDevice* md; + uint64_t addr; + }; + + struct entry_t { + MemDevice *md; + uint64_t start; + uint64_t end; + }; + + bool lookup(uint64_t a, uint32_t wordSize, mem_accessor_t*); + + std::vector entries_; + }; + + struct TLBEntry { + TLBEntry() {} + TLBEntry(uint32_t pfn, uint32_t flags) + : pfn(pfn) + , flags(flags) + {} + uint32_t pfn; + uint32_t flags; + }; + + TLBEntry tlbLookup(uint64_t vAddr, uint32_t flagMask); + + std::unordered_map tlb_; + uint64_t pageSize_; + uint64_t addrBytes_; + ADecoder decoder_; + bool disableVM_; +}; + +/////////////////////////////////////////////////////////////////////////////// + +class RAM : public MemDevice { +public: + + RAM(uint32_t num_pages, uint32_t page_size); + + ~RAM(); + + void clear(); + + uint64_t size() const override; + void read(void *data, uint64_t addr, uint64_t size) override; + void write(const void *data, uint64_t addr, uint64_t size) override; + + void loadBinImage(const char* filename, uint64_t destination); + void loadHexImage(const char* filename); + + uint8_t& operator[](uint64_t address) { + return *this->get(address); + } + + const uint8_t& operator[](uint64_t address) const { + return *this->get(address); + } + +private: + + uint8_t *get(uint32_t address) const; + + mutable std::vector mem_; + uint32_t page_bits_; + uint64_t size_; +}; + +} // namespace vortex \ No newline at end of file diff --git a/sim/common/util.cpp b/sim/common/util.cpp new file mode 100644 index 00000000..94aa3540 --- /dev/null +++ b/sim/common/util.cpp @@ -0,0 +1,92 @@ +#include "util.h" +#include +#include +#include +#include +#include +#include +#include + +using namespace vortex; + +// Apply integer sign extension +uint32_t vortex::signExt(uint32_t w, uint32_t bit, uint32_t mask) { + if (w >> (bit - 1)) + w |= ~mask; + return w; +} + +// Convert a floating point number to IEEE-754 32-bit representation, +// so that it could be stored in a 32-bit integer register file +// Reference: https://www.wikihow.com/Convert-a-Number-from-Decimal-to-IEEE-754-Floating-Point-Representation + // https://www.technical-recipes.com/2012/converting-between-binary-and-decimal-representations-of-ieee-754-floating-point-numbers-in-c/ +uint32_t vortex::floatToBin(float in_value) { + union { + float input; // assumes sizeof(float) == sizeof(int) + int output; + } data; + + data.input = in_value; + + std::bitset bits(data.output); + std::string mystring = bits.to_string, std::allocator>(); + // Convert binary to uint32_t + uint32_t result = stoul(mystring, nullptr, 2); + return result; +} + +// https://en.wikipedia.org/wiki/Single-precision_floating-point_format +// check floating-point number in binary format is NaN +uint8_t vortex::fpBinIsNan(uint32_t din) { + bool fsign = din & 0x80000000; + uint32_t expo = (din>>23) & 0x000000FF; + uint32_t fraction = din & 0x007FFFFF; + uint32_t bit_22 = din & 0x00400000; + + if ((expo==0xFF) && (fraction!=0)) { + // if (!fsign && (fraction == 0x00400000)) + if (!fsign && (bit_22)) + return 1; // quiet NaN, return 1 + else + return 2; // signaling NaN, return 2 + } + return 0; +} + +// check floating-point number in binary format is zero +uint8_t vortex::fpBinIsZero(uint32_t din) { + bool fsign = din & 0x80000000; + uint32_t expo = (din>>23) & 0x000000FF; + uint32_t fraction = din & 0x007FFFFF; + + if ((expo==0) && (fraction==0)) { + if (fsign) + return 1; // negative 0 + else + return 2; // positive 0 + } + return 0; // not zero +} + +// check floating-point number in binary format is infinity +uint8_t vortex::fpBinIsInf(uint32_t din) { + bool fsign = din & 0x80000000; + uint32_t expo = (din>>23) & 0x000000FF; + uint32_t fraction = din & 0x007FFFFF; + + if ((expo==0xFF) && (fraction==0)) { + if (fsign) + return 1; // negative infinity + else + return 2; // positive infinity + } + return 0; // not infinity +} + +// return file extension +const char* vortex::fileExtension(const char* filepath) { + const char *ext = strrchr(filepath, '.'); + if (ext == NULL || ext == filepath) + return ""; + return ext + 1; +} \ No newline at end of file diff --git a/simX/util.h b/sim/common/util.h similarity index 52% rename from simX/util.h rename to sim/common/util.h index 85b64127..d04d4fe8 100644 --- a/simX/util.h +++ b/sim/common/util.h @@ -1,7 +1,7 @@ #pragma once -#include -#include "types.h" +#include +#include namespace vortex { @@ -10,7 +10,7 @@ void unused(Args&&...) {} #define __unused(...) unused(__VA_ARGS__) -constexpr bool ispow2(uint32_t value) { +constexpr bool ispow2(uint64_t value) { return value && !(value & (value - 1)); } @@ -18,20 +18,13 @@ constexpr unsigned log2ceil(uint32_t value) { return 32 - __builtin_clz(value - 1); } -Word signExt(Word w, Size bit, Word mask); +inline uint64_t align_size(uint64_t size, uint64_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); +} -Word bytesToWord(const Byte *b, Size wordSize); -void wordToBytes(Byte *b, Word w, Size wordSize); -Word flagsToWord(bool r, bool w, bool x); -void wordToFlags(bool &r, bool &w, bool &x, Word f); - -Byte readByte(const std::vector &b, Size &n); -Word readWord(const std::vector &b, Size &n, Size wordSize); -void writeByte(std::vector &p, Size &n, Byte b); -void writeWord(std::vector &p, Size &n, Size wordSize, Word w); - -// Convert 32-bit integer register file to IEEE-754 floating point number. -float intregToFloat(uint32_t input); +// Apply integer sign extension +uint32_t signExt(uint32_t w, uint32_t bit, uint32_t mask); // Convert a floating point number to IEEE-754 32-bit representation uint32_t floatToBin(float in_value); diff --git a/hw/simulate/.gitignore b/sim/rtlsim/.gitignore similarity index 100% rename from hw/simulate/.gitignore rename to sim/rtlsim/.gitignore diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile new file mode 100644 index 00000000..69284dce --- /dev/null +++ b/sim/rtlsim/Makefile @@ -0,0 +1,123 @@ +CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors +#CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors + +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I. -I../../../hw -I../../common +CXXFLAGS += -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd + +# control RTL debug print states +DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG +DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA +DBG_PRINT_FLAGS += -DDBG_PRINT_MEM +DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE +DBG_PRINT_FLAGS += -DDBG_PRINT_AVS +DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE + +DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += -DDBG_CACHE_REQ_INFO +DBG_FLAGS += -DVCD_OUTPUT + +SINGLECORE = -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 +MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 + +RTL_DIR=../../hw/rtl +DPI_DIR=../../hw/dpi + +FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src +RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) + +SRCS = ../common/util.cpp ../common/mem.cpp +SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp +SRCS += simulator.cpp + +ifdef AXI_BUS + TOP = Vortex_axi + CFLAGS += -DAXI_BUS +else + TOP = Vortex +endif + +VL_FLAGS = --cc $(TOP) --top-module $(TOP) +VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic +VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO +VL_FLAGS += --x-initial unique --x-assign unique +VL_FLAGS += verilator.vlt +VL_FLAGS += $(CONFIGS) +VL_FLAGS += $(RTL_INCLUDE) + +# Debugigng +ifdef DEBUG + VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) + CXXFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) +else + VL_FLAGS += -DNDEBUG + CXXFLAGS += -DNDEBUG +endif + +# Enable perf counters +ifdef PERF + VL_FLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE +endif + +# ALU backend +VL_FLAGS += -DIMUL_DPI +VL_FLAGS += -DIDIV_DPI + +# FPU backend +FPU_CORE ?= FPU_FPNEW +VL_FLAGS += -D$(FPU_CORE) + +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') + +OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS))) +VPATH := $(sort $(dir $(SRCS))) + +#$(info OBJS is $(OBJS)) +#$(info VPATH is $(VPATH)) + +PROJECT = rtlsim + +all: build-s + +build-s: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' -o ../$(PROJECT) + +build-sd: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) $(SINGLECORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT) + +build-st: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS) -o ../$(PROJECT) + +build-m: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' -o ../$(PROJECT) + +build-md: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) $(MULTICORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT) + +build-mt: + verilator --build --exe main.cpp $(SRCS) $(VL_FLAGS) -DNDEBUG $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS) -o ../$(PROJECT) + +obj_dir/V$(TOP)__ALL.a: + verilator --build $(VL_FLAGS) -CFLAGS '$(CXXFLAGS)' + +obj_dir/%.o: %.cpp + cd obj_dir && $(CXX) $(CXXFLAGS) -c ../$< -o $(notdir $@) + +obj_dir/verilated.o: $(VERILATOR_ROOT)/include/verilated.cpp + cd obj_dir && $(CXX) $(CXXFLAGS) -c $< -o verilated.o + +static: obj_dir/V$(TOP)__ALL.a $(OBJS) obj_dir/verilated.o + cp obj_dir/V$(TOP)__ALL.a lib$(PROJECT).a + $(AR) rs lib$(PROJECT).a $(OBJS) obj_dir/verilated.o + +clean-objdir: + rm -rf obj_dir + +clean: clean-objdir + rm -rf $(PROJECT) lib$(PROJECT).a diff --git a/hw/simulate/main.cpp b/sim/rtlsim/main.cpp similarity index 84% rename from hw/simulate/main.cpp rename to sim/rtlsim/main.cpp index e8c089de..0f0575f5 100644 --- a/hw/simulate/main.cpp +++ b/sim/rtlsim/main.cpp @@ -1,7 +1,13 @@ -#include "simulator.h" #include #include #include +#include +#include +#include +#include +#include "simulator.h" + +using namespace vortex; static void show_usage() { std::cout << "Usage: [-r] [-h: help] programs.." << std::endl; @@ -33,13 +39,6 @@ static void parse_args(int argc, char **argv) { } } -inline const char* fileExtension(const char* filepath) { - const char *ext = strrchr(filepath, '.'); - if (ext == NULL || ext == filepath) - return ""; - return ext + 1; -} - int main(int argc, char **argv) { int exitcode = 0; @@ -50,15 +49,15 @@ int main(int argc, char **argv) { for (auto program : programs) { std::cout << "Running " << program << "..." << std::endl; - RAM ram; - Simulator simulator; + vortex::RAM ram((1<<12), (1<<20)); + vortex::Simulator simulator; simulator.attach_ram(&ram); std::string program_ext(fileExtension(program)); if (program_ext == "bin") { - simulator.load_bin(program); + ram.loadBinImage(program, STARTUP_ADDR); } else if (program_ext == "hex") { - simulator.load_ihex(program); + ram.loadHexImage(program); } else { std::cout << "*** error: only *.bin or *.hex images supported." << std::endl; return -1; diff --git a/hw/simulate/simulator.cpp b/sim/rtlsim/simulator.cpp similarity index 64% rename from hw/simulate/simulator.cpp rename to sim/rtlsim/simulator.cpp index 5dc59405..cc7f1551 100644 --- a/hw/simulate/simulator.cpp +++ b/sim/rtlsim/simulator.cpp @@ -1,7 +1,23 @@ #include "simulator.h" + +#include + +#ifdef AXI_BUS +#include "VVortex_axi.h" +#include "VVortex_axi__Syms.h" +#else +#include "VVortex.h" +#include "VVortex__Syms.h" +#endif + +#ifdef VCD_OUTPUT +#include +#endif + #include #include #include +#include #define ENABLE_MEM_STALLS @@ -32,6 +48,8 @@ #define VL_WDATA_GETW(lwp, i, n, w) \ VL_SEL_IWII(0, n * w, 0, 0, lwp, i * w, w) +using namespace vortex; + static uint64_t timestamp = 0; double sc_time_stamp() { @@ -57,29 +75,55 @@ void sim_trace_enable(bool enable) { /////////////////////////////////////////////////////////////////////////////// -Simulator::Simulator() { - // force random values for unitialized signals - Verilated::randReset(VERILATOR_RESET_VALUE); - Verilated::randSeed(50); - - // Turn off assertion before reset - Verilated::assertOn(false); - - ram_ = nullptr; - +namespace vortex { +class VL_OBJ { +public: #ifdef AXI_BUS - vortex_ = new VVortex_axi(); + VVortex_axi *device; #else - vortex_ = new VVortex(); + VVortex *device; +#endif +#ifdef VCD_OUTPUT + VerilatedVcdC *trace; #endif -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC(); - vortex_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif + VL_OBJ() { + // force random values for unitialized signals + Verilated::randReset(VERILATOR_RESET_VALUE); + Verilated::randSeed(50); + // Turn off assertion before reset + Verilated::assertOn(false); + + #ifdef AXI_BUS + this->device = new VVortex_axi(); + #else + this->device = new VVortex(); + #endif + + #ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->trace = new VerilatedVcdC(); + this->device->trace(this->trace, 99); + this->trace->open("trace.vcd"); + #endif + } + + ~VL_OBJ() { + #ifdef VCD_OUTPUT + this->trace->close(); + delete this->trace; + #endif + delete this->device; + } +}; +} + +/////////////////////////////////////////////////////////////////////////////// + +Simulator::Simulator() { + vl_obj_ = new VL_OBJ(); + ram_ = nullptr; // reset the device this->reset(); } @@ -91,11 +135,7 @@ Simulator::~Simulator() { std::cout << "#" << buf.first << ": " << str << std::endl; } } -#ifdef VCD_OUTPUT - trace_->close(); - delete trace_; -#endif - delete vortex_; + delete vl_obj_; } void Simulator::attach_ram(RAM* ram) { @@ -122,16 +162,16 @@ void Simulator::reset() { this->reset_mem_bus(); #endif - vortex_->reset = 1; + vl_obj_->device->reset = 1; for (int i = 0; i < RESET_DELAY; ++i) { - vortex_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); - vortex_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); } - vortex_->reset = 0; + vl_obj_->device->reset = 0; // Turn on assertion after reset Verilated::assertOn(true); @@ -139,7 +179,7 @@ void Simulator::reset() { void Simulator::step() { - vortex_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); #ifdef AXI_BUS @@ -148,7 +188,7 @@ void Simulator::step() { this->eval_mem_bus(0); #endif - vortex_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); #ifdef AXI_BUS @@ -163,10 +203,10 @@ void Simulator::step() { } void Simulator::eval() { - vortex_->eval(); + vl_obj_->device->eval(); #ifdef VCD_OUTPUT if (sim_trace_enabled()) { - trace_->dump(timestamp); + vl_obj_->trace->dump(timestamp); } #endif ++timestamp; @@ -175,23 +215,23 @@ void Simulator::eval() { #ifdef AXI_BUS void Simulator::reset_axi_bus() { - vortex_->m_axi_wready = 0; - vortex_->m_axi_awready = 0; - vortex_->m_axi_arready = 0; - vortex_->m_axi_rvalid = 0; + vl_obj_->device->m_axi_wready = 0; + vl_obj_->device->m_axi_awready = 0; + vl_obj_->device->m_axi_arready = 0; + vl_obj_->device->m_axi_rvalid = 0; } void Simulator::eval_axi_bus(bool clk) { if (!clk) { - mem_rd_rsp_ready_ = vortex_->m_axi_rready; - mem_wr_rsp_ready_ = vortex_->m_axi_bready; + mem_rd_rsp_ready_ = vl_obj_->device->m_axi_rready; + mem_wr_rsp_ready_ = vl_obj_->device->m_axi_bready; return; } if (ram_ == nullptr) { - vortex_->m_axi_wready = 0; - vortex_->m_axi_awready = 0; - vortex_->m_axi_arready = 0; + vl_obj_->device->m_axi_wready = 0; + vl_obj_->device->m_axi_awready = 0; + vl_obj_->device->m_axi_arready = 0; return; } @@ -222,7 +262,7 @@ void Simulator::eval_axi_bus(bool clk) { // send memory read response if (mem_rd_rsp_active_ - && vortex_->m_axi_rvalid && mem_rd_rsp_ready_) { + && vl_obj_->device->m_axi_rvalid && mem_rd_rsp_ready_) { mem_rd_rsp_active_ = false; } if (!mem_rd_rsp_active_) { @@ -235,21 +275,21 @@ void Simulator::eval_axi_bus(bool clk) { } printf("\n"); */ - vortex_->m_axi_rvalid = 1; - vortex_->m_axi_rid = mem_rsp_it->tag; - vortex_->m_axi_rresp = 0; - vortex_->m_axi_rlast = 1; - memcpy((uint8_t*)vortex_->m_axi_rdata, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); + vl_obj_->device->m_axi_rvalid = 1; + vl_obj_->device->m_axi_rid = mem_rsp_it->tag; + vl_obj_->device->m_axi_rresp = 0; + vl_obj_->device->m_axi_rlast = 1; + memcpy((uint8_t*)vl_obj_->device->m_axi_rdata, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); mem_rd_rsp_active_ = true; } else { - vortex_->m_axi_rvalid = 0; + vl_obj_->device->m_axi_rvalid = 0; } } // send memory write response if (mem_wr_rsp_active_ - && vortex_->m_axi_bvalid && mem_wr_rsp_ready_) { + && vl_obj_->device->m_axi_bvalid && mem_wr_rsp_ready_) { mem_wr_rsp_active_ = false; } if (!mem_wr_rsp_active_) { @@ -258,18 +298,18 @@ void Simulator::eval_axi_bus(bool clk) { /* printf("%0ld: [sim] MEM Wr Rsp: bank=%d, addr=%0lx\n", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr); */ - vortex_->m_axi_bvalid = 1; - vortex_->m_axi_bid = mem_rsp_it->tag; - vortex_->m_axi_bresp = 0; + vl_obj_->device->m_axi_bvalid = 1; + vl_obj_->device->m_axi_bid = mem_rsp_it->tag; + vl_obj_->device->m_axi_bresp = 0; mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); mem_wr_rsp_active_ = true; } else { - vortex_->m_axi_bvalid = 0; + vl_obj_->device->m_axi_bvalid = 0; } } // select the memory bank - uint32_t req_addr = vortex_->m_axi_wvalid ? vortex_->m_axi_awaddr : vortex_->m_axi_araddr; + uint32_t req_addr = vl_obj_->device->m_axi_wvalid ? vl_obj_->device->m_axi_awaddr : vl_obj_->device->m_axi_araddr; uint32_t req_bank = (MEMORY_BANKS >= 2) ? ((req_addr / MEM_BLOCK_SIZE) % MEMORY_BANKS) : 0; // handle memory stalls @@ -285,11 +325,11 @@ void Simulator::eval_axi_bus(bool clk) { // process memory requests if (!mem_stalled) { - if (vortex_->m_axi_wvalid || vortex_->m_axi_arvalid) { - if (vortex_->m_axi_wvalid) { - uint64_t byteen = vortex_->m_axi_wstrb; - unsigned base_addr = vortex_->m_axi_awaddr; - uint8_t* data = (uint8_t*)(vortex_->m_axi_wdata); + if (vl_obj_->device->m_axi_wvalid || vl_obj_->device->m_axi_arvalid) { + if (vl_obj_->device->m_axi_wvalid) { + uint64_t byteen = vl_obj_->device->m_axi_wstrb; + unsigned base_addr = vl_obj_->device->m_axi_awaddr; + uint8_t* data = (uint8_t*)(vl_obj_->device->m_axi_wdata); // detect stdout write if (base_addr >= IO_COUT_ADDR @@ -319,17 +359,17 @@ void Simulator::eval_axi_bus(bool clk) { } } mem_req_t mem_req; - mem_req.tag = vortex_->m_axi_arid; - mem_req.addr = vortex_->m_axi_araddr; + mem_req.tag = vl_obj_->device->m_axi_arid; + mem_req.addr = vl_obj_->device->m_axi_araddr; mem_req.cycles_left = 0; mem_req.write = 1; mem_rsp_vec_[req_bank].emplace_back(mem_req); } } else { mem_req_t mem_req; - mem_req.tag = vortex_->m_axi_arid; - mem_req.addr = vortex_->m_axi_araddr; - ram_->read(vortex_->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data()); + mem_req.tag = vl_obj_->device->m_axi_arid; + mem_req.addr = vl_obj_->device->m_axi_araddr; + ram_->read(vl_obj_->device->m_axi_araddr, MEM_BLOCK_SIZE, mem_req.block.data()); mem_req.cycles_left = MEM_LATENCY; mem_req.write = 0; for (auto& rsp : mem_rsp_vec_[req_bank]) { @@ -344,26 +384,26 @@ void Simulator::eval_axi_bus(bool clk) { } } - vortex_->m_axi_wready = !mem_stalled; - vortex_->m_axi_awready = !mem_stalled; - vortex_->m_axi_arready = !mem_stalled; + vl_obj_->device->m_axi_wready = !mem_stalled; + vl_obj_->device->m_axi_awready = !mem_stalled; + vl_obj_->device->m_axi_arready = !mem_stalled; } #else void Simulator::reset_mem_bus() { - vortex_->mem_req_ready = 0; - vortex_->mem_rsp_valid = 0; + vl_obj_->device->mem_req_ready = 0; + vl_obj_->device->mem_rsp_valid = 0; } void Simulator::eval_mem_bus(bool clk) { if (!clk) { - mem_rd_rsp_ready_ = vortex_->mem_rsp_ready; + mem_rd_rsp_ready_ = vl_obj_->device->mem_rsp_ready; return; } if (ram_ == nullptr) { - vortex_->mem_req_ready = 0; + vl_obj_->device->mem_req_ready = 0; return; } @@ -390,12 +430,12 @@ void Simulator::eval_mem_bus(bool clk) { // send memory response if (mem_rd_rsp_active_ - && vortex_->mem_rsp_valid && mem_rd_rsp_ready_) { + && vl_obj_->device->mem_rsp_valid && mem_rd_rsp_ready_) { mem_rd_rsp_active_ = false; } if (!mem_rd_rsp_active_) { if (has_response) { - vortex_->mem_rsp_valid = 1; + vl_obj_->device->mem_rsp_valid = 1; auto mem_rsp_it = mem_rsp_vec_[last_mem_rsp_bank_].begin(); /* printf("%0ld: [sim] MEM Rd: bank=%d, addr=%0lx, data=", timestamp, last_mem_rsp_bank_, mem_rsp_it->addr); @@ -404,17 +444,17 @@ void Simulator::eval_mem_bus(bool clk) { } printf("\n"); */ - memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); - vortex_->mem_rsp_tag = mem_rsp_it->tag; + memcpy((uint8_t*)vl_obj_->device->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); + vl_obj_->device->mem_rsp_tag = mem_rsp_it->tag; mem_rsp_vec_[last_mem_rsp_bank_].erase(mem_rsp_it); mem_rd_rsp_active_ = true; } else { - vortex_->mem_rsp_valid = 0; + vl_obj_->device->mem_rsp_valid = 0; } } // select the memory bank - uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vortex_->mem_req_addr % MEMORY_BANKS) : 0; + uint32_t req_bank = (MEMORY_BANKS >= 2) ? (vl_obj_->device->mem_req_addr % MEMORY_BANKS) : 0; // handle memory stalls bool mem_stalled = false; @@ -429,11 +469,11 @@ void Simulator::eval_mem_bus(bool clk) { // process memory requests if (!mem_stalled) { - if (vortex_->mem_req_valid) { - if (vortex_->mem_req_rw) { - uint64_t byteen = vortex_->mem_req_byteen; - unsigned base_addr = (vortex_->mem_req_addr * MEM_BLOCK_SIZE); - uint8_t* data = (uint8_t*)(vortex_->mem_req_data); + if (vl_obj_->device->mem_req_valid) { + if (vl_obj_->device->mem_req_rw) { + uint64_t byteen = vl_obj_->device->mem_req_byteen; + unsigned base_addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(vl_obj_->device->mem_req_data); if (base_addr >= IO_COUT_ADDR && base_addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) { for (int i = 0; i < MEM_BLOCK_SIZE; i++) { @@ -463,9 +503,9 @@ void Simulator::eval_mem_bus(bool clk) { } } else { mem_req_t mem_req; - mem_req.tag = vortex_->mem_req_tag; - mem_req.addr = (vortex_->mem_req_addr * MEM_BLOCK_SIZE); - ram_->read(vortex_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.block.data()); + mem_req.tag = vl_obj_->device->mem_req_tag; + mem_req.addr = (vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE); + ram_->read(mem_req.block.data(), vl_obj_->device->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE); mem_req.cycles_left = MEM_LATENCY; for (auto& rsp : mem_rsp_vec_[req_bank]) { if (mem_req.addr == rsp.addr) { @@ -479,7 +519,7 @@ void Simulator::eval_mem_bus(bool clk) { } } - vortex_->mem_req_ready = !mem_stalled; + vl_obj_->device->mem_req_ready = !mem_stalled; } #endif @@ -491,7 +531,7 @@ void Simulator::wait(uint32_t cycles) { } bool Simulator::is_busy() const { - return vortex_->busy; + return vl_obj_->device->busy; } int Simulator::run() { @@ -502,7 +542,7 @@ int Simulator::run() { #endif // execute program - while (vortex_->busy) { + while (vl_obj_->device->busy) { if (get_ebreak()) { exitcode = get_last_wb_value(3); break; @@ -518,104 +558,20 @@ int Simulator::run() { bool Simulator::get_ebreak() const { #ifdef AXI_BUS - return (int)vortex_->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; + return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; #else - return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; + return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->execute->ebreak; #endif } int Simulator::get_last_wb_value(int reg) const { #ifdef AXI_BUS - return (int)vortex_->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; + return (int)vl_obj_->device->Vortex_axi->vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; #else - return (int)vortex_->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; + return (int)vl_obj_->device->Vortex->genblk2__BRA__0__KET____DOT__cluster->genblk2__BRA__0__KET____DOT__core->pipeline->commit->writeback->last_wb_value[reg]; #endif } -void Simulator::load_bin(const char* program_file) { - if (ram_ == nullptr) - return; - - std::ifstream ifs(program_file); - if (!ifs) { - std::cout << "error: " << program_file << " not found" << std::endl; - } - - ifs.seekg(0, ifs.end); - auto size = ifs.tellg(); - std::vector content(size); - ifs.seekg(0, ifs.beg); - ifs.read((char*)content.data(), size); - - ram_->write(STARTUP_ADDR, size, content.data()); -} - -void Simulator::load_ihex(const char* program_file) { - if (ram_ == nullptr) - return; - - auto hti = [&](char c)->uint32_t { - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return c - '0'; - }; - - auto hToI = [&](const char *c, uint32_t size)->uint32_t { - uint32_t value = 0; - for (uint32_t i = 0; i < size; i++) { - value += hti(c[i]) << ((size - i - 1) * 4); - } - return value; - }; - - std::ifstream ifs(program_file); - if (!ifs) { - std::cout << "error: " << program_file << " not found" << std::endl; - } - - ifs.seekg(0, ifs.end); - uint32_t size = ifs.tellg(); - std::vector content(size); - ifs.seekg(0, ifs.beg); - ifs.read(content.data(), size); - - int offset = 0; - char *line = content.data(); - - while (true) { - if (line[0] == ':') { - uint32_t byteCount = hToI(line + 1, 2); - uint32_t nextAddr = hToI(line + 3, 4) + offset; - uint32_t key = hToI(line + 7, 2); - switch (key) { - case 0: - for (uint32_t i = 0; i < byteCount; i++) { - (*ram_)[nextAddr + i] = hToI(line + 9 + i * 2, 2); - } - break; - case 2: - offset = hToI(line + 9, 4) << 4; - break; - case 4: - offset = hToI(line + 9, 4) << 16; - break; - default: - break; - } - } - while (*line != '\n' && size != 0) { - ++line; - --size; - } - if (size <= 1) - break; - ++line; - --size; - } -} - void Simulator::print_stats(std::ostream& out) { out << std::left; out << std::setw(24) << "# of total cycles:" << std::dec << timestamp/2 << std::endl; diff --git a/hw/simulate/simulator.h b/sim/rtlsim/simulator.h similarity index 73% rename from hw/simulate/simulator.h rename to sim/rtlsim/simulator.h index ca618b6a..3b36c520 100644 --- a/hw/simulate/simulator.h +++ b/sim/rtlsim/simulator.h @@ -1,22 +1,6 @@ #pragma once -#include - -#ifdef AXI_BUS -#include "VVortex_axi.h" -#include "VVortex_axi__Syms.h" -#else -#include "VVortex.h" -#include "VVortex__Syms.h" -#endif - -#ifdef VCD_OUTPUT -#include -#endif - #include -#include "ram.h" - #include #include #include @@ -31,6 +15,11 @@ #endif #endif +namespace vortex { + +class VL_OBJ; +class RAM; + class Simulator { public: @@ -39,9 +28,6 @@ public: void attach_ram(RAM* ram); - void load_bin(const char* program_file); - void load_ihex(const char* program_file); - bool is_busy() const; void reset(); @@ -89,13 +75,7 @@ private: RAM *ram_; -#ifdef AXI_BUS - VVortex_axi *vortex_; -#else - VVortex *vortex_; -#endif + VL_OBJ* vl_obj_; +}; -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file +} \ No newline at end of file diff --git a/driver/rtlsim/verilator.vlt b/sim/rtlsim/verilator.vlt similarity index 90% rename from driver/rtlsim/verilator.vlt rename to sim/rtlsim/verilator.vlt index 792578ea..986af455 100644 --- a/driver/rtlsim/verilator.vlt +++ b/sim/rtlsim/verilator.vlt @@ -7,4 +7,4 @@ lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" -lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/sim/simX/Makefile b/sim/simX/Makefile new file mode 100644 index 00000000..70bd281b --- /dev/null +++ b/sim/simX/Makefile @@ -0,0 +1,49 @@ +#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors +CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors + +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I. -I../common -I../../hw +CXXFLAGS += -DDUMP_PERF_STATS + +TOP = vx_cache_sim + +RTL_DIR = ../hw/rtl + +PROJECT = simX + +SRCS = ../common/util.cpp ../common/mem.cpp +SRCS += args.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp + +OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS))) +VPATH := $(sort $(dir $(SRCS))) + +#$(info OBJS is $(OBJS)) +#$(info VPATH is $(VPATH)) + +# Debugigng +ifdef DEBUG + CXXFLAGS += -DDEBUG_LEVEL=$(DEBUG) +else + CXXFLAGS += -DNDEBUG +endif + +all: $(PROJECT) + +$(PROJECT): $(SRCS) + $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ + +obj_dir/%.o: %.cpp + mkdir -p obj_dir + $(CXX) $(CXXFLAGS) -c $< -o $@ + +static: $(OBJS) + $(AR) rs lib$(PROJECT).a $(OBJS) + +.depend: $(SRCS) + $(CXX) $(CXXFLAGS) -MM $^ > .depend; + +clean-objdir: + rm -rf obj_dir .depend + +clean: clean-objdir + rm -rf $(PROJECT) lib$(PROJECT).a \ No newline at end of file diff --git a/simX/archdef.h b/sim/simX/archdef.h similarity index 100% rename from simX/archdef.h rename to sim/simX/archdef.h diff --git a/simX/args.cpp b/sim/simX/args.cpp similarity index 100% rename from simX/args.cpp rename to sim/simX/args.cpp diff --git a/simX/args.h b/sim/simX/args.h similarity index 98% rename from simX/args.h rename to sim/simX/args.h index 7fbf236c..aeaba4e5 100644 --- a/simX/args.h +++ b/sim/simX/args.h @@ -4,7 +4,7 @@ #include #include #include -#include "util.h" +#include namespace vortex { diff --git a/simX/core.cpp b/sim/simX/core.cpp similarity index 97% rename from simX/core.cpp rename to sim/simX/core.cpp index a431a050..c68ac854 100644 --- a/simX/core.cpp +++ b/sim/simX/core.cpp @@ -2,8 +2,8 @@ #include #include #include +#include #include "types.h" -#include "util.h" #include "archdef.h" #include "mem.h" #include "decode.h" @@ -323,7 +323,7 @@ void Core::barrier(int bar_id, int count, int warp_id) { Word Core::icache_fetch(Addr addr) { Word data; - mem_.read(addr, &data, sizeof(Word), 0); + mem_.read(&data, addr, sizeof(Word), 0); return data; } @@ -333,11 +333,11 @@ Word Core::dcache_read(Addr addr, Size size) { #ifdef SM_ENABLE if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE)) && ((addr + 3) < SMEM_BASE_ADDR)) { - shared_mem_.read(addr & (SMEM_SIZE-1), &data, size); + shared_mem_.read(&data, addr & (SMEM_SIZE-1), size); return data; } #endif - mem_.read(addr, &data, size, 0); + mem_.read(&data, addr, size, 0); return data; } @@ -346,7 +346,7 @@ void Core::dcache_write(Addr addr, Word data, Size size) { #ifdef SM_ENABLE if ((addr >= (SMEM_BASE_ADDR - SMEM_SIZE)) && ((addr + 3) < SMEM_BASE_ADDR)) { - shared_mem_.write(addr & (SMEM_SIZE-1), &data, size); + shared_mem_.write(&data, addr & (SMEM_SIZE-1), size); return; } #endif @@ -355,7 +355,7 @@ void Core::dcache_write(Addr addr, Word data, Size size) { this->writeToStdOut(addr, data); return; } - mem_.write(addr, &data, size, 0); + mem_.write(&data, addr, size, 0); } bool Core::running() const { diff --git a/simX/core.h b/sim/simX/core.h similarity index 100% rename from simX/core.h rename to sim/simX/core.h diff --git a/simX/debug.h b/sim/simX/debug.h similarity index 100% rename from simX/debug.h rename to sim/simX/debug.h diff --git a/simX/decode.cpp b/sim/simX/decode.cpp similarity index 98% rename from simX/decode.cpp rename to sim/simX/decode.cpp index 11b8e92d..01570aab 100644 --- a/simX/decode.cpp +++ b/sim/simX/decode.cpp @@ -5,9 +5,9 @@ #include #include #include +#include #include "debug.h" #include "types.h" -#include "util.h" #include "decode.h" #include "archdef.h" #include "instr.h" @@ -280,7 +280,7 @@ Decoder::Decoder(const ArchDef &arch) { v_imm_mask_ = 0x7ff; } -std::shared_ptr Decoder::decode(Word code) { +std::shared_ptr Decoder::decode(Word code, Word PC) { auto instr = std::make_shared(); Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_); instr->setOpcode(op); @@ -289,14 +289,14 @@ std::shared_ptr Decoder::decode(Word code) { Word func6 = (code >> shift_func6_) & func6_mask_; Word func7 = (code >> shift_func7_) & func7_mask_; - int rd = (code >> shift_rd_) & reg_mask_; + int rd = (code >> shift_rd_) & reg_mask_; int rs1 = (code >> shift_rs1_) & reg_mask_; int rs2 = (code >> shift_rs2_) & reg_mask_; int rs3 = (code >> shift_rs3_) & reg_mask_; auto op_it = sc_instTable.find(op); if (op_it == sc_instTable.end()) { - std::cout << std::hex << "invalid opcode: 0x" << op << ", instruction=0x" << code << std::endl; + std::cout << std::hex << "invalid opcode: 0x" << op << ", instruction=0x" << code << ", PC=" << PC << std::endl; std::abort(); } diff --git a/simX/decode.h b/sim/simX/decode.h similarity index 94% rename from simX/decode.h rename to sim/simX/decode.h index 6335a494..f8f3909c 100644 --- a/simX/decode.h +++ b/sim/simX/decode.h @@ -13,7 +13,7 @@ class Decoder { public: Decoder(const ArchDef &); - std::shared_ptr decode(Word code); + std::shared_ptr decode(Word code, Word PC); private: diff --git a/simX/execute.cpp b/sim/simX/execute.cpp similarity index 99% rename from simX/execute.cpp rename to sim/simX/execute.cpp index 8a1c00db..dfb38ab4 100644 --- a/simX/execute.cpp +++ b/sim/simX/execute.cpp @@ -8,7 +8,7 @@ #include #include #include -#include "util.h" +#include #include "warp.h" #include "instr.h" #include "core.h" @@ -535,8 +535,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { else rddata = rsdata[0]; } else { - float fpsrc_0 = intregToFloat(rsdata[0]); - float fpsrc_1 = intregToFloat(rsdata[1]); + float fpsrc_0 = *(float*)&rsdata[0]; + float fpsrc_1 = *(float*)&rsdata[1]; float fpDest; feclearexcept(FE_ALL_EXCEPT); @@ -618,8 +618,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { rddata = (sr1IsZero==2) ? rsdata[0] : rsdata[1]; } } else { - float rs1 = intregToFloat(rsdata[0]); - float rs2 = intregToFloat(rsdata[1]); + float rs1 = *(float*)&rsdata[0]; + float rs2 = *(float*)&rsdata[1]; if (func3) { // FMAX.S float fmax = std::max(rs1, rs2); @@ -635,7 +635,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { // FCVT.W.S FCVT.WU.S case 0x60: { - float fpSrc = intregToFloat(rsdata[0]); + float fpSrc = *(float*)&rsdata[0]; Word result; bool outOfRange = false; if (rsrc1 == 0) { @@ -741,15 +741,15 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { switch(func3) { case 0: { // FLE.S - rddata = (intregToFloat(rsdata[0]) <= intregToFloat(rsdata[1])); + rddata = (*(float*)&rsdata[0] <= *(float*)&rsdata[1]); } break; case 1: { // FLT.S - rddata = (intregToFloat(rsdata[0]) < intregToFloat(rsdata[1])); + rddata = (*(float*)&rsdata[0] < *(float*)&rsdata[1]); } break; case 2: { // FEQ.S - rddata = (intregToFloat(rsdata[0]) == intregToFloat(rsdata[1])); + rddata = (*(float*)&rsdata[0] == *(float*)&rsdata[1]); } break; default: std::abort(); @@ -800,9 +800,9 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) { } rddata = 0x7fc00000; // canonical(quiet) NaN } else { - float rs1 = intregToFloat(rsdata[0]); - float rs2 = intregToFloat(rsdata[1]); - float rs3 = intregToFloat(rsdata[2]); + float rs1 = *(float*)&rsdata[0]; + float rs2 = *(float*)&rsdata[1]; + float rs3 = *(float*)&rsdata[2]; float fpDest(0.0); feclearexcept(FE_ALL_EXCEPT); switch (opcode) { diff --git a/simX/instr.h b/sim/simX/instr.h similarity index 100% rename from simX/instr.h rename to sim/simX/instr.h diff --git a/simX/main.cpp b/sim/simX/main.cpp similarity index 98% rename from simX/main.cpp rename to sim/simX/main.cpp index 07d34129..9af8ff02 100644 --- a/simX/main.cpp +++ b/sim/simX/main.cpp @@ -57,7 +57,7 @@ int main(int argc, char **argv) { std::string program_ext(fileExtension(imgFileName.c_str())); if (program_ext == "bin") { - ram.loadBinImage(imgFileName.c_str()); + ram.loadBinImage(imgFileName.c_str(), STARTUP_ADDR); } else if (program_ext == "hex") { ram.loadHexImage(imgFileName.c_str()); } else { diff --git a/simX/pipeline.cpp b/sim/simX/pipeline.cpp similarity index 100% rename from simX/pipeline.cpp rename to sim/simX/pipeline.cpp diff --git a/simX/pipeline.h b/sim/simX/pipeline.h similarity index 93% rename from simX/pipeline.h rename to sim/simX/pipeline.h index 42cb2af1..f8899a63 100644 --- a/simX/pipeline.h +++ b/sim/simX/pipeline.h @@ -2,8 +2,9 @@ #pragma once #include +#include +#include "types.h" #include "debug.h" -#include "util.h" namespace vortex { diff --git a/simX/types.h b/sim/simX/types.h similarity index 74% rename from simX/types.h rename to sim/simX/types.h index 256118b2..ca732040 100644 --- a/simX/types.h +++ b/sim/simX/types.h @@ -19,13 +19,4 @@ typedef std::bitset<32> ThreadMask; typedef std::bitset<32> WarpMask; -enum MemFlags { - RD_USR = 1, - WR_USR = 2, - EX_USR = 4, - RD_SUP = 8, - WR_SUP = 16, - EX_SUP = 32 -}; - } \ No newline at end of file diff --git a/simX/warp.cpp b/sim/simX/warp.cpp similarity index 99% rename from simX/warp.cpp rename to sim/simX/warp.cpp index bc6ff242..a505fe5c 100644 --- a/simX/warp.cpp +++ b/sim/simX/warp.cpp @@ -3,8 +3,8 @@ #include #include #include +#include -#include "util.h" #include "instr.h" #include "core.h" diff --git a/simX/warp.h b/sim/simX/warp.h similarity index 100% rename from simX/warp.h rename to sim/simX/warp.h diff --git a/driver/opae/vlsim/.gitignore b/sim/vlsim/.gitignore similarity index 100% rename from driver/opae/vlsim/.gitignore rename to sim/vlsim/.gitignore diff --git a/driver/opae/vlsim/Makefile b/sim/vlsim/Makefile similarity index 58% rename from driver/opae/vlsim/Makefile rename to sim/vlsim/Makefile index 52189e9f..3b15bbf6 100644 --- a/driver/opae/vlsim/Makefile +++ b/sim/vlsim/Makefile @@ -1,8 +1,9 @@ -CFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -#CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors +CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors +#CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors -CFLAGS += -DUSE_VLSIM -fPIC -Wno-maybe-uninitialized -CFLAGS += -I../../../../hw +CXXFLAGS += -fPIC -Wno-maybe-uninitialized +CXXFLAGS += -I. -I../../../hw -I../../common +CXXFLAGS += -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd # control RTL debug print states DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE @@ -22,29 +23,31 @@ DBG_FLAGS += -DDBG_CACHE_REQ_INFO CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 -CFLAGS += $(CONFIGS) -CFLAGS += -DDUMP_PERF_STATS +CXXFLAGS += $(CONFIGS) +CXXFLAGS += -DDUMP_PERF_STATS -LDFLAGS += -shared -pthread -# LDFLAGS += -dynamiclib -pthread +LDFLAGS += -shared -TOP = vortex_afu_shim +RTL_DIR = ../../hw/rtl +DPI_DIR = ../../hw/dpi -RTL_DIR=../../../hw/rtl -DPI_DIR=../../../hw/dpi - -SRCS = fpga.cpp opae_sim.cpp +SRCS = ../common/util.cpp ../common/mem.cpp SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp +SRCS += fpga.cpp opae_sim.cpp FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) RTL_INCLUDE += -I$(RTL_DIR)/afu -I$(RTL_DIR)/afu/ccip +TOP = vortex_afu_shim + +VL_FLAGS = --cc $(TOP) --top-module $(TOP) VL_FLAGS += -O2 --language 1800-2009 --assert -Wall -Wpedantic VL_FLAGS += -Wno-DECLFILENAME -Wno-REDEFMACRO VL_FLAGS += --x-initial unique --x-assign unique VL_FLAGS += verilator.vlt VL_FLAGS += $(CONFIGS) +VL_FLAGS += $(RTL_INCLUDE) # Enable Verilator multithreaded simulation #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') @@ -53,27 +56,27 @@ VL_FLAGS += $(CONFIGS) # Debugigng ifdef DEBUG VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS) - CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) + CXXFLAGS += -DVCD_OUTPUT $(DBG_FLAGS) else VL_FLAGS += -DNDEBUG - CFLAGS += -DNDEBUG + CXXFLAGS += -DNDEBUG endif # Enable scope analyzer ifdef SCOPE VL_FLAGS += -DSCOPE - CFLAGS += -DSCOPE + CXXFLAGS += -DSCOPE endif # Enable perf counters ifdef PERF VL_FLAGS += -DPERF_ENABLE - CFLAGS += -DPERF_ENABLE + CXXFLAGS += -DPERF_ENABLE endif # use our OPAE shim VL_FLAGS += -DNOPAE -CFLAGS += -DNOPAE +CXXFLAGS += -DNOPAE # ALU backend VL_FLAGS += -DIMUL_DPI @@ -83,16 +86,31 @@ VL_FLAGS += -DIDIV_DPI FPU_CORE ?= FPU_DPI VL_FLAGS += -D$(FPU_CORE) -PROJECT = libopae-c-vlsim.so +OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS))) +VPATH := $(sort $(dir $(SRCS))) -all: $(PROJECT) +#$(info OBJS is $(OBJS)) +#$(info VPATH is $(VPATH)) -vortex_afu.h : $(RTL_DIR)/afu/vortex_afu.vh - ../../../hw/scripts/gen_config.py -i $(RTL_DIR)/afu/vortex_afu.vh -o vortex_afu.h - -$(PROJECT): $(SRCS) vortex_afu.h - verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) - make -j -C obj_dir -f V$(TOP).mk +PROJECT = libopae-c-vlsim -clean: - rm -rf $(PROJECT) obj_dir ../scope-defs.h $(RTL_DIR)/scope-defs.vh vortex_afu.h +all: shared + +shared: $(SRCS) + verilator --build --exe $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT).so + +obj_dir/V$(TOP)__ALL.a: + verilator --build $(VL_FLAGS) -CFLAGS '$(CXXFLAGS)' + +obj_dir/%.o: %.cpp + cd obj_dir && $(CXX) $(CXXFLAGS) -c ../$< -o $(notdir $@) + +static: obj_dir/V$(TOP)__ALL.a $(OBJS) + cp obj_dir/V$(TOP)__ALL.a $(PROJECT).a + $(AR) rs $(PROJECT).a $(OBJS) + +clean-objdir: + rm -rf obj_dir + +clean: clean-objdir + rm -rf $(PROJECT).a $(PROJECT).so diff --git a/driver/opae/vlsim/fpga.cpp b/sim/vlsim/fpga.cpp similarity index 100% rename from driver/opae/vlsim/fpga.cpp rename to sim/vlsim/fpga.cpp diff --git a/driver/opae/vlsim/fpga.h b/sim/vlsim/fpga.h similarity index 100% rename from driver/opae/vlsim/fpga.h rename to sim/vlsim/fpga.h diff --git a/driver/opae/vlsim/opae_sim.cpp b/sim/vlsim/opae_sim.cpp similarity index 61% rename from driver/opae/vlsim/opae_sim.cpp rename to sim/vlsim/opae_sim.cpp index 40890908..ced1e233 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/sim/vlsim/opae_sim.cpp @@ -1,7 +1,17 @@ #include "opae_sim.h" + +#include +#include "Vvortex_afu_shim.h" +#include "Vvortex_afu_shim__Syms.h" + +#ifdef VCD_OUTPUT +#include +#endif + #include #include #include +#include #define CCI_LATENCY 8 #define CCI_RAND_MOD 8 @@ -34,6 +44,8 @@ #define VERILATOR_RESET_VALUE 2 #endif +using namespace vortex; + static uint64_t timestamp = 0; double sc_time_stamp() { @@ -74,25 +86,57 @@ void sim_trace_enable(bool enable) { /////////////////////////////////////////////////////////////////////////////// +namespace vortex { +class VL_OBJ { +public: +#ifdef AXI_BUS + VVortex_axi *device; +#else + Vvortex_afu_shim *device; +#endif +#ifdef VCD_OUTPUT + VerilatedVcdC *trace; +#endif + + VL_OBJ() { + // force random values for unitialized signals + Verilated::randReset(VERILATOR_RESET_VALUE); + Verilated::randSeed(50); + + // Turn off assertion before reset + Verilated::assertOn(false); + + #ifdef AXI_BUS + this->device = new Vvortex_afu_shim(); + #else + this->device = new Vvortex_afu_shim(); + #endif + + #ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + this->trace = new VerilatedVcdC(); + this->device->trace(this->trace, 99); + this->trace->open("trace.vcd"); + #endif + } + + ~VL_OBJ() { + #ifdef VCD_OUTPUT + this->trace->close(); + delete this->trace; + #endif + delete this->device; + } +}; +} + +/////////////////////////////////////////////////////////////////////////////// + opae_sim::opae_sim() : stop_(false) - , host_buffer_ids_(0) -{ - // force random values for unitialized signals - Verilated::randReset(VERILATOR_RESET_VALUE); - Verilated::randSeed(50); - - // Turn off assertion before reset - Verilated::assertOn(false); - - vortex_afu_ = new Vvortex_afu_shim(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC(); - vortex_afu_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif + , host_buffer_ids_(0) { + vl_obj_ = new VL_OBJ(); + ram_ = new RAM((1<<12), (1<<20)); // reset the device this->reset(); @@ -110,15 +154,12 @@ opae_sim::~opae_sim() { stop_ = true; if (future_.valid()) { future_.wait(); - } -#ifdef VCD_OUTPUT - trace_->close(); - delete trace_; -#endif + } for (auto& buffer : host_buffers_) { __aligned_free(buffer.second.data); } - delete vortex_afu_; + delete vl_obj_; + delete ram_; } int opae_sim::prepare_buffer(uint64_t len, void **buf_addr, uint64_t *wsid, int flags) { @@ -151,26 +192,26 @@ void opae_sim::get_io_address(uint64_t wsid, uint64_t *ioaddr) { void opae_sim::read_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t *value) { std::lock_guard guard(mutex_); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; this->step(); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0; - assert(vortex_afu_->af2cp_sTxPort_c2_mmioRdValid); - *value = vortex_afu_->af2cp_sTxPort_c2_data; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 0; + assert(vl_obj_->device->af2cp_sTxPort_c2_mmioRdValid); + *value = vl_obj_->device->af2cp_sTxPort_c2_data; } void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value) { std::lock_guard guard(mutex_); - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; - vortex_afu_->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; - memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, &value, 8); + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_address = offset / 4; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_length = 1; + vl_obj_->device->vcp2af_sRxPort_c0_ReqMmioHdr_tid = 0; + memcpy(vl_obj_->device->vcp2af_sRxPort_c0_data, &value, 8); this->step(); - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 0; } /////////////////////////////////////////////////////////////////////////////// @@ -178,29 +219,29 @@ void opae_sim::write_mmio64(uint32_t mmio_num, uint64_t offset, uint64_t value) void opae_sim::reset() { cci_reads_.clear(); cci_writes_.clear(); - vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0; - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0; - vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = 0; - vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull = 0; + vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull = 0; for (int b = 0; b < MEMORY_BANKS; ++b) { mem_reads_[b].clear(); - vortex_afu_->avs_readdatavalid[b] = 0; - vortex_afu_->avs_waitrequest[b] = 0; + vl_obj_->device->avs_readdatavalid[b] = 0; + vl_obj_->device->avs_waitrequest[b] = 0; } - vortex_afu_->reset = 1; + vl_obj_->device->reset = 1; for (int i = 0; i < RESET_DELAY; ++i) { - vortex_afu_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); - vortex_afu_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); } - vortex_afu_->reset = 0; + vl_obj_->device->reset = 0; // Turn on assertion after reset Verilated::assertOn(true); @@ -211,9 +252,9 @@ void opae_sim::step() { this->sTxPort_bus(); this->avs_bus(); - vortex_afu_->clk = 0; + vl_obj_->device->clk = 0; this->eval(); - vortex_afu_->clk = 1; + vl_obj_->device->clk = 1; this->eval(); #ifndef NDEBUG @@ -222,10 +263,10 @@ void opae_sim::step() { } void opae_sim::eval() { - vortex_afu_->eval(); + vl_obj_->device->eval(); #ifdef VCD_OUTPUT if (sim_trace_enabled()) { - trace_->dump(timestamp); + vl_obj_->trace->dump(timestamp); } #endif ++timestamp; @@ -233,8 +274,8 @@ void opae_sim::eval() { void opae_sim::sRxPort_bus() { // check mmio request - bool mmio_req_enabled = vortex_afu_->vcp2af_sRxPort_c0_mmioRdValid - || vortex_afu_->vcp2af_sRxPort_c0_mmioWrValid; + bool mmio_req_enabled = vl_obj_->device->vcp2af_sRxPort_c0_mmioRdValid + || vl_obj_->device->vcp2af_sRxPort_c0_mmioWrValid; // schedule CCI read responses std::list::iterator cci_rd_it(cci_reads_.end()); @@ -257,22 +298,22 @@ void opae_sim::sRxPort_bus() { } // send CCI write response - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 0; if (cci_wr_it != cci_writes_.end()) { - vortex_afu_->vcp2af_sRxPort_c1_rspValid = 1; - vortex_afu_->vcp2af_sRxPort_c1_hdr_resp_type = 0; - vortex_afu_->vcp2af_sRxPort_c1_hdr_mdata = cci_wr_it->mdata; + vl_obj_->device->vcp2af_sRxPort_c1_rspValid = 1; + vl_obj_->device->vcp2af_sRxPort_c1_hdr_resp_type = 0; + vl_obj_->device->vcp2af_sRxPort_c1_hdr_mdata = cci_wr_it->mdata; cci_writes_.erase(cci_wr_it); } // send CCI read response (ensure mmio disabled) - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 0; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 0; if (!mmio_req_enabled && (cci_rd_it != cci_reads_.end())) { - vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1; - vortex_afu_->vcp2af_sRxPort_c0_hdr_resp_type = 0; - memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_rd_it->data.data(), CACHE_BLOCK_SIZE); - vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; + vl_obj_->device->vcp2af_sRxPort_c0_rspValid = 1; + vl_obj_->device->vcp2af_sRxPort_c0_hdr_resp_type = 0; + memcpy(vl_obj_->device->vcp2af_sRxPort_c0_data, cci_rd_it->data.data(), CACHE_BLOCK_SIZE); + vl_obj_->device->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; /*printf("%0ld: [sim] CCI Rd Rsp: addr=%ld, mdata=%d, data=", timestamp, cci_rd_it->addr, cci_rd_it->mdata); for (int i = 0; i < CACHE_BLOCK_SIZE; ++i) printf("%02x", cci_rd_it->data[CACHE_BLOCK_SIZE-1-i]); @@ -283,32 +324,32 @@ void opae_sim::sRxPort_bus() { void opae_sim::sTxPort_bus() { // process read requests - if (vortex_afu_->af2cp_sTxPort_c0_valid) { - assert(!vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull); + if (vl_obj_->device->af2cp_sTxPort_c0_valid) { + assert(!vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull); cci_rd_req_t cci_req; cci_req.cycles_left = CCI_LATENCY + (timestamp % CCI_RAND_MOD); - cci_req.addr = vortex_afu_->af2cp_sTxPort_c0_hdr_address; - cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata; - auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); + cci_req.addr = vl_obj_->device->af2cp_sTxPort_c0_hdr_address; + cci_req.mdata = vl_obj_->device->af2cp_sTxPort_c0_hdr_mdata; + auto host_ptr = (uint64_t*)(vl_obj_->device->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); memcpy(cci_req.data.data(), host_ptr, CACHE_BLOCK_SIZE); - //printf("%0ld: [sim] CCI Rd Req: addr=%ld, mdata=%d\n", timestamp, vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); + //printf("%0ld: [sim] CCI Rd Req: addr=%ld, mdata=%d\n", timestamp, vl_obj_->device->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); cci_reads_.emplace_back(cci_req); } // process write requests - if (vortex_afu_->af2cp_sTxPort_c1_valid) { - assert(!vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull); + if (vl_obj_->device->af2cp_sTxPort_c1_valid) { + assert(!vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull); cci_wr_req_t cci_req; cci_req.cycles_left = CCI_LATENCY + (timestamp % CCI_RAND_MOD); - cci_req.mdata = vortex_afu_->af2cp_sTxPort_c1_hdr_mdata; - auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c1_hdr_address * CACHE_BLOCK_SIZE); - memcpy(host_ptr, vortex_afu_->af2cp_sTxPort_c1_data, CACHE_BLOCK_SIZE); + cci_req.mdata = vl_obj_->device->af2cp_sTxPort_c1_hdr_mdata; + auto host_ptr = (uint64_t*)(vl_obj_->device->af2cp_sTxPort_c1_hdr_address * CACHE_BLOCK_SIZE); + memcpy(host_ptr, vl_obj_->device->af2cp_sTxPort_c1_data, CACHE_BLOCK_SIZE); cci_writes_.emplace_back(cci_req); } // check queues overflow - vortex_afu_->vcp2af_sRxPort_c0_TxAlmFull = (cci_reads_.size() >= (CCI_RQ_SIZE-1)); - vortex_afu_->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= (CCI_WQ_SIZE-1)); + vl_obj_->device->vcp2af_sRxPort_c0_TxAlmFull = (cci_reads_.size() >= (CCI_RQ_SIZE-1)); + vl_obj_->device->vcp2af_sRxPort_c1_TxAlmFull = (cci_writes_.size() >= (CCI_WQ_SIZE-1)); } void opae_sim::avs_bus() { @@ -327,10 +368,10 @@ void opae_sim::avs_bus() { } // send memory response - vortex_afu_->avs_readdatavalid[b] = 0; + vl_obj_->device->avs_readdatavalid[b] = 0; if (mem_rd_it != mem_reads_[b].end()) { - vortex_afu_->avs_readdatavalid[b] = 1; - memcpy(vortex_afu_->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE); + vl_obj_->device->avs_readdatavalid[b] = 1; + memcpy(vl_obj_->device->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE); uint32_t addr = mem_rd_it->addr; mem_reads_[b].erase(mem_rd_it); /*printf("%0ld: [sim] MEM Rd Rsp: bank=%d, addr=%x, pending={", timestamp, b, addr * MEM_BLOCK_SIZE); @@ -356,14 +397,14 @@ void opae_sim::avs_bus() { // process memory requests if (!mem_stalled) { - assert(!vortex_afu_->avs_read[b] || !vortex_afu_->avs_write[b]); - if (vortex_afu_->avs_write[b]) { - uint64_t byteen = vortex_afu_->avs_byteenable[b]; - unsigned base_addr = vortex_afu_->avs_address[b] * MEM_BLOCK_SIZE; - uint8_t* data = (uint8_t*)(vortex_afu_->avs_writedata[b]); + assert(!vl_obj_->device->avs_read[b] || !vl_obj_->device->avs_write[b]); + if (vl_obj_->device->avs_write[b]) { + uint64_t byteen = vl_obj_->device->avs_byteenable[b]; + unsigned base_addr = vl_obj_->device->avs_address[b] * MEM_BLOCK_SIZE; + uint8_t* data = (uint8_t*)(vl_obj_->device->avs_writedata[b]); for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { - ram_[base_addr + i] = data[i]; + (*ram_)[base_addr + i] = data[i]; } } /*printf("%0ld: [sim] MEM Wr Req: bank=%d, addr=%x, data=", timestamp, b, base_addr); @@ -372,10 +413,10 @@ void opae_sim::avs_bus() { } printf("\n");*/ } - if (vortex_afu_->avs_read[b]) { + if (vl_obj_->device->avs_read[b]) { mem_rd_req_t mem_req; - mem_req.addr = vortex_afu_->avs_address[b]; - ram_.read(vortex_afu_->avs_address[b] * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data.data()); + mem_req.addr = vl_obj_->device->avs_address[b]; + ram_->read(mem_req.data.data(), vl_obj_->device->avs_address[b] * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE); mem_req.cycles_left = MEM_LATENCY; for (auto& rsp : mem_reads_[b]) { if (mem_req.addr == rsp.addr) { @@ -396,6 +437,6 @@ void opae_sim::avs_bus() { } } - vortex_afu_->avs_waitrequest[b] = mem_stalled; + vl_obj_->device->avs_waitrequest[b] = mem_stalled; } } \ No newline at end of file diff --git a/driver/opae/vlsim/opae_sim.h b/sim/vlsim/opae_sim.h similarity index 85% rename from driver/opae/vlsim/opae_sim.h rename to sim/vlsim/opae_sim.h index 3d20180a..aa19532f 100644 --- a/driver/opae/vlsim/opae_sim.h +++ b/sim/vlsim/opae_sim.h @@ -1,16 +1,7 @@ #pragma once -#include -#include "Vvortex_afu_shim.h" -#include "Vvortex_afu_shim__Syms.h" - -#ifdef VCD_OUTPUT -#include -#endif - #include -#include "vortex_afu.h" -#include "ram.h" +#include #include #include @@ -30,6 +21,11 @@ #define CACHE_BLOCK_SIZE 64 +namespace vortex { + +class VL_OBJ; +class RAM; + class opae_sim { public: @@ -96,9 +92,9 @@ private: std::mutex mutex_; - RAM ram_; - Vvortex_afu_shim *vortex_afu_; -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; \ No newline at end of file + RAM *ram_; + + VL_OBJ* vl_obj_; +}; + +} \ No newline at end of file diff --git a/driver/opae/vlsim/verilator.vlt b/sim/vlsim/verilator.vlt similarity index 100% rename from driver/opae/vlsim/verilator.vlt rename to sim/vlsim/verilator.vlt diff --git a/driver/opae/vlsim/vortex_afu_shim.sv b/sim/vlsim/vortex_afu_shim.sv similarity index 100% rename from driver/opae/vlsim/vortex_afu_shim.sv rename to sim/vlsim/vortex_afu_shim.sv diff --git a/simX/Makefile b/simX/Makefile deleted file mode 100644 index e4cb9fbb..00000000 --- a/simX/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors -CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors - -CXXFLAGS += -Wno-maybe-uninitialized -CXXFLAGS += -I. -I../hw -CXXFLAGS += -DDUMP_PERF_STATS - -TOP = vx_cache_sim - -RTL_DIR = ../hw/rtl - -PROJECT = simX - -SRCS = util.cpp args.cpp mem.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp - -# Debugigng -ifdef DEBUG - CXXFLAGS += -DDEBUG_LEVEL=$(DEBUG) -else - CXXFLAGS += -DNDEBUG -endif - -all: $(PROJECT) - -$(PROJECT): $(SRCS) - $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ - -.depend: $(SRCS) - $(CXX) $(CXXFLAGS) -MM $^ > .depend; - -clean: - rm -rf $(PROJECT) *.o .depend diff --git a/simX/mem.h b/simX/mem.h deleted file mode 100644 index 5c3e3211..00000000 --- a/simX/mem.h +++ /dev/null @@ -1,159 +0,0 @@ -#pragma once - -#include -#include -#include -#include -#include "types.h" - -namespace vortex { -struct BadAddress {}; - -class MemDevice { -public: - virtual ~MemDevice() {} - virtual Size size() const = 0; - virtual void read(Addr addr, void *data, Size size) = 0; - virtual void write(Addr addr, const void *data, Size size) = 0; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RamMemDevice : public MemDevice { -public: - RamMemDevice(Size size, Size wordSize); - RamMemDevice(const char *filename, Size wordSize); - ~RamMemDevice() {} - - void read(Addr addr, void *data, Size size) override; - void write(Addr addr, const void *data, Size size) override; - - virtual Size size() const { - return contents_.size(); - }; - -protected: - std::vector contents_; - Size wordSize_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RomMemDevice : public RamMemDevice { -public: - RomMemDevice(const char *filename, Size wordSize) - : RamMemDevice(filename, wordSize) - {} - - RomMemDevice(Size size, Size wordSize) - : RamMemDevice(size, wordSize) - {} - - ~RomMemDevice(); - - void write(Addr addr, const void *data, Size size) override; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class MemoryUnit { -public: - - struct PageFault { - PageFault(Addr a, bool nf) - : faultAddr(a) - , notFound(nf) - {} - Addr faultAddr; - bool notFound; - }; - - MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false); - - void attach(MemDevice &m, Addr start, Addr end); - - void read(Addr addr, void *data, Size size, bool sup); - void write(Addr addr, const void *data, Size size, bool sup); - - void tlbAdd(Addr virt, Addr phys, Word flags); - void tlbRm(Addr va); - void tlbFlush() { - tlb_.clear(); - } -private: - - class ADecoder { - public: - ADecoder() {} - - void read(Addr addr, void *data, Size size); - void write(Addr addr, const void *data, Size size); - - void map(Addr start, Addr end, MemDevice &md); - - private: - - struct mem_accessor_t { - MemDevice* md; - Addr addr; - }; - - struct entry_t { - MemDevice *md; - Addr start; - Addr end; - }; - - bool lookup(Addr a, Size wordSize, mem_accessor_t*); - - std::vector entries_; - }; - - struct TLBEntry { - TLBEntry() {} - TLBEntry(Word pfn, Word flags) - : pfn(pfn) - , flags(flags) - {} - Word pfn; - Word flags; - }; - - TLBEntry tlbLookup(Addr vAddr, Word flagMask); - - std::unordered_map tlb_; - Size pageSize_; - Size addrBytes_; - ADecoder decoder_; - bool disableVm_; -}; - -/////////////////////////////////////////////////////////////////////////////// - -class RAM : public MemDevice { -public: - - RAM(uint32_t num_pages, uint32_t page_size); - - ~RAM(); - - void clear(); - - Size size() const override; - void read(Addr addr, void *data, Size size) override; - void write(Addr addr, const void *data, Size size) override; - - void loadBinImage(const char* path); - - void loadHexImage(const char* path); - -private: - - uint8_t *get(uint32_t address); - - std::vector mem_; - uint32_t page_bits_; - uint32_t size_; -}; - -} // namespace vortex \ No newline at end of file diff --git a/simX/util.cpp b/simX/util.cpp deleted file mode 100644 index 7f78eb7b..00000000 --- a/simX/util.cpp +++ /dev/null @@ -1,188 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "types.h" -#include "util.h" - -using namespace vortex; - -Word vortex::signExt(Word w, Size bit, Word mask) { - if (w >> (bit - 1)) - w |= ~mask; - return w; -} - -void vortex::wordToBytes(Byte *b, Word w, Size wordSize) { - while (wordSize--) { - *(b++) = w & 0xff; - w >>= 8; - } -} - -Word vortex::bytesToWord(const Byte *b, Size wordSize) { - Word w = 0; - b += wordSize-1; - while (wordSize--) { - w <<= 8; - w |= *(b--); - } - return w; -} - -Word vortex::flagsToWord(bool r, bool w, bool x) { - Word word = 0; - if (r) word |= RD_USR; - if (w) word |= WR_USR; - if (x) word |= EX_USR; - return word; -} - -void vortex::wordToFlags(bool &r, bool &w, bool &x, Word f) { - r = f & RD_USR; - w = f & WR_USR; - x = f & EX_USR; -} - -Byte vortex::readByte(const std::vector &b, Size &n) { - if (b.size() <= n) - throw std::out_of_range("out of range"); - return b[n++]; -} - -Word vortex::readWord(const std::vector &b, Size &n, Size wordSize) { - if (b.size() - n < wordSize) - throw std::out_of_range("out of range"); - Word w(0); - n += wordSize; - // std::cout << "wordSize: " << wordSize << "\n"; - for (Size i = 0; i < wordSize; i++) { - w <<= 8; - // cout << "index: " << n - i - 1 << "\n"; - w |= b[n - i - 1]; - } - // cout << "b[0]" << std::hex << w << "\n"; - return w; -} - -void vortex::writeByte(std::vector &p, Size &n, Byte b) { - if (p.size() <= n) p.resize(n+1); - p[n++] = b; -} - -void vortex::writeWord(std::vector &p, Size &n, Size wordSize, Word w) { - if (p.size() < (n+wordSize)) p.resize(n+wordSize); - while (wordSize--) { - p[n++] = w & 0xff; - w >>= 8; - } -} - -// Convert 32-bit integer register file to IEEE-754 floating point number. -float vortex::intregToFloat(uint32_t input) { - // 31th bit - bool sign = input & 0x80000000; - // Exponent: 23th ~ 30th bits -> 8 bits in total - int32_t exp = ((input & 0x7F800000)>>23); - // printf("exp = %u\n", exp); - // 0th ~ 22th bits -> 23 bits fraction - uint32_t frac = input & 0x007FFFFF; - // Frac_value= 1 + sum{i = 1}{23}{b_{23-i}*2^{-i}} - double frac_value; - if (exp == 0) { // subnormal - if (frac == 0) { - // zero - if (sign) - return -0.0; - else - return 0.0; - } - frac_value = 0.0; - } else - frac_value = 1.0; - - for (int i = 0; i < 23; i++) { - int bi = frac & 0x1; - frac_value += static_cast(bi * pow(2.0, i-23)); - frac = (frac >> 1); - } - - return (float)((static_cast(pow(-1.0, sign))) * (static_cast(pow(2.0, exp - 127.0)))* frac_value); -} - -// Convert a floating point number to IEEE-754 32-bit representation, -// so that it could be stored in a 32-bit integer register file -// Reference: https://www.wikihow.com/Convert-a-Number-from-Decimal-to-IEEE-754-Floating-Point-Representation - // https://www.technical-recipes.com/2012/converting-between-binary-and-decimal-representations-of-ieee-754-floating-point-numbers-in-c/ -uint32_t vortex::floatToBin(float in_value) { - union { - float input; // assumes sizeof(float) == sizeof(int) - int output; - } data; - - data.input = in_value; - - std::bitset bits(data.output); - std::string mystring = bits.to_string, std::allocator >(); - // Convert binary to uint32_t - Word result = stoul(mystring, nullptr, 2); - return result; -} - -// https://en.wikipedia.org/wiki/Single-precision_floating-point_format -// check floating-point number in binary format is NaN -uint8_t vortex::fpBinIsNan(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - uint32_t bit_22 = din & 0x00400000; - - if ((expo==0xFF) && (fraction!=0)) { - // if (!fsign && (fraction == 0x00400000)) - if (!fsign && (bit_22)) - return 1; // quiet NaN, return 1 - else - return 2; // signaling NaN, return 2 - } - return 0; -} - -// check floating-point number in binary format is zero -uint8_t vortex::fpBinIsZero(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - - if ((expo==0) && (fraction==0)) { - if (fsign) - return 1; // negative 0 - else - return 2; // positive 0 - } - return 0; // not zero -} - -// check floating-point number in binary format is infinity -uint8_t vortex::fpBinIsInf(uint32_t din) { - bool fsign = din & 0x80000000; - uint32_t expo = (din>>23) & 0x000000FF; - uint32_t fraction = din & 0x007FFFFF; - - if ((expo==0xFF) && (fraction==0)) { - if (fsign) - return 1; // negative infinity - else - return 2; // positive infinity - } - return 0; // not infinity -} - -const char* vortex::fileExtension(const char* filepath) { - const char *ext = strrchr(filepath, '.'); - if (ext == NULL || ext == filepath) - return ""; - return ext + 1; -} \ No newline at end of file diff --git a/tests/opencl/bfs/Makefile b/tests/opencl/bfs/Makefile index cf71bf13..32eca492 100644 --- a/tests/opencl/bfs/Makefile +++ b/tests/opencl/bfs/Makefile @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/convolution/Makefile b/tests/opencl/convolution/Makefile index 0a1e9d0c..694e5f8c 100644 --- a/tests/opencl/convolution/Makefile +++ b/tests/opencl/convolution/Makefile @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/guassian/Makefile b/tests/opencl/guassian/Makefile index dd98e5dd..a2ded527 100644 --- a/tests/opencl/guassian/Makefile +++ b/tests/opencl/guassian/Makefile @@ -34,13 +34,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/kmeans/Makefile b/tests/opencl/kmeans/Makefile index fee9950b..98f56777 100644 --- a/tests/opencl/kmeans/Makefile +++ b/tests/opencl/kmeans/Makefile @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/nearn/Makefile b/tests/opencl/nearn/Makefile index 84045f59..182b913e 100644 --- a/tests/opencl/nearn/Makefile +++ b/tests/opencl/nearn/Makefile @@ -36,13 +36,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/oclprintf/Makefile b/tests/opencl/oclprintf/Makefile index 88eafa1c..33385763 100644 --- a/tests/opencl/oclprintf/Makefile +++ b/tests/opencl/oclprintf/Makefile @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/psort/Makefile b/tests/opencl/psort/Makefile index f1b48924..faf9a0f7 100644 --- a/tests/opencl/psort/Makefile +++ b/tests/opencl/psort/Makefile @@ -1,16 +1,25 @@ -LLVM_PREFIX ?= /opt/llvm-riscv +#LLVM_PREFIX ?= /opt/llvm-riscv +#LLVM_PREFIX=/home/blaise/dev/llvm-riscv/builddbg +#LLVM_PREFIX=/home/blaise/dev/llvm_rv12/build_dbg/release +LLVM_PREFIX=/home/blaise/dev/llvm-riscv/build_rel + RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain SYSROOT ?= $(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf POCL_CC_PATH ?= /opt/pocl/compiler POCL_RT_PATH ?= /opt/pocl/runtime -OPTS ?= -n32 +OPTS ?= -f -n16 VORTEX_DRV_PATH ?= $(realpath ../../../driver) VORTEX_RT_PATH ?= $(realpath ../../../runtime) -K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -float-abi=hard -code-model=small" -K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" +#CC = ${CLANG_PATH}/bin/clang +#AR = ${CLANG_PATH}/bin/llvm-ar +#DP = ${CLANG_PATH}/bin/llvm-objdump +#CP = ${CLANG_PATH}/bin/llvm-objcopy + +K_LLCFLAGS += "-O3 -march=riscv32 -target-abi=ilp32f -mcpu=generic-rv32 -mattr=+m,+f -mattr=+vortex -float-abi=hard -code-model=small" +K_CFLAGS += "-v -O3 --sysroot=$(SYSROOT) --gcc-toolchain=$(RISCV_TOOLCHAIN_PATH) -march=rv32imf -mabi=ilp32f -Xclang -target-feature -Xclang +vortex -I$(VORTEX_RT_PATH)/include -fno-rtti -fno-exceptions -ffreestanding -nostartfiles -fdata-sections -ffunction-sections" K_LDFLAGS += "-Wl,-Bstatic,-T$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a -lm" CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors @@ -35,13 +44,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/saxpy/Makefile b/tests/opencl/saxpy/Makefile index 0414fcff..03c74c72 100644 --- a/tests/opencl/saxpy/Makefile +++ b/tests/opencl/saxpy/Makefile @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/sfilter/Makefile b/tests/opencl/sfilter/Makefile index 6a22e827..8bac4aaf 100644 --- a/tests/opencl/sfilter/Makefile +++ b/tests/opencl/sfilter/Makefile @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/sgemm/Makefile b/tests/opencl/sgemm/Makefile index ebfcad08..1416b831 100644 --- a/tests/opencl/sgemm/Makefile +++ b/tests/opencl/sgemm/Makefile @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/opencl/transpose/Makefile b/tests/opencl/transpose/Makefile index d19ad3c7..016cfaa4 100644 --- a/tests/opencl/transpose/Makefile +++ b/tests/opencl/transpose/Makefile @@ -31,13 +31,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) diff --git a/tests/opencl/vecadd/Makefile b/tests/opencl/vecadd/Makefile index 04065438..ad48243c 100644 --- a/tests/opencl/vecadd/Makefile +++ b/tests/opencl/vecadd/Makefile @@ -35,13 +35,13 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@ run-fpga: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.pocl - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-simx: $(PROJECT) kernel.pocl LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/basic/Makefile b/tests/regression/basic/Makefile index 139ec97d..dcf85e2d 100644 --- a/tests/regression/basic/Makefile +++ b/tests/regression/basic/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/demo/Makefile b/tests/regression/demo/Makefile index a78f605a..798f5780 100644 --- a/tests/regression/demo/Makefile +++ b/tests/regression/demo/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/diverge/Makefile b/tests/regression/diverge/Makefile index 6c531257..679847af 100644 --- a/tests/regression/diverge/Makefile +++ b/tests/regression/diverge/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/dogfood/Makefile b/tests/regression/dogfood/Makefile index dce752d4..61113c7e 100644 --- a/tests/regression/dogfood/Makefile +++ b/tests/regression/dogfood/Makefile @@ -47,13 +47,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/fence/Makefile b/tests/regression/fence/Makefile index 7440669f..3491cb99 100644 --- a/tests/regression/fence/Makefile +++ b/tests/regression/fence/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/io_addr/Makefile b/tests/regression/io_addr/Makefile index 36f05992..80f62fc6 100644 --- a/tests/regression/io_addr/Makefile +++ b/tests/regression/io_addr/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/mstress/Makefile b/tests/regression/mstress/Makefile index 14e40685..024967de 100644 --- a/tests/regression/mstress/Makefile +++ b/tests/regression/mstress/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/no_mf_ext/Makefile b/tests/regression/no_mf_ext/Makefile index fd43dc85..99384023 100644 --- a/tests/regression/no_mf_ext/Makefile +++ b/tests/regression/no_mf_ext/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/no_smem/Makefile b/tests/regression/no_smem/Makefile index 74c3190c..de5a4f78 100644 --- a/tests/regression/no_smem/Makefile +++ b/tests/regression/no_smem/Makefile @@ -47,13 +47,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/printf/Makefile b/tests/regression/printf/Makefile index 9e67a639..a7aeb266 100644 --- a/tests/regression/printf/Makefile +++ b/tests/regression/printf/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/regression/sort/Makefile b/tests/regression/sort/Makefile index e4e8a25c..ef4d86f0 100644 --- a/tests/regression/sort/Makefile +++ b/tests/regression/sort/Makefile @@ -45,13 +45,13 @@ run-simx: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/simx:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-fpga: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/fpga:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-asesim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/asesim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-vlsim: $(PROJECT) kernel.bin - LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/opae/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) + LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/vlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) run-rtlsim: $(PROJECT) kernel.bin LD_LIBRARY_PATH=$(POCL_RT_PATH)/lib:$(VORTEX_DRV_PATH)/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) $(OPTS) diff --git a/tests/riscv/isa/Makefile b/tests/riscv/isa/Makefile index 4684911d..b3d22140 100644 --- a/tests/riscv/isa/Makefile +++ b/tests/riscv/isa/Makefile @@ -8,7 +8,7 @@ EXCLUDED_TESTS := $(V_TESTS) $(D_TESTS) rv32si-p-scall.hex rv32si-p-sbreak.hex r TESTS := $(filter-out $(EXCLUDED_TESTS), $(ALL_TESTS)) run-simx: - $(foreach test, $(TESTS), ../../../simX/simX -r -a rv32i -c 1 -i $(test) || exit;) + $(foreach test, $(TESTS), ../../../sim/simX/simX -r -a rv32i -c 1 -i $(test) || exit;) run-rtlsim: - $(foreach test, $(TESTS), ../../../hw/simulate/obj_dir/VVortex -r $(test) || exit;) \ No newline at end of file + $(foreach test, $(TESTS), ../../../sim/rtlsim/rtlsim -r $(test) || exit;) \ No newline at end of file diff --git a/tests/runtime/fibonacci/Makefile b/tests/runtime/fibonacci/Makefile index 0eaa9592..cd5195e0 100644 --- a/tests/runtime/fibonacci/Makefile +++ b/tests/runtime/fibonacci/Makefile @@ -15,25 +15,25 @@ PROJECT = fibonacci SRCS = main.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend diff --git a/tests/runtime/hello/Makefile b/tests/runtime/hello/Makefile index c585e882..43e768b6 100644 --- a/tests/runtime/hello/Makefile +++ b/tests/runtime/hello/Makefile @@ -15,25 +15,25 @@ PROJECT = hello SRCS = main.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend diff --git a/tests/runtime/simple/Makefile b/tests/runtime/simple/Makefile index 79620a20..dabb4cc0 100644 --- a/tests/runtime/simple/Makefile +++ b/tests/runtime/simple/Makefile @@ -6,7 +6,7 @@ AR = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-gcc-ar DP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objdump CP = $(RISCV_TOOLCHAIN_PATH)/bin/riscv32-unknown-elf-objcopy -CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections +CFLAGS += -march=rv32imf -mabi=ilp32f -O3 -Wstack-usage=1024 -ffreestanding -nostartfiles -fdata-sections -ffunction-sections -fpermissive CFLAGS += -I$(VORTEX_RT_PATH)/include -I$(VORTEX_RT_PATH)/../hw LDFLAGS += -Wl,-Bstatic,-T,$(VORTEX_RT_PATH)/linker/vx_link.ld -Wl,--gc-sections $(VORTEX_RT_PATH)/libvortexrt.a @@ -15,25 +15,25 @@ PROJECT = simple SRCS = main.cpp tests.cpp -all: $(PROJECT).elf $(PROJECT).hex $(PROJECT).dump +all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump $(PROJECT).dump: $(PROJECT).elf $(DP) -D $(PROJECT).elf > $(PROJECT).dump -$(PROJECT).hex: $(PROJECT).elf - $(CP) -O ihex $(PROJECT).elf $(PROJECT).hex +$(PROJECT).bin: $(PROJECT).elf + $(CP) -O binary $(PROJECT).elf $(PROJECT).bin $(PROJECT).elf: $(SRCS) $(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf -run-rtlsim: $(PROJECT).hex - ../../../hw/simulate/obj_dir/VVortex $(PROJECT).hex +run-rtlsim: $(PROJECT).bin + ../../../sim/rtlsim/rtlsim $(PROJECT).bin -run-simx: $(PROJECT).hex - ../../../simX/simX -a rv32i -c 1 -i $(PROJECT).hex +run-simx: $(PROJECT).bin + ../../../sim/simX/simX -a rv32i -c 1 -i $(PROJECT).bin .depend: $(SRCS) $(CC) $(CFLAGS) -MM $^ > .depend; clean: - rm -rf *.elf *.hex *.dump .depend + rm -rf *.elf *.bin *.dump .depend