From 629ed3f8f94fd6025f56f88dbb5177fa93cca3ea Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Fri, 18 Oct 2019 04:15:34 -0400 Subject: [PATCH] Before ISA2.0 --- rtl/VX_back_end.v | 9 +-------- rtl/VX_fetch.v | 10 +--------- rtl/VX_front_end.v | 6 +----- rtl/VX_scheduler.v | 3 ++- rtl/Vortex.v | 7 ++----- 5 files changed, 7 insertions(+), 28 deletions(-) diff --git a/rtl/VX_back_end.v b/rtl/VX_back_end.v index 2830b1a7..f835e132 100644 --- a/rtl/VX_back_end.v +++ b/rtl/VX_back_end.v @@ -1,7 +1,6 @@ module VX_back_end ( input wire clk, input wire reset, - input wire fetch_delay, input wire schedule_delay, input wire[31:0] csr_decode_csr_data, @@ -23,12 +22,6 @@ module VX_back_end ( VX_csr_write_request_inter VX_csr_w_req ); -wire memory_delay; - -assign out_mem_delay = memory_delay; - - -wire total_freeze = fetch_delay || memory_delay; wire[11:0] execute_csr_address; wire execute_is_csr; @@ -84,7 +77,7 @@ VX_lsu load_store_unit( .VX_mem_wb (VX_mem_wb), .VX_dcache_rsp(VX_dcache_rsp), .VX_dcache_req(VX_dcache_req), - .out_delay (memory_delay) + .out_delay (out_mem_delay) ); diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index e142cd10..23ce6410 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -3,13 +3,11 @@ module VX_fetch ( input wire clk, - input wire in_memory_delay, VX_wstall_inter VX_wstall, input wire schedule_delay, VX_icache_response_inter icache_response, VX_icache_request_inter icache_request, - output wire out_delay, output wire out_ebreak, VX_jal_response_inter VX_jal_rsp, VX_branch_response_inter VX_branch_rsp, @@ -17,15 +15,11 @@ module VX_fetch ( VX_warp_ctl_inter VX_warp_ctl ); - // Inputs - wire in_freeze = out_delay || in_memory_delay; - - // Locals wire pipe_stall; - assign pipe_stall = in_freeze || schedule_delay; + assign pipe_stall = schedule_delay; wire[`NT_M1:0] thread_mask; wire[`NW_M1:0] warp_num; @@ -66,8 +60,6 @@ module VX_fetch ( ); - assign out_delay = 0; - assign icache_request.pc_address = warp_pc; assign fe_inst_meta_fd.warp_num = warp_num; assign fe_inst_meta_fd.valid = thread_mask; diff --git a/rtl/VX_front_end.v b/rtl/VX_front_end.v index d972a747..ea97d04d 100644 --- a/rtl/VX_front_end.v +++ b/rtl/VX_front_end.v @@ -4,7 +4,6 @@ module VX_front_end ( input wire clk, input wire reset, - input wire memory_delay, input wire schedule_delay, VX_warp_ctl_inter VX_warp_ctl, @@ -19,7 +18,6 @@ module VX_front_end ( output wire[11:0] decode_csr_address, - output wire fetch_delay, output wire fetch_ebreak ); @@ -33,7 +31,7 @@ VX_inst_meta_inter fd_inst_meta_de(); wire decode_branch_stall; -wire total_freeze = memory_delay || fetch_delay || schedule_delay; +wire total_freeze = schedule_delay; /* verilator lint_off UNUSED */ wire real_fetch_ebreak; @@ -45,7 +43,6 @@ VX_wstall_inter VX_wstall(); VX_fetch vx_fetch( .clk (clk), .VX_wstall (VX_wstall), - .in_memory_delay (memory_delay), .schedule_delay (schedule_delay), .VX_jal_rsp (VX_jal_rsp), .icache_response (icache_response_fe), @@ -53,7 +50,6 @@ VX_fetch vx_fetch( .icache_request (icache_request_fe), .VX_branch_rsp (VX_branch_rsp), - .out_delay (fetch_delay), .out_ebreak (real_fetch_ebreak), // fetch_ebreak .fe_inst_meta_fd (fe_inst_meta_fd) ); diff --git a/rtl/VX_scheduler.v b/rtl/VX_scheduler.v index 938b7b9c..d91f7b1c 100644 --- a/rtl/VX_scheduler.v +++ b/rtl/VX_scheduler.v @@ -4,6 +4,7 @@ module VX_scheduler ( input wire clk, + input wire memory_delay, VX_frE_to_bckE_req_inter VX_bckE_req, VX_wb_inter VX_writeback_inter, @@ -38,7 +39,7 @@ module VX_scheduler ( wire rename_valid = rs1_rename_qual || rs2_rename_qual ; - assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid); + assign schedule_delay = (rename_valid) && (|VX_bckE_req.valid) || memory_delay; always @(posedge clk) begin diff --git a/rtl/Vortex.v b/rtl/Vortex.v index 53288030..2d4c7914 100644 --- a/rtl/Vortex.v +++ b/rtl/Vortex.v @@ -43,14 +43,12 @@ assign icache_request_pc_address = icache_request_fe.pc_address; // Front-end to Back-end VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM -wire fetch_delay; // Back-end to Front-end VX_wb_inter VX_writeback_inter(); // Writeback to GPRs VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch -wire memory_delay; // CSR Buses VX_csr_write_request_inter VX_csr_w_req(); @@ -61,6 +59,7 @@ wire[11:0] decode_csr_address; VX_warp_ctl_inter VX_warp_ctl(); +wire memory_delay; wire schedule_delay; @@ -70,8 +69,6 @@ VX_front_end vx_front_end( .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req (VX_bckE_req), .decode_csr_address (decode_csr_address), - .memory_delay (memory_delay), - .fetch_delay (fetch_delay), .schedule_delay (schedule_delay), .icache_response_fe (icache_response_fe), .icache_request_fe (icache_request_fe), @@ -82,6 +79,7 @@ VX_front_end vx_front_end( VX_scheduler schedule( .clk (clk), + .memory_delay (memory_delay), .VX_bckE_req (VX_bckE_req), .VX_writeback_inter(VX_writeback_inter), .schedule_delay (schedule_delay) @@ -91,7 +89,6 @@ VX_back_end vx_back_end( .clk (clk), .reset (reset), .schedule_delay (schedule_delay), - .fetch_delay (fetch_delay), .VX_warp_ctl (VX_warp_ctl), .VX_bckE_req (VX_bckE_req), .csr_decode_csr_data (csr_decode_csr_data),