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getting dogfood tests passing on Verilator!

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This commit is contained in:
Blaise Tine
2020-08-09 18:13:12 -04:00
parent 9e0639b49f
commit 65415d2bbc
43 changed files with 748 additions and 585 deletions
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201
hw/rtl/fp_cores/VX_fp_fpga.v
View File

@@ -5,10 +5,10 @@ module VX_fp_fpga (
input wire clk,
input wire reset,
input wire in_valid,
output wire in_ready,
input wire valid_in,
output wire ready_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
@@ -21,21 +21,22 @@ module VX_fp_fpga (
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
localparam NUM_FPC = 12;
localparam FPC_BITS = `LOG2UP(NUM_FPC);
wire [NUM_FPC-1:0] core_in_ready;
wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] core_result;
wire [NUM_FPC-1:0] per_core_ready_in;
wire [NUM_FPC-1:0][`NUM_THREADS-1:0][31:0] per_core_result;
wire [NUM_FPC-1:0][`ISTAG_BITS-1:0] per_core_tag_out;
wire [NUM_FPC-1:0] per_core_ready_out;
wire [NUM_FPC-1:0] per_core_valid_out;
wire fpnew_has_fflags;
fflags_t fpnew_fflags;
wire [NUM_FPC-1:0][`ISTAG_BITS-1:0] core_out_tag;
wire [NUM_FPC-1:0] core_out_ready;
wire [NUM_FPC-1:0] core_out_valid;
reg [FPC_BITS-1:0] core_select;
reg fmadd_negate;
@@ -66,172 +67,172 @@ module VX_fp_fpga (
VX_fp_noncomp fp_noncomp (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 0)),
.in_ready (core_in_ready[0]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 0)),
.ready_in (per_core_ready_in[0]),
.tag_in (tag_in),
.op (op),
.frm (frm),
.dataa (dataa),
.datab (datab),
.result (core_result[0]),
.result (per_core_result[0]),
.has_fflags (fpnew_has_fflags),
.fflags (fpnew_fflags),
.out_tag (core_out_tag[0]),
.out_ready (core_out_ready[0]),
.out_valid (core_out_valid[0])
.tag_out (per_core_tag_out[0]),
.ready_out (per_core_ready_out[0]),
.valid_out (per_core_valid_out[0])
);
VX_fp_add fp_add (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 1)),
.in_ready (core_in_ready[1]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 1)),
.ready_in (per_core_ready_in[1]),
.tag_in (tag_in),
.dataa (dataa),
.datab (datab),
.result (core_result[1]),
.out_tag (core_out_tag[1]),
.out_ready (core_out_ready[1]),
.out_valid (core_out_valid[1])
.result (per_core_result[1]),
.tag_out (per_core_tag_out[1]),
.ready_out (per_core_ready_out[1]),
.valid_out (per_core_valid_out[1])
);
VX_fp_sub fp_sub (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 2)),
.in_ready (core_in_ready[2]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 2)),
.ready_in (per_core_ready_in[2]),
.tag_in (tag_in),
.dataa (dataa),
.datab (datab),
.result (core_result[2]),
.out_tag (core_out_tag[2]),
.out_ready (core_out_ready[2]),
.out_valid (core_out_valid[2])
.result (per_core_result[2]),
.tag_out (per_core_tag_out[2]),
.ready_out (per_core_ready_out[2]),
.valid_out (per_core_valid_out[2])
);
VX_fp_mul fp_mul (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 3)),
.in_ready (core_in_ready[3]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 3)),
.ready_in (per_core_ready_in[3]),
.tag_in (tag_in),
.dataa (dataa),
.datab (datab),
.result (core_result[3]),
.out_tag (core_out_tag[3]),
.out_ready (core_out_ready[3]),
.out_valid (core_out_valid[3])
.result (per_core_result[3]),
.tag_out (per_core_tag_out[3]),
.ready_out (per_core_ready_out[3]),
.valid_out (per_core_valid_out[3])
);
VX_fp_madd fp_madd (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 4)),
.in_ready (core_in_ready[4]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 4)),
.ready_in (per_core_ready_in[4]),
.tag_in (tag_in),
.negate (fmadd_negate),
.dataa (dataa),
.datab (datab),
.datac (datac),
.result (core_result[4]),
.out_tag (core_out_tag[4]),
.out_ready (core_out_ready[4]),
.out_valid (core_out_valid[4])
.result (per_core_result[4]),
.tag_out (per_core_tag_out[4]),
.ready_out (per_core_ready_out[4]),
.valid_out (per_core_valid_out[4])
);
VX_fp_msub fp_msub (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 5)),
.in_ready (core_in_ready[5]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 5)),
.ready_in (per_core_ready_in[5]),
.tag_in (tag_in),
.negate (fmadd_negate),
.dataa (dataa),
.datab (datab),
.datac (datac),
.result (core_result[5]),
.out_tag (core_out_tag[5]),
.out_ready (core_out_ready[5]),
.out_valid (core_out_valid[5])
.result (per_core_result[5]),
.tag_out (per_core_tag_out[5]),
.ready_out (per_core_ready_out[5]),
.valid_out (per_core_valid_out[5])
);
VX_fp_div fp_div (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 6)),
.in_ready (core_in_ready[6]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 6)),
.ready_in (per_core_ready_in[6]),
.tag_in (tag_in),
.dataa (dataa),
.datab (datab),
.result (core_result[6]),
.out_tag (core_out_tag[6]),
.out_ready (core_out_ready[6]),
.out_valid (core_out_valid[6])
.result (per_core_result[6]),
.tag_out (per_core_tag_out[6]),
.ready_out (per_core_ready_out[6]),
.valid_out (per_core_valid_out[6])
);
VX_fp_sqrt fp_sqrt (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 7)),
.in_ready (core_in_ready[7]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 7)),
.ready_in (per_core_ready_in[7]),
.tag_in (tag_in),
.dataa (dataa),
.result (core_result[7]),
.out_tag (core_out_tag[7]),
.out_ready (core_out_ready[7]),
.out_valid (core_out_valid[7])
.result (per_core_result[7]),
.tag_out (per_core_tag_out[7]),
.ready_out (per_core_ready_out[7]),
.valid_out (per_core_valid_out[7])
);
VX_fp_ftoi fp_ftoi (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 8)),
.in_ready (core_in_ready[8]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 8)),
.ready_in (per_core_ready_in[8]),
.tag_in (tag_in),
.dataa (dataa),
.result (core_result[8]),
.out_tag (core_out_tag[8]),
.out_ready (core_out_ready[8]),
.out_valid (core_out_valid[8])
.result (per_core_result[8]),
.tag_out (per_core_tag_out[8]),
.ready_out (per_core_ready_out[8]),
.valid_out (per_core_valid_out[8])
);
VX_fp_ftou fp_ftou (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 9)),
.in_ready (core_in_ready[9]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 9)),
.ready_in (per_core_ready_in[9]),
.tag_in (tag_in),
.dataa (dataa),
.result (core_result[9]),
.out_tag (core_out_tag[9]),
.out_ready (core_out_ready[9]),
.out_valid (core_out_valid[9])
.result (per_core_result[9]),
.tag_out (per_core_tag_out[9]),
.ready_out (per_core_ready_out[9]),
.valid_out (per_core_valid_out[9])
);
VX_fp_itof fp_itof (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 10)),
.in_ready (core_in_ready[10]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 10)),
.ready_in (per_core_ready_in[10]),
.tag_in (tag_in),
.dataa (dataa),
.result (core_result[10]),
.out_tag (core_out_tag[10]),
.out_ready (core_out_ready[10]),
.out_valid (core_out_valid[10])
.result (per_core_result[10]),
.tag_out (per_core_tag_out[10]),
.ready_out (per_core_ready_out[10]),
.valid_out (per_core_valid_out[10])
);
VX_fp_utof fp_utof (
.clk (clk),
.reset (reset),
.in_valid (in_valid && (core_select == 11)),
.in_ready (core_in_ready[11]),
.in_tag (in_tag),
.valid_in (valid_in && (core_select == 11)),
.ready_in (per_core_ready_in[11]),
.tag_in (tag_in),
.dataa (dataa),
.result (core_result[11]),
.out_tag (core_out_tag[11]),
.out_ready (core_out_ready[11]),
.out_valid (core_out_valid[11])
.result (per_core_result[11]),
.tag_out (per_core_tag_out[11]),
.ready_out (per_core_ready_out[11]),
.valid_out (per_core_valid_out[11])
);
wire [FPC_BITS-1:0] fp_index;
@@ -240,18 +241,18 @@ module VX_fp_fpga (
VX_priority_encoder #(
.N(NUM_FPC)
) wb_select (
.data_in (core_out_valid),
.data_in (per_core_valid_out),
.data_out (fp_index),
.valid_out (fp_valid)
);
for (i = 0; i < NUM_FPC; i++) begin
assign core_out_ready[i] = out_ready && (i == fp_index);
assign per_core_ready_out[i] = ready_out && (i == fp_index);
end
wire tmp_valid = fp_valid;
wire [`ISTAG_BITS-1:0] tmp_tag = core_out_tag[fp_index];
wire [`NUM_THREADS-1:0][31:0] tmp_result = core_result[fp_index];
wire [`ISTAG_BITS-1:0] tmp_tag = per_core_tag_out[fp_index];
wire [`NUM_THREADS-1:0][31:0] tmp_result = per_core_result[fp_index];
wire tmp_has_fflags = fpnew_has_fflags && (fp_index == 0);
fflags_t [`NUM_THREADS-1:0] tmp_flags = fpnew_fflags;
@@ -263,7 +264,7 @@ module VX_fp_fpga (
.stall (stall),
.flush (1'b0),
.in ({tmp_valid, tmp_tag, tmp_result, tmp_has_fflags, tmp_fflags}),
.out ({out_valid, out_tag, result, has_fflags, fflags})
.out ({valid_out, tag_out, result, has_fflags, fflags})
);
endmodule

20
hw/rtl/fp_cores/VX_fp_noncomp.v
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@@ -4,10 +4,10 @@ module VX_fp_noncomp (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
@@ -19,10 +19,10 @@ module VX_fp_noncomp (
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
localparam NEG_INF = 32'h00000001,
NEG_NORM = 32'h00000002,
@@ -226,8 +226,8 @@ module VX_fp_noncomp (
end
end
wire stall = ~out_ready && out_valid;
assign in_ready = ~stall;
wire stall = ~ready_out && valid_out;
assign ready_in = ~stall;
VX_generic_register #(
.N(1 + `ISTAG_BITS + (`NUM_THREADS * 32) + 1 + (`NUM_THREADS * `FFG_BITS))
@@ -236,8 +236,8 @@ module VX_fp_noncomp (
.reset (reset),
.stall (stall),
.flush (1'b0),
.in ({tmp_valid, in_tag, tmp_result, tmp_has_fflags, tmp_fflags}),
.out ({out_valid, out_tag, result, has_fflags, fflags})
.in ({tmp_valid, tag_in, tmp_result, tmp_has_fflags, tmp_fflags}),
.out ({valid_out, tag_out, result, has_fflags, fflags})
);
endmodule

58
hw/rtl/fp_cores/VX_fpnew.v
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@@ -11,10 +11,10 @@ module VX_fpnew #(
input wire clk,
input wire reset,
input wire in_valid,
output wire in_ready,
input wire valid_in,
output wire ready_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`FPU_BITS-1:0] op,
input wire [`FRM_BITS-1:0] frm,
@@ -27,10 +27,10 @@ module VX_fpnew #(
output wire has_fflags,
output fflags_t [`NUM_THREADS-1:0] fflags,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
localparam UNIT_FMULADD = FMULADD ? fpnew_pkg::PARALLEL : fpnew_pkg::DISABLED;
localparam UNIT_FDIVSQRT = FDIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;
@@ -56,17 +56,17 @@ module VX_fpnew #(
'{default: `LATENCY_FDIVSQRT}, // DIVSQRT
'{default: `LATENCY_FNONCOMP}, // NONCOMP
'{default: `LATENCY_FCONV}}, // CONV
UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL
UnitTypes:'{'{default: UNIT_FMULADD}, // ADDMUL
'{default: UNIT_FDIVSQRT}, // DIVSQRT
'{default: UNIT_FNONCOMP}, // NONCOMP
'{default: UNIT_FCONV}}, // CONV
PipeConfig: fpnew_pkg::DISTRIBUTED
};
wire fpu_in_ready, fpu_in_valid;
wire fpu_out_ready, fpu_out_valid;
wire fpu_ready_in, fpu_valid_in;
wire fpu_ready_out, fpu_valid_out;
reg [`ISTAG_BITS-1:0] fpu_in_tag, fpu_out_tag;
reg [`ISTAG_BITS-1:0] fpu_tag_in, fpu_tag_out;
reg [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
@@ -77,13 +77,13 @@ module VX_fpnew #(
wire [`NUM_THREADS-1:0][31:0] fpu_result;
fpnew_pkg::status_t [0:`NUM_THREADS-1] fpu_status;
wire is_class_op_i, is_class_op_o;
assign is_class_op_i = (op == `FPU_CLASS);
wire is_class_op, is_class_op_out;
assign is_class_op = (op == `FPU_CLASS);
reg [FOP_BITS-1:0] fpu_op;
reg [`FRM_BITS-1:0] fpu_rnd;
reg fpu_op_mod;
reg fpu_has_fflags, fpu_has_fflags_o;
reg fpu_has_fflags, fpu_has_fflags_out;
always @(*) begin
fpu_op = fpnew_pkg::SGNJ;
@@ -150,15 +150,15 @@ module VX_fpnew #(
.dst_fmt_i (fpnew_pkg::fp_format_e'(fpu_dst_fmt)),
.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
.vectorial_op_i (1'b0),
.tag_i ({fpu_in_tag, fpu_has_fflags, is_class_op_i}),
.in_valid_i (fpu_in_valid),
.in_ready_o (fpu_in_ready),
.tag_i ({fpu_tag_in, fpu_has_fflags, is_class_op}),
.in_valid_i (fpu_valid_in),
.in_ready_o (fpu_ready_in),
.flush_i (reset),
.result_o (fpu_result[0]),
.status_o (fpu_status[0]),
.tag_o ({fpu_out_tag, fpu_has_fflags_o, is_class_op_o}),
.out_valid_o (fpu_out_valid),
.out_ready_i (fpu_out_ready),
.tag_o ({fpu_tag_out, fpu_has_fflags_out, is_class_op_out}),
.out_valid_o (fpu_valid_out),
.out_ready_i (fpu_ready_out),
`UNUSED_PIN (busy_o)
);
end else begin
@@ -178,14 +178,14 @@ module VX_fpnew #(
.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
.vectorial_op_i (1'b0),
.tag_i (1'b0),
.in_valid_i (fpu_in_valid),
.in_valid_i (fpu_valid_in),
`UNUSED_PIN (in_ready_o),
.flush_i (reset),
.result_o (fpu_result[i]),
.status_o (fpu_status[i]),
`UNUSED_PIN (tag_o),
`UNUSED_PIN (out_valid_o),
.out_ready_i (fpu_out_ready),
.out_ready_i (fpu_ready_out),
`UNUSED_PIN (busy_o)
);
end
@@ -193,19 +193,19 @@ module VX_fpnew #(
`ENABLE_TRACING
assign fpu_in_valid = in_valid;
assign in_ready = fpu_in_ready
|| ~in_valid; // fix fpnews's in_ready containing in_valid;
assign fpu_valid_in = valid_in;
assign ready_in = fpu_ready_in
|| ~valid_in; // fix
assign fpu_in_tag = in_tag;
assign out_tag = fpu_out_tag;
assign fpu_tag_in = tag_in;
assign tag_out = fpu_tag_out;
assign result = fpu_result;
assign has_fflags = fpu_has_fflags_o;
assign has_fflags = fpu_has_fflags_out;
assign fflags = fpu_status;
assign out_valid = fpu_out_valid;
assign fpu_out_ready = out_ready;
assign valid_out = fpu_valid_out;
assign fpu_ready_out = ready_out;
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_add.v
View File

@@ -4,23 +4,23 @@ module VX_fp_add (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_add (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_div.v
View File

@@ -4,23 +4,23 @@ module VX_fp_div (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -42,8 +42,8 @@ module VX_fp_div (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
View File

@@ -4,22 +4,22 @@ module VX_fp_ftoi (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_ftoi (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_ftou.v
View File

@@ -4,22 +4,22 @@ module VX_fp_ftou (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_ftou (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_itof.v
View File

@@ -4,22 +4,22 @@ module VX_fp_itof (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_itof (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

22
hw/rtl/fp_cores/altera/VX_fp_madd.v
View File

@@ -4,10 +4,10 @@ module VX_fp_madd (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -16,13 +16,13 @@ module VX_fp_madd (
input wire negate,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign in_ready = enable0 && enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
@@ -119,7 +119,7 @@ module VX_fp_madd (
.clk(clk),
.reset(reset),
.enable(enable0),
.in({in_tag, (in_valid && ~negate), (in_valid && negate)}),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
@@ -134,12 +134,12 @@ module VX_fp_madd (
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~out_ready && out_valid;
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign out_valid = out_valid_st0 || out_valid_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

22
hw/rtl/fp_cores/altera/VX_fp_msub.v
View File

@@ -4,10 +4,10 @@ module VX_fp_msub (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
@@ -16,13 +16,13 @@ module VX_fp_msub (
input wire negate,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire enable0, enable1;
assign in_ready = enable0 && enable1;
assign ready_in = enable0 && enable1;
wire [`NUM_THREADS-1:0][31:0] result_st0, result_st1;
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
@@ -119,7 +119,7 @@ module VX_fp_msub (
.clk(clk),
.reset(reset),
.enable(enable0),
.in({in_tag, (in_valid && ~negate), (in_valid && negate)}),
.in ({tag_in, (valid_in && ~negate), (valid_in && negate)}),
.out({out_tag_st0, out_valid_st0, in_valid_st0})
);
@@ -134,12 +134,12 @@ module VX_fp_msub (
.out({out_tag_st1, out_valid_st1})
);
wire out_stall = ~out_ready && out_valid;
wire out_stall = ~ready_out && valid_out;
assign enable0 = ~out_stall;
assign enable1 = ~out_stall && ~(out_valid_st0 && out_valid_st1); // stall the negate stage if dual outputs
assign result = out_valid_st0 ? result_st0 : result_st1;
assign out_tag = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign out_valid = out_valid_st0 || out_valid_st1;
assign tag_out = out_valid_st0 ? out_tag_st0 : out_tag_st1;
assign valid_out = out_valid_st0 || out_valid_st1;
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_mul.v
View File

@@ -4,23 +4,23 @@ module VX_fp_mul (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_mul (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
View File

@@ -4,22 +4,22 @@ module VX_fp_sqrt (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_sqrt (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_sub.v
View File

@@ -4,23 +4,23 @@ module VX_fp_sub (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
input wire [`NUM_THREADS-1:0][31:0] datab,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -73,8 +73,8 @@ module VX_fp_sub (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule

20
hw/rtl/fp_cores/altera/VX_fp_utof.v
View File

@@ -4,22 +4,22 @@ module VX_fp_utof (
input wire clk,
input wire reset,
output wire in_ready,
input wire in_valid,
output wire ready_in,
input wire valid_in,
input wire [`ISTAG_BITS-1:0] in_tag,
input wire [`ISTAG_BITS-1:0] tag_in,
input wire [`NUM_THREADS-1:0][31:0] dataa,
output wire [`NUM_THREADS-1:0][31:0] result,
output wire [`ISTAG_BITS-1:0] out_tag,
output wire [`ISTAG_BITS-1:0] tag_out,
input wire out_ready,
output wire out_valid
input wire ready_out,
output wire valid_out
);
wire stall = ~out_ready && out_valid;
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
assign in_ready = enable;
assign ready_in = enable;
genvar i;
@@ -40,8 +40,8 @@ module VX_fp_utof (
.clk(clk),
.reset(reset),
.enable(enable),
.in({in_tag, in_valid}),
.out({out_tag, out_valid})
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
);
endmodule