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pipeline refactoring - fmax >= 222 mhz

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This commit is contained in:
Blaise Tine
2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
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4
hw/rtl/fp_cores/VX_fp_fpga.v
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@@ -41,8 +41,6 @@ module VX_fp_fpga (
reg [FPC_BITS-1:0] core_select;
reg fmadd_negate;
genvar i;
always @(*) begin
core_select = 0;
fmadd_negate = 0;
@@ -246,7 +244,7 @@ module VX_fp_fpga (
.valid_out (fp_valid)
);
for (i = 0; i < NUM_FPC; i++) begin
for (genvar i = 0; i < NUM_FPC; i++) begin
assign per_core_ready_out[i] = ready_out && (i == fp_index);
end

14
hw/rtl/fp_cores/VX_fp_noncomp.v
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@@ -48,10 +48,8 @@ module VX_fp_noncomp (
reg [`NUM_THREADS-1:0][31:0] fcmp_res; // result of comparison
reg [`NUM_THREADS-1:0][ 4:0] fcmp_excp; // exception of comparison
genvar i;
// Setup
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
assign a_sign[i] = dataa[i][31];
assign a_exponent[i] = dataa[i][30:23];
assign a_mantissa[i] = dataa[i][22:0];
@@ -77,7 +75,7 @@ module VX_fp_noncomp (
end
// FCLASS
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin
if (a_type[i].is_normal) begin
fclass_mask[i] = a_sign[i] ? NEG_NORM : POS_NORM;
@@ -101,7 +99,7 @@ module VX_fp_noncomp (
end
// Min/Max
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin
if (a_type[i].is_nan && b_type[i].is_nan)
fminmax_res[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN
@@ -120,7 +118,7 @@ module VX_fp_noncomp (
end
// Sign Injection
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin
case (op)
`FPU_SGNJ: fsgnj_res[i] = { b_sign[i], a_exponent[i], a_mantissa[i]};
@@ -132,7 +130,7 @@ module VX_fp_noncomp (
end
// Comparison
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin
case (frm)
`FRM_RNE: begin
@@ -193,7 +191,7 @@ module VX_fp_noncomp (
endcase
end
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
always @(*) begin
tmp_valid = 1'b1;
case (op)

7
hw/rtl/fp_cores/VX_fpnew.v
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@@ -129,11 +129,9 @@ module VX_fpnew #(
endcase
end
genvar i;
`DISABLE_TRACING
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
if (0 == i) begin
fpnew_top #(
.Features (FPU_FEATURES),
@@ -194,8 +192,7 @@ module VX_fpnew #(
`ENABLE_TRACING
assign fpu_valid_in = valid_in;
assign ready_in = fpu_ready_in
|| ~valid_in; // fix
assign ready_in = fpu_ready_in;
assign fpu_tag_in = tag_in;
assign tag_out = fpu_tag_out;

4
hw/rtl/fp_cores/altera/VX_fp_add.v
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@@ -22,9 +22,7 @@ module VX_fp_add (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_div.v
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@@ -22,9 +22,7 @@ module VX_fp_div (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_div fdiv (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_ftoi.v
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@@ -21,9 +21,7 @@ module VX_fp_ftoi (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_ftoi ftoi (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_ftou.v
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@@ -21,9 +21,7 @@ module VX_fp_ftou (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_ftou ftou (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_itof.v
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@@ -21,9 +21,7 @@ module VX_fp_itof (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_itof itof (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_madd.v
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@@ -28,9 +28,7 @@ module VX_fp_madd (
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_msub.v
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@@ -28,9 +28,7 @@ module VX_fp_msub (
wire [`ISTAG_BITS-1:0] out_tag_st0, out_tag_st1;
wire in_valid_st0, out_valid_st0, out_valid_st1;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys0 (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_mul.v
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@@ -22,9 +22,7 @@ module VX_fp_mul (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_sqrt.v
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@@ -21,9 +21,7 @@ module VX_fp_sqrt (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_sqrt fsqrt (
.clk (clk),
.areset (1'b0),

4
hw/rtl/fp_cores/altera/VX_fp_sub.v
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@@ -22,9 +22,7 @@ module VX_fp_sub (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
twentynm_fp_mac mac_fp_wys (
// inputs
.accumulate(),

4
hw/rtl/fp_cores/altera/VX_fp_utof.v
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@@ -21,9 +21,7 @@ module VX_fp_utof (
wire enable = ~stall;
assign ready_in = enable;
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
acl_fp_utof utof (
.clk (clk),
.areset (1'b0),