From 73d102afed40286597aac4ecd322b8c5a95691a9 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Wed, 15 Sep 2021 04:49:24 -0700
Subject: [PATCH] minor fix

---
 hw/rtl/cache/VX_bank.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v
index 4e4a9801..a1f0f9db 100644
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -221,7 +221,7 @@ module VX_bank #(
         .data_in  ({
             flush_fire || mshr_fire || mem_rsp_fire || creq_fire,
             flush_enable,
-            mshr_valid,
+            mshr_enable,
             mrsq_enable,
             creq_enable && ~creq_rw,
             creq_enable && creq_rw,
@@ -278,7 +278,7 @@ module VX_bank #(
     );
 
     // we have a core request hit
-    wire miss_st0 = (is_read_st0 || is_write_st0) && ~tag_match_st0;
+    assign miss_st0 = (is_read_st0 || is_write_st0) && ~tag_match_st0;
 
     wire [MSHR_ADDR_WIDTH-1:0] mshr_id_a_st0 = (is_read_st0 || is_write_st0) ? mshr_alloc_id : mshr_id_st0;