diff --git a/.gitignore b/.gitignore
index 64d30ed8..e69de29b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,39 +0,0 @@
-*.o
-src/harptool
-src/lex.yy.cc
-src/libharplib.a
-src/libharplib.so
-*.bin
-src/test/2thread.4b.d
-src/test/2thread.4b.out
-src/test/2thread.d
-src/test/2thread.out
-src/test/bubble.4b.d
-src/test/bubble.4b.out
-src/test/bubble.d
-src/test/bubble.out
-src/test/diverge.d
-src/test/diverge.out
-src/test/dotprod.4b.d
-src/test/dotprod.4b.out
-src/test/dotprod.d
-src/test/dotprod.out
-src/test/lfsr.4b.out
-src/test/lfsr.d
-src/test/lfsr.out
-src/test/matmul-mt.d
-src/test/matmul-mt.out
-src/test/matmul.4b.d
-src/test/matmul.4b.out
-src/test/matmul.d
-src/test/matmul.out
-src/test/sieve.4b.d
-src/test/sieve.4b.out
-src/test/sieve.d
-src/test/sieve.out
-src/test/simple.4b.d
-src/test/simple.4b.out
-src/test/simple.d
-src/test/simple.out
-util/bin2mif
-
diff --git a/TODO b/TODO
index 3ca24e06..f4c1926d 100644
--- a/TODO
+++ b/TODO
@@ -2,4 +2,5 @@
 
 
 * csri bug?
-* Start on the Verilog Pipeline (Research loading into mem)
\ No newline at end of file
+* Add hardware threads to rtl
+* Add hardware warps to rtl
\ No newline at end of file
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diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
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diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
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