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pipeline refactoring: centralized issue buffer

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This commit is contained in:
Blaise Tine
2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
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5
hw/simulate/simulator.cpp
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@@ -11,7 +11,7 @@ double sc_time_stamp() {
Simulator::Simulator() {
// force random values for unitialized signals
Verilated::randReset(1);
Verilated::randReset(2);
// Turn off assertion before reset
Verilated::assertOn(false);
@@ -24,7 +24,8 @@ Simulator::Simulator() {
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC;
trace_ = new VerilatedVcdC();
trace_->set_time_unit("1ns");
vortex_->trace(trace_, 99);
trace_->open("trace.vcd");
#endif