From 7f7d17d17677b29aff523ae4cd45bd3648c94c39 Mon Sep 17 00:00:00 2001 From: "Lyons, Ethan Tyler" Date: Wed, 13 Nov 2019 10:06:36 -0500 Subject: [PATCH] Shared Memory Implemented --- rtl/shared_memory/VX_shared_memory.v | 81 ++++++++++++++++------ rtl/shared_memory/VX_shared_memory_block.v | 61 +++++++++++----- 2 files changed, 100 insertions(+), 42 deletions(-) diff --git a/rtl/shared_memory/VX_shared_memory.v b/rtl/shared_memory/VX_shared_memory.v index 3442af86..666d46f1 100644 --- a/rtl/shared_memory/VX_shared_memory.v +++ b/rtl/shared_memory/VX_shared_memory.v @@ -2,8 +2,20 @@ module VX_shared_memory #( - parameter NB = 4, - parameter BITS_PER_BANK = 3 + parameter SM_SIZE = 4096, // Bytes + parameter SM_BANKS = 4, + parameter SM_BYTES_PER_READ = 16, + parameter SM_WORDS_PER_READ = 4, + parameter SM_LOG_WORDS_PER_READ = 2, + parameter SM_HEIGHT = 128, // Bytes + parameter SM_BANK_OFFSET_START = 2, + parameter SM_BANK_OFFSET_END = 4, + parameter SM_BLOCK_OFFSET_START = 5, + parameter SM_BLOCK_OFFSET_END = 6, + parameter SM_INDEX_START = 7, + parameter SM_INDEX_END = 13, + parameter NUM_REQ = 4, + parameter BITS_PER_BANK = 3 ) ( //INPUTS @@ -20,21 +32,29 @@ module VX_shared_memory output wire stall ); -reg[NB:0][31:0] temp_address; -reg[NB:0][31:0] temp_in_data; -reg[NB:0] temp_in_valid; +//reg[NB:0][31:0] temp_address; +//reg[NB:0][31:0] temp_in_data; +//reg[NB:0] temp_in_valid; +reg[SM_BANKS - 1:0][31:0] temp_address; +reg[SM_BANKS - 1:0][31:0] temp_in_data; +reg[SM_BANKS - 1:0] temp_in_valid; reg[`NT_M1:0] temp_out_valid; reg[`NT_M1:0][31:0] temp_out_data; -reg [NB:0][6:0] block_addr; -reg [NB:0][3:0][31:0] block_wdata; -reg [NB:0][3:0][31:0] block_rdata; -reg [NB:0][1:0] block_we; +//reg [NB:0][6:0] block_addr; +//reg [NB:0][3:0][31:0] block_wdata; +//reg [NB:0][3:0][31:0] block_rdata; +//reg [NB:0][1:0] block_we; +reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr; +reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata; +reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata; +reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ:0] block_we; wire send_data; -reg[NB:0][1:0] req_num; +//reg[NB:0][1:0] req_num; +reg[SM_BANKS - 1:0][$clog2(NUM_REQ) - 1:0] req_num; // not positive about this wire [`NT_M1:0] orig_in_valid; @@ -50,7 +70,8 @@ genvar f; endgenerate -VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm( +//VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm( +VX_priority_encoder_sm #(.NB(SM_BANKS - 1), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_encoder_sm( .clk(clk), .reset(reset), .in_valid(orig_in_valid), @@ -70,11 +91,18 @@ VX_priority_encoder_sm #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_priority_enc genvar j; integer i; generate -for(j=0; j<= NB; j=j+1) begin : sm_mem_block +//for(j=0; j<= NB; j=j+1) begin : sm_mem_block +for(j=0; j<= SM_BANKS - 1; j=j+1) begin wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j]; - VX_shared_memory_block vx_shared_memory_block( + VX_shared_memory_block# + ( + .SMB_HEIGHT(SM_HEIGHT), + .SMB_WORDS_PER_READ(SM_WORDS_PER_READ), + .SMB_LOG_WORDS_PER_READ(SM_LOG_WORDS_PER_READ) + ) vx_shared_memory_block + ( .clk (clk), .reset (reset), .addr (block_addr[j]), @@ -83,19 +111,20 @@ for(j=0; j<= NB; j=j+1) begin : sm_mem_block .shm_write(shm_write), .data_out (block_rdata[j]) ); -end +end always @(*) begin block_addr = 0; block_we = 0; block_wdata = 0; - for(i = 0; i <= NB; i = i+1) begin + //for(i = 0; i <= NB; i = i+1) begin + for(i = 0; i <= SM_BANKS - 1; i = i+1) begin if(temp_in_valid[i] == 1'b1) begin //1. Check if the request is actually to the shared memory if((temp_address[i][31:24]) == 8'hFF) begin // STORES - if(mem_write != `NO_MEM_WRITE) begin + if(mem_write != `NO_MEM_WRITE) begin if(mem_write == `SB_MEM_WRITE) begin //TODO end @@ -103,13 +132,16 @@ always @(*) begin //TODO end else if(mem_write == `SW_MEM_WRITE) begin - block_addr[i] = temp_address[i][13:7]; - block_we[i] = temp_address[i][6:5]; - block_wdata[i][temp_address[i][6:5]] = temp_in_data[i]; + //block_addr[i] = temp_address[i][13:7]; + //block_we[i] = temp_address[i][6:5]; + //block_wdata[i][temp_address[i][6:5]] = temp_in_data[i]; + block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; + block_we[i] = temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]; + block_wdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]] = temp_in_data[i]; end end //LOADS - else if(mem_read != `NO_MEM_READ) begin + else if(mem_read != `NO_MEM_READ) begin if(mem_read == `LB_MEM_READ) begin //TODO end @@ -119,8 +151,11 @@ always @(*) begin end else if (mem_read == `LW_MEM_READ) begin - block_addr[i] = temp_address[i][13:7]; - temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]]; + //block_addr[i] = temp_address[i][13:7]; + //temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][6:5]]; + //temp_out_valid[req_num[i]] = 1'b1; + block_addr[i] = temp_address[i][SM_INDEX_END:SM_INDEX_START]; + temp_out_data[req_num[i]] = block_rdata[i][temp_address[i][SM_BLOCK_OFFSET_END:SM_BLOCK_OFFSET_START]]; temp_out_valid[req_num[i]] = 1'b1; end else if (mem_read == `LBU_MEM_READ) @@ -140,4 +175,4 @@ end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/rtl/shared_memory/VX_shared_memory_block.v b/rtl/shared_memory/VX_shared_memory_block.v index ab52d539..4f142bf0 100644 --- a/rtl/shared_memory/VX_shared_memory_block.v +++ b/rtl/shared_memory/VX_shared_memory_block.v @@ -1,50 +1,73 @@ -module VX_shared_memory_block ( +module VX_shared_memory_block +#( + parameter SMB_SIZE = 4096, // Bytes + parameter SMB_BYTES_PER_READ = 16, + parameter SMB_WORDS_PER_READ = 4, + parameter SMB_LOG_WORDS_PER_READ = 2, + parameter SMB_HEIGHT = 128, // Bytes + parameter BITS_PER_BANK = 3 +) +( input wire clk, // Clock input wire reset, - input wire[6:0] addr, - input wire[3:0][31:0] wdata, - input wire[1:0] we, - input wire shm_write, + //input wire[6:0] addr, + //input wire[3:0][31:0] wdata, + //input wire[1:0] we, + //input wire shm_write, + + //output wire[3:0][31:0] data_out + input wire[$clog2(SMB_HEIGHT) - 1:0] addr, + input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata, + input wire[SMB_LOG_WORDS_PER_READ-1:0] we, + input wire shm_write, + + output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out - output wire[3:0][31:0] data_out - ); `ifndef SYN - reg[3:0][31:0] shared_memory[127:0]; + //reg[3:0][31:0] shared_memory[127:0]; + reg[SMB_WORDS_PER_READ-1:0][31:0] shared_memory[SMB_HEIGHT-1:0]; //wire need_to_write = (|we); integer curr_ind; always @(posedge clk, posedge reset) begin if (reset) begin - for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) + //for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1) + for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1) begin shared_memory[curr_ind] <= 0; end end else if(shm_write) begin - if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; - if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0]; - if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0]; - if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0]; + shared_memory[addr][we][31:0] <= wdata[we][31:0]; // - Ethan's addition + //if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; + //if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0]; + //if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0]; + //if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0]; end end assign data_out = shm_write ? 0 : shared_memory[addr]; - `else + `else wire cena = 0; wire cenb = !shm_write; - wire[3:0][31:0] write_bit_mask; + //wire[3:0][31:0] write_bit_mask; - assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}}; - assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}}; - assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}}; - assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}}; + //assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}}; + integer curr_word; + for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1) + begin + assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}}; + end // Using ASIC MEM /* verilator lint_off PINCONNECTEMPTY */