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fpga fixes

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This commit is contained in:
Blaise Tine
2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
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21
hw/rtl/VX_alu_unit.v
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@@ -30,11 +30,11 @@ module VX_alu_unit (
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
.SPEED("HIGHEST"),
.REP("UNSIGNED"),
.PIPELINE(DIV_PIPELINE_LEN)
) unsigned_div (
.clock(clk),
.aclr(1'b0),
.clk(clk),
.reset(reset),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
@@ -45,13 +45,11 @@ module VX_alu_unit (
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
.NREP("SIGNED"),
.DREP("SIGNED"),
.SPEED("HIGHEST"),
.REP("SIGNED"),
.PIPELINE(DIV_PIPELINE_LEN)
) signed_div (
.clock(clk),
.aclr(1'b0),
.clk(clk),
.reset(reset),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
.denom(ALU_in2),
@@ -63,12 +61,11 @@ module VX_alu_unit (
.WIDTHA(64),
.WIDTHB(64),
.WIDTHP(64),
.SPEED("HIGHEST"),
.FORCE_LE("YES"),
.REP("UNSIGNED"),
.PIPELINE(MUL_PIPELINE_LEN)
) multiplier (
.clock(clk),
.aclr(1'b0),
.clk(clk),
.reset(reset),
.clken(1'b1), // TODO this could be disabled on inactive instructions
.dataa(mul_data_a),
.datab(mul_data_b),