From 8543e3a8bfe1b63efd286256861bc655f18a5bee Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 26 Apr 2021 02:34:21 -0700 Subject: [PATCH] code refactoring --- driver/opae/vlsim/opae_sim.h | 2 -- hw/rtl/VX_config.vh | 8 ++++---- hw/rtl/VX_define.vh | 8 ++++---- hw/simulate/simulator.cpp | 8 ++++---- hw/simulate/simulator.h | 2 +- hw/unit_tests/cache/cachesim.cpp | 10 +++++----- hw/unit_tests/cache/cachesim.h | 2 +- 7 files changed, 19 insertions(+), 21 deletions(-) diff --git a/driver/opae/vlsim/opae_sim.h b/driver/opae/vlsim/opae_sim.h index 76e5f435..ee4f022a 100644 --- a/driver/opae/vlsim/opae_sim.h +++ b/driver/opae/vlsim/opae_sim.h @@ -17,8 +17,6 @@ #include #include -#define MEM_BLOCK_SIZE (PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8) - #define CACHE_BLOCK_SIZE 64 class opae_sim { diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 2b2727fc..2f7bfe07 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -33,11 +33,11 @@ `define SM_ENABLE 1 `endif -`ifndef GLOBAL_BLOCK_SIZE -`ifdef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH - `define GLOBAL_BLOCK_SIZE (`PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH / 8) +`ifndef MEM_BLOCK_SIZE +`ifdef LOCAL_MEM_DATA_N_BYTES + `define MEM_BLOCK_SIZE `LOCAL_MEM_DATA_N_BYTES `else - `define GLOBAL_BLOCK_SIZE 64 + `define MEM_BLOCK_SIZE 64 `endif `endif diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 79de9b8f..b9ef4014 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -243,7 +243,7 @@ `define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0) // Block size in bytes -`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE) +`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE) // Word size in bytes `define IWORD_SIZE 4 @@ -275,7 +275,7 @@ `define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1) // Block size in bytes -`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `GLOBAL_BLOCK_SIZE) +`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE) // Word size in bytes `define DWORD_SIZE 4 @@ -324,7 +324,7 @@ `define L2CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID) // Block size in bytes -`define L2CACHE_LINE_SIZE `GLOBAL_BLOCK_SIZE +`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE // Word size in bytes `define L2WORD_SIZE `DCACHE_LINE_SIZE @@ -350,7 +350,7 @@ `define L3CACHE_ID 0 // Block size in bytes -`define L3CACHE_LINE_SIZE `GLOBAL_BLOCK_SIZE +`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE // Word size in bytes `define L3WORD_SIZE `L2CACHE_LINE_SIZE diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index e19aaacd..86156b94 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -144,7 +144,7 @@ void Simulator::eval_mem_bus() { if (!mem_rsp_active_) { if (mem_rsp_it != mem_rsp_vec_.end()) { vortex_->mem_rsp_valid = 1; - memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), GLOBAL_BLOCK_SIZE); + memcpy((uint8_t*)vortex_->mem_rsp_data, mem_rsp_it->block.data(), MEM_BLOCK_SIZE); vortex_->mem_rsp_tag = mem_rsp_it->tag; mem_rsp_vec_.erase(mem_rsp_it); mem_rsp_active_ = true; @@ -169,9 +169,9 @@ void Simulator::eval_mem_bus() { if (vortex_->mem_req_valid) { if (vortex_->mem_req_rw) { uint64_t byteen = vortex_->mem_req_byteen; - unsigned base_addr = (vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE); + unsigned base_addr = (vortex_->mem_req_addr * MEM_BLOCK_SIZE); uint8_t* data = (uint8_t*)(vortex_->mem_req_data); - for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { (*ram_)[base_addr + i] = data[i]; } @@ -180,7 +180,7 @@ void Simulator::eval_mem_bus() { mem_req_t mem_req; mem_req.tag = vortex_->mem_req_tag; mem_req.addr = vortex_->mem_req_addr; - ram_->read(vortex_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.block.data()); + ram_->read(vortex_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.block.data()); mem_req.cycles_left = MEM_LATENCY; for (auto& rsp : mem_rsp_vec_) { if (mem_req.addr == rsp.addr) { diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index f800e643..80e2fa42 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -48,7 +48,7 @@ private: typedef struct { int cycles_left; - std::array block; + std::array block; uint32_t addr; uint32_t tag; } mem_req_t; diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp index 528a5dfe..951740d8 100644 --- a/hw/unit_tests/cache/cachesim.cpp +++ b/hw/unit_tests/cache/cachesim.cpp @@ -208,7 +208,7 @@ void CacheSim::eval_mem_bus() { cache_->mem_rsp_valid = 1; //copy data from the rsp queue to the cache module - memcpy((uint8_t*)cache_->mem_rsp_data, mem_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); + memcpy((uint8_t*)cache_->mem_rsp_data, mem_rsp_vec_[dequeue_index].data, MEM_BLOCK_SIZE); cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag; free(mem_rsp_vec_[dequeue_index].data); //take data out of the queue @@ -235,9 +235,9 @@ void CacheSim::eval_mem_bus() { if (cache_->mem_req_valid) { if (cache_->mem_req_rw) { //write = 1 uint64_t byteen = cache_->mem_req_byteen; - unsigned base_addr = (cache_->mem_req_addr * GLOBAL_BLOCK_SIZE); + unsigned base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE); uint8_t* data = (uint8_t*)(cache_->mem_req_data); - for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { + for (int i = 0; i < MEM_BLOCK_SIZE; i++) { if ((byteen >> i) & 0x1) { (*ram_)[base_addr + i] = data[i]; } @@ -245,9 +245,9 @@ void CacheSim::eval_mem_bus() { } else { mem_req_t mem_req; mem_req.cycles_left = MEM_LATENCY; - mem_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); + mem_req.data = (uint8_t*)malloc(MEM_BLOCK_SIZE); mem_req.tag = cache_->mem_req_tag; - ram_->read(cache_->mem_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, mem_req.data); + ram_->read(cache_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data); mem_rsp_vec_.push_back(mem_req); } } diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h index 2a4be624..72cc44f9 100644 --- a/hw/unit_tests/cache/cachesim.h +++ b/hw/unit_tests/cache/cachesim.h @@ -18,7 +18,7 @@ #define MEM_LATENCY 100 #define MEM_RQ_SIZE 16 #define MEM_STALLS_MODULO 16 -#define GLOBAL_BLOCK_SIZE 16 +#define MEM_BLOCK_SIZE 16 typedef struct { int cycles_left;