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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
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16
hw/rtl/libs/VX_generic_queue.v
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@@ -10,13 +10,13 @@ module VX_generic_queue #(
output wire empty,
output wire full,
`IGNORE_WARNINGS_END
input wire [DATAW-1:0] data_i,
output wire [DATAW-1:0] data_o
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (SIZE == 0) begin
assign empty = 1;
assign data_o = data_i;
assign data_out = data_in;
assign full = 0;
end else begin // (SIZE > 0)
@@ -49,12 +49,12 @@ module VX_generic_queue #(
end
if (writing) begin
head_r <= data_i;
head_r <= data_in;
end
end
end
assign data_o = head_r;
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
@@ -99,7 +99,7 @@ module VX_generic_queue #(
always @(posedge clk) begin
if (writing) begin
data[wr_ctr_r] <= data_i;
data[wr_ctr_r] <= data_in;
end
end
@@ -121,12 +121,12 @@ module VX_generic_queue #(
end
bypass_r <= writing && (empty_r || (1 == size_r) && reading);
curr_r <= data_i;
curr_r <= data_in;
head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r];
end
end
assign data_o = bypass_r ? curr_r : head_r;
assign data_out = bypass_r ? curr_r : head_r;
assign empty = empty_r;
assign full = full_r;
end

15
hw/rtl/libs/VX_generic_stack.v
View File

@@ -1,10 +1,8 @@
module VX_generic_stack
#(
parameter WIDTH = 40,
parameter DEPTH = 2
)
(
module VX_generic_stack #(
parameter WIDTH = 40,
parameter DEPTH = 2
) (
input wire clk,
input wire reset,
input wire push,
@@ -12,8 +10,7 @@ module VX_generic_stack
input reg [WIDTH - 1:0] q1,
input reg [WIDTH - 1:0] q2,
output wire[WIDTH - 1:0] d
);
);
reg [DEPTH - 1:0] ptr;
reg [WIDTH - 1:0] stack [0:(1 << DEPTH) - 1];
@@ -30,10 +27,8 @@ module VX_generic_stack
end else if (pop) begin
ptr <= ptr - 1;
end
end
assign d = stack[ptr - 1];
endmodule

6
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -2,9 +2,9 @@
module VX_priority_encoder (
input wire[`NUM_WARPS-1:0] valids,
output reg[`NW_BITS-1:0] index,
output reg found
);
output reg[`NW_BITS-1:0] index,
output reg found
);
integer i;
always @(*) begin

18
hw/rtl/libs/VX_priority_encoder_w_mask.v
View File

@@ -1,16 +1,14 @@
`include "VX_define.vh"
module VX_priority_encoder_w_mask
#(
parameter N = 10
)
(
input wire[N-1:0] valids,
output reg [N-1:0] mask,
module VX_priority_encoder_w_mask #(
parameter N = 10
) (
input wire[N-1:0] valids,
output reg [N-1:0] mask,
//output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
//output reg[`LOG2UP(N):0] index, // eh
output reg found
);
output reg found
);
integer i;
always @(valids) begin