RTL code refactoring

2020-04-20 14:05:08 -04:00
parent 1a2823da0d
commit 8e7046a388
15 changed files with 53 additions and 484 deletions
--- a/hw/rtl/libs/VX_priority_encoder.v
+++ b/hw/rtl/libs/VX_priority_encoder.v
@@ -2,9 +2,9 @@

 module VX_priority_encoder (
    input  wire[`NUM_WARPS-1:0] valids,
-    output reg[`NW_BITS-1:0] index,
-    output reg           found
-  );
+    output reg[`NW_BITS-1:0] 	index,
+    output reg           		found
+);

 	integer i;
 	always @(*) begin