fpga build refactoring

ci/regression.sh

@@ -21,15 +21,17 @@ make -s
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
 ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
 
-# Build tests disabling extensions
+# disabling M extension
 CONFIGS=-DEXT_M_DISABLE make -C hw/simulate
+
+# disabling F extension
 CONFIGS=-DEXT_F_DISABLE make -C hw/simulate
 
 # disable shared memory
 CONFIGS=-DSM_ENABLE=0 make -C hw/simulate
 
+# using FPNEW core
+FPU_CORE=FPU_FPNEW ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
+
 # test 128-bit DRAM bus
 CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS=4 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo
-
-# test 256-bit DRAM bus
-CONFIGS=-DPLATFORM_PARAM_LOCAL_MEMORY_DATA_SIZE_BITS=4 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo

driver/opae/vlsim/Makefile

@@ -82,8 +82,9 @@ endif
 VL_FLAGS += -DNOPAE
 CFLAGS += -DNOPAE
 
-# use DPI FPU
+# FPU backend
-VL_FLAGS += -DFPU_DPI
+FPU_CORE ?= FPU_DPI
+VL_FLAGS += -D$(FPU_CORE)
 
 PROJECT = libopae-c-vlsim.so
 

driver/rtlsim/Makefile

@@ -68,8 +68,9 @@ ifdef PERF
 	CFLAGS += -DPERF_ENABLE
 endif
 
-# use DPI FPU
+# FPU backend
-VL_FLAGS += -DFPU_DPI
+FPU_CORE ?= FPU_DPI
+VL_FLAGS += -D$(FPU_CORE)
 
 PROJECT = libvortex.so
 # PROJECT = libvortex.dylib

hw/rtl/afu/vortex_afu.sv

@@ -12,8 +12,6 @@ import ccip_if_pkg::*;
 import local_mem_cfg_pkg::*;
 /* verilator lint_on IMPORTSTAR */
 
-`define MEM_BLOCK_SIZE LOCAL_MEM_DATA_N_BYTES
-
 `include "VX_define.vh"
 
 module vortex_afu #(

hw/simulate/Makefile

@@ -49,8 +49,9 @@ VL_FLAGS += verilator.vlt
 VL_FLAGS += --exe $(SRCS) $(RTL_INCLUDE)
 VL_FLAGS += --cc Vortex.v --top-module $(TOP)
 
-# Use FPNEW PFU core
+# FPU backend
-VL_FLAGS += -DFPU_FPNEW
+FPU_CORE ?= FPU_DPI
+VL_FLAGS += -D$(FPU_CORE)
 
 DBG_FLAGS += -DVCD_OUTPUT
 

hw/syn/opae/Makefile

@@ -1,11 +1,14 @@
 ASE_BUILD_DIR ?= build_ase
 FPGA_BUILD_DIR ?= build_fpga
+DEVICE_FAMILY ?= arria10
 RTL_DIR=../../rtl
 
-ifdef $(shell [[ '$(FPGA_CLASS)' =~ 'fpga-pac-s10' ]] && echo matched)
+ifeq ($(DEVICE_FAMILY),arria10)
-	DEVICE_FAMILY ?= stratix10
+	CFLAGS += -DMEM_BLOCK_SIZE=64
-else
+endif
-	DEVICE_FAMILY ?= arria10
+
+ifeq ($(DEVICE_FAMILY),stratix10)
+	CFLAGS += -DMEM_BLOCK_SIZE=16
 endif
 
 ifeq ($(shell which qsub-synth),)
@@ -14,22 +17,106 @@ else
 	RUN_SYNTH=qsub-synth
 endif
 
+# control RTL debug print states
+DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE  
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK 
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG
+DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA
+DBG_PRINT_FLAGS += -DDBG_PRINT_MEM
+DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
+DBG_PRINT_FLAGS += -DDBG_PRINT_AVS
+DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
+
+DBG_FLAGS += $(DBG_PRINT_FLAGS)
+DBG_FLAGS += -DDBG_CACHE_REQ_INFO
+
+CONFIG1  := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG2  := -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG4  := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG8  := -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG16 := -DNUM_CLUSTERS=4 -DNUM_CORES=4 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG32 := -DNUM_CLUSTERS=4 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+CONFIG64 := -DNUM_CLUSTERS=8 -DNUM_CORES=8 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS)
+
+FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)
+RTL_INCLUDE = -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/afu
+
+CFLAGS += $(RTL_INCLUDE)
+
+# Debugigng
+ifdef DEBUG
+	CFLAGS += $(DBG_FLAGS)
+else    
+	CFLAGS += -DNDEBUG
+endif
+
+# Enable scope analyzer
+ifdef SCOPE
+	CFLAGS += -DSCOPE
+endif
+
+# Enable perf counters
+ifdef PERF
+	CFLAGS += -DPERF_ENABLE
+endif
+
 all: ase-1c
 
-gen-sources:
+$(ASE_BUILD_DIR)_1c/Makefile:
-	./gen_sources.sh $(DEVICE_FAMILY) > sources.txt
+	afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_1c
 
-ase-1c: gen-sources setup-ase-1c 
+$(ASE_BUILD_DIR)_2c/Makefile:
-	make -C $(ASE_BUILD_DIR)_1c
+	afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_2c
-	cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
 
-ase-2c: gen-sources setup-ase-2c
+$(ASE_BUILD_DIR)_4c/Makefile:
-	make -C $(ASE_BUILD_DIR)_2c
+	afu_sim_setup -s setup.cfg $(ASE_BUILD_DIR)_4c
-	cp $(RTL_DIR)/fp_cores/altera/arria$(DEVICE_FAMILY)10/*.hex $(ASE_BUILD_DIR)_2c/work
 
-ase-4c: gen-sources setup-ase-4c
+$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
-	make -C $(ASE_BUILD_DIR)_4c
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_1c
-	cp $(RTL_DIR)/fp_cores/altera/arria10/*.hex $(ASE_BUILD_DIR)_4c/work
+
+$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_2c
+
+$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c
+
+$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c
+
+$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c
+
+$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c
+
+$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
+	afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c
+
+gen-sources-1c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt
+
+gen-sources-2c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG2) > sources.txt
+
+gen-sources-4c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG4) > sources.txt
+
+gen-sources-8c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG8) > sources.txt
+
+gen-sources-16c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG16) > sources.txt
+
+gen-sources-32c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG32) > sources.txt
+
+gen-sources-64c:
+	./gen_sources.sh $(CFLAGS) $(CONFIG64) > sources.txt
+
+# setup
 
 setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
 
@@ -37,36 +124,6 @@ setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
 
 setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
 
-$(ASE_BUILD_DIR)_1c/Makefile:
-	afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
-
-$(ASE_BUILD_DIR)_2c/Makefile:
-	afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
-
-$(ASE_BUILD_DIR)_4c/Makefile:
-	afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
-
-fpga-1c: gen-sources setup-fpga-1c
-	cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
-
-fpga-2c: gen-sources setup-fpga-2c
-	cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
-
-fpga-4c: gen-sources setup-fpga-4c
-	cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
-
-fpga-8c: gen-sources setup-fpga-8c
-	cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
-
-fpga-16c: gen-sources setup-fpga-16c
-	cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
-
-fpga-32c: gen-sources setup-fpga-32c
-	cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
-
-fpga-64c: gen-sources setup-fpga-64c
-	cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
-	
 setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
 
 setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
@@ -81,35 +138,42 @@ setup-fpga-32c: $(FPGA_BUILD_DIR)_32c/build/dcp.qpf
 
 setup-fpga-64c: $(FPGA_BUILD_DIR)_64c/build/dcp.qpf
 
-$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
+# build
-	afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
 
-$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
+ase-1c: gen-sources-1c setup-ase-1c
-	afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
+	make -C $(ASE_BUILD_DIR)_1c
+	cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_1c/work
 
-$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
+ase-2c: gen-sources-2c setup-ase-2c
-	afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
+	make -C $(ASE_BUILD_DIR)_2c
+	cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_2c/work
 
-$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
+ase-4c: gen-sources-4c setup-ase-4c
-	afu_synth_setup -s sources_8c.txt $(FPGA_BUILD_DIR)_8c
+	make -C $(ASE_BUILD_DIR)_4c
+	cp $(RTL_DIR)/fp_cores/altera/$(DEVICE_FAMILY)/*.hex $(ASE_BUILD_DIR)_4c/work
 
-$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
+fpga-1c: gen-sources-1c setup-fpga-1c
-	afu_synth_setup -s sources_16c.txt $(FPGA_BUILD_DIR)_16c
+	cd $(FPGA_BUILD_DIR)_1c && $(RUN_SYNTH)
 
-$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
+fpga-2c: gen-sources-2c setup-fpga-2c
-	afu_synth_setup -s sources_32c.txt $(FPGA_BUILD_DIR)_32c
+	cd $(FPGA_BUILD_DIR)_2c && $(RUN_SYNTH)
 
-$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
+fpga-4c: gen-sources-4c setup-fpga-4c
-	afu_synth_setup -s sources_64c.txt $(FPGA_BUILD_DIR)_64c
+	cd $(FPGA_BUILD_DIR)_4c && $(RUN_SYNTH)
 
-run-ase-1c:
+fpga-8c: gen-sources-8c setup-fpga-8c
-	cd $(ASE_BUILD_DIR)_1c && make sim
+	cd $(FPGA_BUILD_DIR)_8c && $(RUN_SYNTH)
 
-run-ase-2c:
+fpga-16c: gen-sources-16c setup-fpga-16c
-	cd $(ASE_BUILD_DIR)_2c && make sim
+	cd $(FPGA_BUILD_DIR)_16c && $(RUN_SYNTH)
 
-run-ase-4c:
+fpga-32c: gen-sources-32c setup-fpga-32c
-	cd $(ASE_BUILD_DIR)_4c && make sim
+	cd $(FPGA_BUILD_DIR)_32c && $(RUN_SYNTH)
+
+fpga-64c: gen-sources-64c setup-fpga-64c
+	cd $(FPGA_BUILD_DIR)_64c && $(RUN_SYNTH)
+
+# cleanup
 
 clean-ase-1c:
 	rm -rf $(ASE_BUILD_DIR)_1c sources.txt

hw/syn/opae/README

@@ -97,15 +97,4 @@ tar -xvf vortex.vcd.tar.bz2
 lsof +D build_ase_1c
 
 # quick off synthesis
-make -C unittest clean && make -C unittest > unittest/build.log 2>&1 &
+make core
-make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
-make -C cache clean && make -C cache > cache/build.log 2>&1 &
-make -C core clean && make -C core > core/build.log 2>&1 &
-make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
-make -C top1 clean && make -C top1 > top1/build.log 2>&1 &
-make -C top2 clean && make -C top2 > top2/build.log 2>&1 &
-make -C top4 clean && make -C top4 > top4/build.log 2>&1 &
-make -C top8 clean && make -C top8 > top8/build.log 2>&1 &
-make -C top16 clean && make -C top16 > top16/build.log 2>&1 &
-make -C top32 clean && make -C top32 > top32/build.log 2>&1 &
-make -C top64 clean && make -C top64 > top64/build.log 2>&1 &

hw/syn/opae/gen_sources.sh

@@ -1,14 +1,37 @@
 #!/bin/bash
 
-rtl_dir="../../rtl"
 exclude_list="VX_fpu_fpnew.v"
-file_list=""
+macros=()
-device_family=$1
+includes=()
 
-add_dirs()
+# parse command arguments
-{
+while getopts D:I:h flag
-    for dir in $*; do
+do
+  case "${flag}" in
+    D) macros+=( ${OPTARG} );;
+    I) includes+=( ${OPTARG} );;
+    h) echo "Usage: [-D macro] [-I include] [-h help]"
+       exit 0
+    ;;
+  \?)
+    echo "Invalid option: -$OPTARG" 1>&2
+    exit 1
+    ;;
+  esac
+done
+
+# dump macros
+for value in ${macros[@]}; do
+    echo "+define+$value"
+done
+
+# dump include directories
+for dir in ${includes[@]}; do
     echo "+incdir+$dir"
+done
+
+# dump source files
+for dir in ${includes[@]}; do
     for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
         exclude=0
         for fe in $exclude_list; do
@@ -17,24 +40,7 @@ add_dirs()
             fi
         done
         if [[ $exclude == 0 ]]; then
-                file_list="$file_list $file"
+            echo $file
         fi
     done
-    done
-}
-
-add_files()
-{
-    for file in $*; do
-        file_list="$file_list $file"
-    done
-}
-
-add_dirs $rtl_dir/fp_cores/altera/$device_family
-
-add_dirs $rtl_dir/libs $rtl_dir/interfaces $rtl_dir/fp_cores $rtl_dir/cache $rtl_dir $rtl_dir/afu
-
-# dump file list
-for file in $file_list; do
-    echo $file
 done

hw/syn/opae/setup.cfg

@@ -1,8 +1,5 @@
-+define+NUM_CORES=4
-
 +define+SYNTHESIS
 +define+QUARTUS
-#+define+PERF_ENABLE
 
 vortex_afu.json
 QI:vortex_afu.qsf

hw/syn/opae/sources_16c.txt

@@ -1,12 +0,0 @@
-+define+NUM_CORES=4
-+define+NUM_CLUSTERS=4
-#+define+L3_ENABLE=1
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+PERF_ENABLE
-
-vortex_afu16.json
-QI:vortex_afu.qsf
-
-C:sources.txt

hw/syn/opae/sources_1c.txt

@@ -1,24 +0,0 @@
-+define+NUM_CORES=1
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+SCOPE
-#+define+PERF_ENABLE
-
-#+define+DBG_PRINT_CORE_ICACHE
-#+define+DBG_PRINT_CORE_DCACHE
-#+define+DBG_PRINT_CACHE_BANK
-#+define+DBG_PRINT_CACHE_MSHR
-#+define+DBG_PRINT_CACHE_TAG
-#+define+DBG_PRINT_CACHE_DATA
-#+define+DBG_PRINT_DRAM
-#+define+DBG_PRINT_PIPELINE
-#+define+DBG_PRINT_OPAE
-#+define+DBG_PRINT_AVS
-#+define+DBG_PRINT_SCOPE
-#+define+DBG_CACHE_REQ_INFO
-
-vortex_afu.json
-QI:vortex_afu.qsf
-
-C:sources.txt

hw/syn/opae/sources_2c.txt

@@ -1,10 +0,0 @@
-+define+NUM_CORES=2
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+PERF_ENABLE
-
-vortex_afu.json
-QI:vortex_afu.qsf
-
-C:sources.txt

hw/syn/opae/sources_32c.txt

@@ -1,12 +0,0 @@
-+define+NUM_CORES=8
-+define+NUM_CLUSTERS=4
-#+define+L3_ENABLE=1
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+PERF_ENABLE
-
-vortex_afu.json
-QI:vortex_afu.qsf
-
-C:sources.txt

hw/syn/opae/sources_64c.txt

@@ -1,12 +0,0 @@
-+define+NUM_CORES=8
-+define+NUM_CLUSTERS=8
-#+define+L3_ENABLE=1
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+PERF_ENABLE
-
-vortex_afu.json
-QI:vortex_afu.qsf
-
-C:sources.txt

hw/syn/opae/sources_8c.txt

@@ -1,12 +0,0 @@
-+define+NUM_CORES=4
-+define+NUM_CLUSTERS=2
-#+define+L3_ENABLE=1
-
-+define+SYNTHESIS
-+define+QUARTUS
-#+define+PERF_ENABLE
-
-vortex_afu8.json
-QI:vortex_afu.qsf
-
-C:sources.txt