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RAM blocks inference fixes

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This commit is contained in:
Blaise Tine
2020-11-30 14:02:47 -08:00
parent 5758ef9ebf
commit 97739e9dcf
27 changed files with 218 additions and 189 deletions
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6
hw/rtl/fp_cores/VX_fp_addmul.v
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@@ -178,14 +178,14 @@ module VX_fp_addmul #(
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1 + 1),
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FADDMUL)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in({tag_in, valid_in, do_sub, do_mul}),
.out({tag_out, valid_out, do_sub_r, do_mul_r})
.in({valid_in, tag_in, do_sub, do_mul}),
.out({valid_out, tag_out, do_sub_r, do_mul_r})
);
assign ready_in = enable;

6
hw/rtl/fp_cores/VX_fp_div.v
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@@ -50,14 +50,14 @@ module VX_fp_div #(
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FDIV)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
.in ({valid_in, tag_in}),
.out({valid_out, tag_out})
);
assign ready_in = enable;

6
hw/rtl/fp_cores/VX_fp_ftoi.v
View File

@@ -68,14 +68,14 @@ module VX_fp_ftoi #(
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1),
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_FTOI)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in, is_signed}),
.out({tag_out, valid_out, is_signed_r})
.in ({valid_in, tag_in, is_signed}),
.out({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

6
hw/rtl/fp_cores/VX_fp_itof.v
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@@ -68,14 +68,14 @@ module VX_fp_itof #(
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1),
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_ITOF)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in, is_signed}),
.out({tag_out, valid_out, is_signed_r})
.in ({valid_in, tag_in, is_signed}),
.out({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

6
hw/rtl/fp_cores/VX_fp_madd.v
View File

@@ -138,14 +138,14 @@ module VX_fp_madd #(
end
VX_shift_register #(
.DATAW(TAGW + 1 + 1 + 1),
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FMADD)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in({tag_in, valid_in, do_sub, do_neg}),
.out({tag_out, valid_out, do_sub_r, do_neg_r})
.in({valid_in, tag_in, do_sub, do_neg}),
.out({valid_out, tag_out, do_sub_r, do_neg_r})
);
assign ready_in = enable;

6
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -48,14 +48,14 @@ module VX_fp_sqrt #(
end
VX_shift_register #(
.DATAW(TAGW + 1),
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FSQRT)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.in ({tag_in, valid_in}),
.out({tag_out, valid_out})
.in ({valid_in, tag_in}),
.out({valid_out, tag_out})
);
assign ready_in = enable;

2
hw/rtl/fp_cores/VX_fpnew.v
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@@ -78,7 +78,7 @@ module VX_fpnew
wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32;
wire [`NUM_THREADS-1:0][31:0] fpu_result;
fpnew_pkg::status_t [0:`NUM_THREADS-1] fpu_status;
fpnew_pkg::status_t [`NUM_THREADS-1:0] fpu_status;
reg [FOP_BITS-1:0] fpu_op;
reg [`FRM_BITS-1:0] fpu_rnd;