From 9b186dcc6e4e4e3a86e0e3e1b1020a07c042ba0c Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 2 Jun 2020 05:32:50 -0700 Subject: [PATCH] fixed L2 cache --- hw/opae/README | 2 +- hw/opae/sources.txt | 15 ++++++------ hw/rtl/cache/VX_bank.v | 38 +++++++++++++++++------------- hw/rtl/cache/VX_cache_config.vh | 6 ++--- hw/rtl/cache/VX_cache_miss_resrv.v | 4 ++-- hw/rtl/cache/VX_tag_data_access.v | 18 ++++++++------ 6 files changed, 46 insertions(+), 37 deletions(-) diff --git a/hw/opae/README b/hw/opae/README index ffcf562b..d5aadd97 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -82,4 +82,4 @@ ps -u tinebp kill -9 # fixing device resource busy issue when deleting /build_ase/ -lsof +D build_ase \ No newline at end of file +- \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 83a93aca..7b75973f 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -7,6 +7,7 @@ vortex_afu.json +define+NUM_CORES=2 +define+NUM_WARPS=4 +define+NUM_THREADS=4 ++define+L2_ENABLE=0 +define+DNUM_BANKS=4 +define+INUM_BANKS=1 @@ -16,13 +17,13 @@ vortex_afu.json +define+IDFPQ_SIZE=16 +define+SDFPQ_SIZE=0 -+define+DBG_PRINT_CORE_ICACHE -+define+DBG_PRINT_CORE_DCACHE -+define+DBG_PRINT_CACHE_BANK -+define+DBG_PRINT_CACHE_SNP -+define+DBG_PRINT_CACHE_MSRQ -+define+DBG_PRINT_DRAM -+define+DBG_PRINT_OPAE +#+define+DBG_PRINT_CORE_ICACHE +#+define+DBG_PRINT_CORE_DCACHE +#+define+DBG_PRINT_CACHE_BANK +#+define+DBG_PRINT_CACHE_SNP +#+define+DBG_PRINT_CACHE_MSRQ +#+define+DBG_PRINT_DRAM +#+define+DBG_PRINT_OPAE +incdir+. +incdir+../rtl diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index f0280aff..1ff01d33 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -230,7 +230,7 @@ module VX_bank #( wire mrvq_valid_st0; wire[`REQS_BITS-1:0] mrvq_tid_st0; wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0; - wire [`WORD_SELECT_WIDTH-1:0] mrvq_wsel_st0; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] mrvq_wsel_st0; wire [`WORD_WIDTH-1:0] mrvq_writeword_st0; wire [`REQ_TAG_WIDTH-1:0] mrvq_tag_st0; wire mrvq_rw_st0; @@ -287,7 +287,7 @@ module VX_bank #( wire qual_is_fill_st0; wire qual_valid_st0; wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0; - wire [`WORD_SELECT_WIDTH-1:0] qual_wsel_st0; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] qual_wsel_st0; wire qual_from_mrvq_st0; wire [`WORD_WIDTH-1:0] qual_writeword_st0; @@ -298,7 +298,7 @@ module VX_bank #( wire valid_st1 [STAGE_1_CYCLES-1:0]; wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0]; - wire [`WORD_SELECT_WIDTH-1:0] wsel_st1 [STAGE_1_CYCLES-1:0]; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st1 [STAGE_1_CYCLES-1:0]; wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0]; wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0]; wire [`BANK_LINE_WIDTH-1:0] writedata_st1 [STAGE_1_CYCLES-1:0]; @@ -313,18 +313,22 @@ module VX_bank #( mrvq_pop_unqual ? mrvq_addr_st0 : reqq_pop_unqual ? reqq_req_addr_st0[`LINE_SELECT_ADDR_RNG] : snrq_pop_unqual ? snrq_addr_st0 : - 0; - - assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] : - mrvq_pop_unqual ? mrvq_wsel_st0 : - 0; + 0; + if (`WORD_SELECT_WIDTH != 0) begin + assign qual_wsel_st0 = reqq_pop_unqual ? reqq_req_addr_st0[`WORD_SELECT_WIDTH-1:0] : + mrvq_pop_unqual ? mrvq_wsel_st0 : + 0; + end else begin + `UNUSED_VAR(mrvq_wsel_st0) + assign qual_wsel_st0 = 0; + end assign qual_writedata_st0 = dfpq_pop_unqual ? dfpq_filldata_st0 : 57; assign qual_inst_meta_st0 = mrvq_pop_unqual ? {`REQ_TAG_WIDTH'(mrvq_tag_st0) , mrvq_rw_st0, mrvq_byteen_st0, mrvq_tid_st0} : reqq_pop_unqual ? {`REQ_TAG_WIDTH'(reqq_req_tag_st0), reqq_req_rw_st0, reqq_req_byteen_st0, reqq_req_tid_st0} : snrq_pop_unqual ? {`REQ_TAG_WIDTH'(snrq_tag_st0), 1'b0, WORD_SIZE'(0), `REQS_BITS'(0)} : - 0; + 0; assign qual_going_to_write_st0 = dfpq_pop_unqual ? 1 : (mrvq_pop_unqual && mrvq_rw_st0) ? 1 : @@ -333,11 +337,11 @@ module VX_bank #( assign qual_is_snp_st0 = mrvq_pop_unqual ? mrvq_is_snp_st0 : snrq_pop_unqual ? 1 : - 0; + 0; assign qual_writeword_st0 = mrvq_pop_unqual ? mrvq_writeword_st0 : reqq_pop_unqual ? reqq_req_writeword_st0 : - 0; + 0; assign qual_from_mrvq_st0 = mrvq_pop_unqual; @@ -348,7 +352,7 @@ module VX_bank #( ) VX_generic_register #( - .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) + .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_c0 ( .clk (clk), .reset (reset), @@ -361,7 +365,7 @@ module VX_bank #( genvar i; for (i = 1; i < STAGE_1_CYCLES; i++) begin VX_generic_register #( - .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) + .N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + `BANK_LINE_WIDTH) ) s0_1_cc ( .clk (clk), .reset(reset), @@ -428,7 +432,7 @@ module VX_bank #( .valid_req_st1e (valid_st1e), .writefill_st1e (is_fill_st1[STAGE_1_CYCLES-1]), .writeaddr_st1e (addr_st1[STAGE_1_CYCLES-1]), - .writewsel_st1e (wsel_st1[STAGE_1_CYCLES-1]), + .wordsel_st1e (wsel_st1[STAGE_1_CYCLES-1]), .writeword_st1e (writeword_st1[STAGE_1_CYCLES-1]), .writedata_st1e (writedata_st1[STAGE_1_CYCLES-1]), @@ -458,7 +462,7 @@ module VX_bank #( wire from_mrvq_st1e_st2 = from_mrvq_st1e && !is_snp_st1e; wire valid_st2; - wire [`WORD_SELECT_WIDTH-1:0] wsel_st2; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] wsel_st2; wire [`WORD_WIDTH-1:0] writeword_st2; wire [`WORD_WIDTH-1:0] readword_st2; wire [`BANK_LINE_WIDTH-1:0] readdata_st2; @@ -478,7 +482,7 @@ module VX_bank #( wire mrvq_init_ready_state_hazard_st1e_st1; VX_generic_register #( - .N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_WIDTH + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH) + .N(1+ 1+ 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_WIDTH) + `WORD_WIDTH + `WORD_WIDTH + `BANK_LINE_WIDTH + `TAG_SELECT_BITS + 1 + 1 + BANK_LINE_SIZE + `REQ_INST_META_WIDTH) ) st_1e_2 ( .clk (clk), .reset(reset), @@ -512,7 +516,7 @@ module VX_bank #( assign recover_mrvq_state_st2 = miss_add && from_mrvq_st2; wire [`LINE_ADDR_WIDTH-1:0] miss_add_addr = addr_st2; - wire [`WORD_SELECT_WIDTH-1:0] miss_add_wsel = wsel_st2; + wire [`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel = wsel_st2; wire [`WORD_WIDTH-1:0] miss_add_data = writeword_st2; assign {miss_add_tag, miss_add_rw, miss_add_byteen, miss_add_tid} = inst_meta_st2; wire miss_add_is_snp = is_snp_st2; diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index 52af265e..7d163a73 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -8,8 +8,8 @@ // tag rw byteen tid `define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS) -// data metadata word_sel is_snp -`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `WORD_SELECT_WIDTH + 1) +// data metadata word_sel is_snp +`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1) `define REQS_BITS `LOG2UP(NUM_REQUESTS) @@ -48,7 +48,7 @@ `define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) `define TAG_SELECT_ADDR_END 31 -`define WORD_SELECT_WIDTH `LOG2UP(`BANK_LINE_WORDS) +`define WORD_SELECT_WIDTH `CLOG2(`BANK_LINE_WORDS) `define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE)) diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index 260b0098..23631381 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -25,7 +25,7 @@ module VX_cache_miss_resrv #( input wire miss_add, input wire from_mrvq, input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr, - input wire[`WORD_SELECT_WIDTH-1:0] miss_add_wsel, + input wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_add_wsel, input wire[`WORD_WIDTH-1:0] miss_add_data, input wire[`REQS_BITS-1:0] miss_add_tid, input wire[`REQ_TAG_WIDTH-1:0] miss_add_tag, @@ -46,7 +46,7 @@ module VX_cache_miss_resrv #( input wire miss_resrv_pop, output wire miss_resrv_valid_st0, output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0, - output wire[`WORD_SELECT_WIDTH-1:0] miss_resrv_wsel_st0, + output wire[`UP(`WORD_SELECT_WIDTH)-1:0] miss_resrv_wsel_st0, output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0, output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, output wire[`REQ_TAG_WIDTH-1:0] miss_resrv_tag_st0, diff --git a/hw/rtl/cache/VX_tag_data_access.v b/hw/rtl/cache/VX_tag_data_access.v index 97397e1c..00279c0f 100644 --- a/hw/rtl/cache/VX_tag_data_access.v +++ b/hw/rtl/cache/VX_tag_data_access.v @@ -38,7 +38,7 @@ module VX_tag_data_access #( `IGNORE_WARNINGS_BEGIN input wire mem_rw_st1e, input wire[WORD_SIZE-1:0] mem_byteen_st1e, - input wire[`WORD_SELECT_WIDTH-1:0] writewsel_st1e, + input wire[`UP(`WORD_SELECT_WIDTH)-1:0] wordsel_st1e, `IGNORE_WARNINGS_END output wire[`WORD_WIDTH-1:0] readword_st1e, @@ -141,7 +141,11 @@ module VX_tag_data_access #( assign use_read_dirtyb_st1e= read_dirtyb_st1c[STAGE_1_CYCLES-1]; assign use_read_data_st1e = read_data_st1c[STAGE_1_CYCLES-1]; - assign readword_st1e = use_read_data_st1e[writewsel_st1e * `WORD_WIDTH +: `WORD_WIDTH]; + if (`WORD_SELECT_WIDTH != 0) begin + assign readword_st1e = use_read_data_st1e[wordsel_st1e * `WORD_WIDTH +: `WORD_WIDTH]; + end else begin + assign readword_st1e = use_read_data_st1e; + end wire [`BANK_LINE_WORDS-1:0][WORD_SIZE-1:0] we; wire [`BANK_LINE_WIDTH-1:0] data_write; @@ -150,15 +154,15 @@ module VX_tag_data_access #( && valid_req_st1e && use_read_valid_st1e && !miss_st1e - && !is_snp_st1e; + && !is_snp_st1e + && !real_writefill; for (i = 0; i < `BANK_LINE_WORDS; i++) begin - wire normal_write = ((writewsel_st1e == `WORD_SELECT_WIDTH'(i)) || (`BANK_LINE_WORDS == 1)) - && should_write - && !real_writefill; + wire normal_write = ((`WORD_SELECT_WIDTH == 0) || (wordsel_st1e == `UP(`WORD_SELECT_WIDTH)'(i))) + && should_write; assign we[i] = real_writefill ? {WORD_SIZE{1'b1}} : - normal_write ? mem_byteen_st1e: + normal_write ? mem_byteen_st1e : {WORD_SIZE{1'b0}}; assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = real_writefill ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : writeword_st1e;