diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 99d3cbb6..c8c17734 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ endif SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache -I../../hw/rtl/shared_memory -I../../hw/rtl/pipe_regs +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache VL_FLAGS += -DNDEBUG --assert -Wall -Wpedantic diff --git a/hw/Makefile b/hw/Makefile index 42c94001..7f7d0ef4 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -4,7 +4,7 @@ CF += -std=c++11 -fms-extensions VF += -compiler gcc --language 1800-2009 --assert -Wall -Wpedantic -INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/shared_memory -I./rtl/simulate +INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate SINGLE_CORE = Vortex.v diff --git a/hw/modelsim/Makefile b/hw/modelsim/Makefile index 409d5600..16cec83a 100644 --- a/hw/modelsim/Makefile +++ b/hw/modelsim/Makefile @@ -71,10 +71,6 @@ SRC = \ ../rtl/cache/VX_cache_data_per_index.v \ ../rtl/pipe_regs/VX_d_e_reg.v \ ../rtl/pipe_regs/VX_f_d_reg.v \ -../rtl/shared_memory/VX_bank_valids.v \ -../rtl/shared_memory/VX_priority_encoder_sm.v \ -../rtl/shared_memory/VX_shared_memory.v \ -../rtl/shared_memory/VX_shared_memory_block.v \ ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 4017ec31..267a752c 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -4,12 +4,10 @@ vortex_afu.json +incdir+. +incdir+../rtl -+incdir+../rtl/shared_memory -+incdir+../rtl/cache -+incdir+../rtl/cache +incdir+../rtl/interfaces +incdir+../rtl/pipe_regs -+incdir+../rtl/compat ++incdir+../rtl/cache ++incdir+../rtl/libs ../rtl/VX_user_config.vh ../rtl/VX_config.vh @@ -96,11 +94,6 @@ vortex_afu.json ../rtl/cache/VX_tag_data_structure.v ../rtl/cache/VX_prefetcher.v -../rtl/shared_memory/VX_shared_memory_block.v -../rtl/shared_memory/VX_priority_encoder_sm.v -../rtl/shared_memory/VX_shared_memory.v -../rtl/shared_memory/VX_bank_valids.v - ../rtl/libs/VX_priority_encoder_w_mask.v ../rtl/libs/VX_generic_register.v ../rtl/libs/VX_mult.v @@ -109,7 +102,6 @@ vortex_afu.json ../rtl/libs/VX_generic_priority_encoder.v ../rtl/libs/VX_priority_encoder.v ../rtl/libs/VX_generic_queue.v -../rtl/libs/VX_generic_queue_ll.v ccip_interface_reg.sv ccip_std_afu.sv diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index d253621d..cab7ab48 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -371,7 +371,7 @@ begin avs_raq_push = avs_read; end -VX_generic_queue_ll #( +VX_generic_queue #( .DATAW($bits(t_local_mem_addr)), .SIZE(AVS_RD_QUEUE_SIZE) ) vx_rd_addr_queue ( @@ -394,7 +394,7 @@ begin avs_rdq_push = avs_readdatavalid; end -VX_generic_queue_ll #( +VX_generic_queue #( .DATAW($bits(t_local_mem_data)), .SIZE(AVS_RD_QUEUE_SIZE) ) vx_rd_data_queue ( diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 11deae12..c93a0b2d 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -118,7 +118,7 @@ module VX_bank #( assign snrq_valid_st0 = !snrq_empty; - VX_generic_queue_ll #( + VX_generic_queue #( .DATAW(32), .SIZE(SNRQ_SIZE) ) snr_queue ( @@ -140,8 +140,8 @@ module VX_bank #( assign dram_fill_rsp_ready = !dfpq_full; - VX_generic_queue_ll #( - .DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)), + VX_generic_queue #( + .DATAW(32 + (`BANK_LINE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE) ) dfp_queue ( .clk (clk), @@ -530,8 +530,8 @@ module VX_bank #( wire cwbq_empty; assign core_rsp_valid = !cwbq_empty; - VX_generic_queue_ll #( - .DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), + VX_generic_queue #( + .DATAW(`LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE) ) cwb_queue( .clk (clk), @@ -598,8 +598,8 @@ module VX_bank #( assign dram_wb_req_valid = !dwbq_empty; - VX_generic_queue_ll #( - .DATAW( 32 + (`BANK_LINE_WORDS * `WORD_SIZE)), + VX_generic_queue #( + .DATAW(32 + (`BANK_LINE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE) ) dwb_queue ( .clk (clk), @@ -620,7 +620,7 @@ module VX_bank #( assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full)); assign snp_fwd_valid = !ffsq_empty; - VX_generic_queue_ll #( + VX_generic_queue #( .DATAW(32), .SIZE(FFSQ_SIZE) ) ffs_queue ( diff --git a/hw/rtl/cache/VX_cache_dfq_queue.v b/hw/rtl/cache/VX_cache_dfq_queue.v index 592d2ea8..83024873 100644 --- a/hw/rtl/cache/VX_cache_dfq_queue.v +++ b/hw/rtl/cache/VX_cache_dfq_queue.v @@ -72,7 +72,7 @@ module VX_cache_dfq_queue #( wire push_qual = dfqq_push && !dfqq_full; wire pop_qual = dfqq_pop && use_empty && !out_empty; - VX_generic_queue_ll #( + VX_generic_queue #( .DATAW(NUM_BANKS * (1+32)), .SIZE(DFQQ_SIZE) ) dfqq_queue ( diff --git a/hw/rtl/cache/VX_cache_req_queue.v b/hw/rtl/cache/VX_cache_req_queue.v index 205e9c8c..78f5a310 100644 --- a/hw/rtl/cache/VX_cache_req_queue.v +++ b/hw/rtl/cache/VX_cache_req_queue.v @@ -115,7 +115,7 @@ module VX_cache_req_queue #( wire push_qual = reqq_push && !reqq_full; wire pop_qual = !out_empty && use_empty; - VX_generic_queue_ll #( + VX_generic_queue #( .DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE) ) reqq_queue ( diff --git a/hw/rtl/cache/VX_prefetcher.v b/hw/rtl/cache/VX_prefetcher.v index a1d4cf37..50792dbc 100644 --- a/hw/rtl/cache/VX_prefetcher.v +++ b/hw/rtl/cache/VX_prefetcher.v @@ -32,7 +32,7 @@ module VX_prefetcher #( wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid; - VX_generic_queue_ll #( + VX_generic_queue #( .DATAW(32), .SIZE(PRFQ_SIZE) ) pfq_queue ( diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 4b386543..36801156 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,41 +1,135 @@ -module VX_generic_queue #( - parameter DATAW = 4, - parameter SIZE = 277 +module VX_generic_queue #( + parameter DATAW, + parameter SIZE = 16 ) ( - input wire clk, - input wire reset, - input wire push, - input wire[DATAW-1:0] in_data, +`IGNORE_WARNINGS_BEGIN + input wire clk, + input wire reset, + input wire push, + input wire pop, + output wire empty, + output wire full, +`IGNORE_WARNINGS_END + input wire [DATAW-1:0] in_data, + output wire [DATAW-1:0] out_data +); + if (SIZE == 0) begin - input wire pop, - output wire[DATAW-1:0] out_data, - output wire empty, - output wire full -); + assign empty = 1; + assign out_data = in_data; + assign full = 0; - reg [DATAW-1:0] data [SIZE-1:0]; - reg [`LOG2UP(SIZE)-1:0] head; - reg [`LOG2UP(SIZE)-1:0] tail; + end else begin // (SIZE > 0) + + `ifdef QUEUE_FORCE_MLAB + (* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0]; + `else + reg [DATAW-1:0] data [SIZE-1:0]; + `endif - assign empty = (head == tail); - assign full = (head == (tail+1)); + reg [DATAW-1:0] head_r; + reg [`LOG2UP(SIZE+1)-1:0] size_r; + wire reading; + wire writing; - integer i; - always @(posedge clk) begin - if (reset) begin - head <= 0; - tail <= 0; - end else begin - if (push && !full) begin - data[tail] <= in_data; - tail <= tail+1; - end - if (pop && !empty) begin - head <= head + 1; - end - end - end + assign reading = pop && !empty; + assign writing = push && !full; - assign out_data = data[head]; + if (SIZE == 1) begin + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + head_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= 1; + end else if (reading && !writing) begin + size_r <= 0; + end + + if (writing) begin + head_r <= in_data; + end + end + end + + assign out_data = head_r; + assign empty = (size_r == 0); + assign full = (size_r != 0) && !pop; + + end else begin // (SIZE > 1) + + reg [DATAW-1:0] curr_r; + reg [`LOG2UP(SIZE)-1:0] wr_ctr_r; + reg [`LOG2UP(SIZE)-1:0] rd_ptr_r; + reg [`LOG2UP(SIZE)-1:0] rd_next_ptr_r; + reg empty_r; + reg full_r; + reg bypass_r; + + always @(posedge clk) begin + if (reset) begin + wr_ctr_r <= 0; + end else begin + if (writing) + wr_ctr_r <= wr_ctr_r + 1; + end + end + + always @(posedge clk) begin + if (reset) begin + size_r <= 0; + empty_r <= 1; + full_r <= 0; + end else begin + if (writing && !reading) begin + size_r <= size_r + 1; + empty_r <= 0; + if (size_r == SIZE-1) + full_r <= 1; + end else if (reading && !writing) begin + size_r <= size_r - 1; + if (size_r == 1) + empty_r <= 1; + full_r <= 0; + end + end + end + + always @(posedge clk) begin + if (writing) begin + data[wr_ctr_r] <= in_data; + end + end + + always @(posedge clk) begin + if (reset) begin + curr_r <= 0; + rd_ptr_r <= 0; + rd_next_ptr_r <= 1; + bypass_r <= 0; + end else begin + if (reading) begin + if (SIZE == 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= ~rd_next_ptr_r; + end else if (SIZE > 2) begin + rd_ptr_r <= rd_next_ptr_r; + rd_next_ptr_r <= rd_ptr_r + 2; + end + end + + bypass_r <= writing && (empty_r || (1 == size_r) && reading); + curr_r <= in_data; + head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; + end + end + + assign out_data = bypass_r ? curr_r : head_r; + assign empty = empty_r; + assign full = full_r; + end + end + endmodule \ No newline at end of file diff --git a/hw/rtl/libs/VX_generic_queue_ll.v b/hw/rtl/libs/VX_generic_queue_ll.v deleted file mode 100644 index 6bda1dbe..00000000 --- a/hw/rtl/libs/VX_generic_queue_ll.v +++ /dev/null @@ -1,135 +0,0 @@ -module VX_generic_queue_ll #( - parameter DATAW, - parameter SIZE = 16 -) ( -`IGNORE_WARNINGS_BEGIN - input wire clk, - input wire reset, - input wire push, - input wire pop, - output wire empty, - output wire full, -`IGNORE_WARNINGS_END - input wire [DATAW-1:0] in_data, - output wire [DATAW-1:0] out_data -); - if (SIZE == 0) begin - - assign empty = 1; - assign out_data = in_data; - assign full = 0; - - end else begin // (SIZE > 0) - - `ifdef QUEUE_FORCE_MLAB - (* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0]; - `else - reg [DATAW-1:0] data [SIZE-1:0]; - `endif - - reg [DATAW-1:0] head_r; - reg [`LOG2UP(SIZE+1)-1:0] size_r; - wire reading; - wire writing; - - assign reading = pop && !empty; - assign writing = push && !full; - - if (SIZE == 1) begin - - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - head_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= 1; - end else if (reading && !writing) begin - size_r <= 0; - end - - if (writing) begin - head_r <= in_data; - end - end - end - - assign out_data = head_r; - assign empty = (size_r == 0); - assign full = (size_r != 0) && !pop; - - end else begin // (SIZE > 1) - - reg [DATAW-1:0] curr_r; - reg [`LOG2UP(SIZE)-1:0] wr_ctr_r; - reg [`LOG2UP(SIZE)-1:0] rd_ptr_r; - reg [`LOG2UP(SIZE)-1:0] rd_next_ptr_r; - reg empty_r; - reg full_r; - reg bypass_r; - - always @(posedge clk) begin - if (reset) begin - wr_ctr_r <= 0; - end else begin - if (writing) - wr_ctr_r <= wr_ctr_r + 1; - end - end - - always @(posedge clk) begin - if (reset) begin - size_r <= 0; - empty_r <= 1; - full_r <= 0; - end else begin - if (writing && !reading) begin - size_r <= size_r + 1; - empty_r <= 0; - if (size_r == SIZE-1) - full_r <= 1; - end else if (reading && !writing) begin - size_r <= size_r - 1; - if (size_r == 1) - empty_r <= 1; - full_r <= 0; - end - end - end - - always @(posedge clk) begin - if (writing) begin - data[wr_ctr_r] <= in_data; - end - end - - always @(posedge clk) begin - if (reset) begin - curr_r <= 0; - rd_ptr_r <= 0; - rd_next_ptr_r <= 1; - bypass_r <= 0; - end else begin - if (reading) begin - if (SIZE == 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= ~rd_next_ptr_r; - end else if (SIZE > 2) begin - rd_ptr_r <= rd_next_ptr_r; - rd_next_ptr_r <= rd_ptr_r + 2; - end - end - - bypass_r <= writing && (empty_r || (1 == size_r) && reading); - curr_r <= in_data; - head_r <= data[reading ? rd_next_ptr_r : rd_ptr_r]; - end - end - - assign out_data = bypass_r ? curr_r : head_r; - assign empty = empty_r; - assign full = full_r; - end - end - -endmodule \ No newline at end of file diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index a8844494..14aa9150 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -57,7 +57,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache;../shared_memory" + $(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../libs;../interfaces;../pipe_regs;../cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/yosys/synthesis.ys b/hw/syn/yosys/synthesis.ys index c04a41e3..fd208160 100644 --- a/hw/syn/yosys/synthesis.ys +++ b/hw/syn/yosys/synthesis.ys @@ -1,5 +1,5 @@ # load design -read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/cache -I../../rtl/shared_memory -I../../rtl/pipe_regs ../../rtl/Vortex.v +read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v # high-level synthesis proc; opt; fsm;; memory -nomap; opt diff --git a/hw/rtl/libs/VX_divide_tb.v b/hw/unit_tests/VX_divide_tb.v similarity index 100% rename from hw/rtl/libs/VX_divide_tb.v rename to hw/unit_tests/VX_divide_tb.v diff --git a/hw/unit_tests/generic_queue/testbench.v b/hw/unit_tests/generic_queue/testbench.v index b2dc8720..3eb57648 100644 --- a/hw/unit_tests/generic_queue/testbench.v +++ b/hw/unit_tests/generic_queue/testbench.v @@ -1,5 +1,5 @@ `timescale 1ns/1ns -`include "VX_generic_queue_ll.v" +`include "VX_generic_queue.v" `define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y) @@ -14,7 +14,7 @@ module testbench(); wire full; wire empty; - VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut ( + VX_generic_queue #(.DATAW(4), .SIZE(4)) dut ( .clk(clk), .reset(reset), .in_data(in_data), diff --git a/simX/cache_simX.v b/simX/cache_simX.v index 72059baf..1b10ab0e 100644 --- a/simX/cache_simX.v +++ b/simX/cache_simX.v @@ -1,5 +1,5 @@ -`include "../old_rtl/VX_define.v" +`include "VX_define.v" module cache_simX ( input wire clk, // Clock