wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

minor updates

Browse Source
This commit is contained in:
Blaise Tine
2021-01-16 14:05:47 -08:00
parent 4f26228d50
commit a56ecb696d
2 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/rtl/cache/VX_cache.v vendored
View File

@@ -200,7 +200,7 @@ module VX_cache #(
// Core WB // Core WB
assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i]; assign curr_bank_core_rsp_ready = per_bank_core_rsp_ready[i];
assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid; assign per_bank_core_rsp_valid[i] = curr_bank_core_rsp_valid;
assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid; assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag; assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data; assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;

1
hw/rtl/cache/VX_shared_mem.v vendored
View File

@@ -136,6 +136,7 @@ module VX_shared_mem #(
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (NUM_BANKS * (1 + `REQS_BITS + 1 + WORD_SIZE + `LINE_SELECT_BITS + `WORD_WIDTH + CORE_TAG_WIDTH)), .DATAW (NUM_BANKS * (1 + `REQS_BITS + 1 + WORD_SIZE + `LINE_SELECT_BITS + `WORD_WIDTH + CORE_TAG_WIDTH)),
.SIZE (CREQ_SIZE), .SIZE (CREQ_SIZE),
.BUFFERED (1),
.FASTRAM (1) .FASTRAM (1)
) core_req_queue ( ) core_req_queue (
.clk (clk), .clk (clk),