set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

2020-06-29 08:03:19 -07:00
parent d33916f1e0
commit a70562d386
8 changed files with 40 additions and 11 deletions
--- a/hw/rtl/VX_alu_unit.v
+++ b/hw/rtl/VX_alu_unit.v
@@ -13,8 +13,8 @@ module VX_alu_unit (
    output reg [31:0]  alu_result,
    output reg         alu_stall
 );
-    localparam DIV_PIPELINE_LEN = 20;
-    localparam MUL_PIPELINE_LEN = 8;
+    localparam DIV_PIPELINE_LEN = 18;
+    localparam MUL_PIPELINE_LEN = 1;

    wire[31:0] div_result_unsigned;
    wire[31:0] div_result_signed;