From ab63ac9e5deeedb172545d336ad46a1f254c49f4 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 10 Feb 2021 20:55:04 -0800 Subject: [PATCH] cache request interfaces update --- hw/rtl/VX_core.v | 71 ++++++------ hw/rtl/VX_databus_arb.v | 12 +- hw/rtl/VX_define.vh | 3 - hw/rtl/VX_execute.v | 4 +- hw/rtl/VX_fetch.v | 4 +- hw/rtl/VX_icache_stage.v | 24 ++-- hw/rtl/VX_lsu_unit.v | 26 ++--- hw/rtl/VX_mem_unit.v | 44 ++++---- hw/rtl/VX_pipeline.v | 72 ++++++------ hw/rtl/cache/VX_cache_config.vh | 2 + hw/rtl/cache/VX_cache_core_req_bank_sel.v | 106 ++++++++++++++---- hw/rtl/cache/VX_shared_mem.v | 10 +- hw/rtl/interfaces/VX_cache_core_rsp_if.v | 20 ---- ..._core_req_if.v => VX_dcache_core_req_if.v} | 6 +- hw/rtl/interfaces/VX_dcache_core_rsp_if.v | 20 ++++ hw/rtl/interfaces/VX_icache_core_req_if.v | 19 ++++ hw/rtl/interfaces/VX_icache_core_rsp_if.v | 19 ++++ hw/rtl/interfaces/VX_lsu_req_if.v | 2 +- hw/syn/quartus/project.tcl | 3 +- 19 files changed, 275 insertions(+), 192 deletions(-) delete mode 100644 hw/rtl/interfaces/VX_cache_core_rsp_if.v rename hw/rtl/interfaces/{VX_cache_core_req_if.v => VX_dcache_core_req_if.v} (86%) create mode 100644 hw/rtl/interfaces/VX_dcache_core_rsp_if.v create mode 100644 hw/rtl/interfaces/VX_icache_core_req_if.v create mode 100644 hw/rtl/interfaces/VX_icache_core_rsp_if.v diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 19f53d86..47f23d59 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -70,33 +70,31 @@ module VX_core #( //-- - VX_cache_core_req_if #( + VX_dcache_core_req_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_req_if(); + ) dcache_core_req_if(); - VX_cache_core_rsp_if #( + VX_dcache_core_rsp_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_rsp_if(); + ) dcache_core_rsp_if(); - VX_cache_core_req_if #( - .NUM_REQS(`INUM_REQUESTS), + VX_icache_core_req_if #( .WORD_SIZE(`IWORD_SIZE), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) - ) core_icache_req_if(); + ) icache_core_req_if(); - VX_cache_core_rsp_if #( - .NUM_REQS(`INUM_REQUESTS), + VX_icache_core_rsp_if #( .WORD_SIZE(`IWORD_SIZE), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) - ) core_icache_rsp_if(); + ) icache_core_rsp_if(); VX_pipeline #( .CORE_ID(CORE_ID) @@ -110,34 +108,31 @@ module VX_core #( .reset(reset), // Dcache core request - .dcache_req_valid (core_dcache_req_if.valid), - .dcache_req_rw (core_dcache_req_if.rw), - .dcache_req_byteen (core_dcache_req_if.byteen), - .dcache_req_addr (core_dcache_req_if.addr), - .dcache_req_data (core_dcache_req_if.data), - .dcache_req_tag (core_dcache_req_if.tag), - .dcache_req_ready (core_dcache_req_if.ready), + .dcache_req_valid (dcache_core_req_if.valid), + .dcache_req_rw (dcache_core_req_if.rw), + .dcache_req_byteen (dcache_core_req_if.byteen), + .dcache_req_addr (dcache_core_req_if.addr), + .dcache_req_data (dcache_core_req_if.data), + .dcache_req_tag (dcache_core_req_if.tag), + .dcache_req_ready (dcache_core_req_if.ready), // Dcache core reponse - .dcache_rsp_valid (core_dcache_rsp_if.valid), - .dcache_rsp_data (core_dcache_rsp_if.data), - .dcache_rsp_tag (core_dcache_rsp_if.tag), - .dcache_rsp_ready (core_dcache_rsp_if.ready), + .dcache_rsp_valid (dcache_core_rsp_if.valid), + .dcache_rsp_data (dcache_core_rsp_if.data), + .dcache_rsp_tag (dcache_core_rsp_if.tag), + .dcache_rsp_ready (dcache_core_rsp_if.ready), - // Dcache core request - .icache_req_valid (core_icache_req_if.valid), - .icache_req_rw (core_icache_req_if.rw), - .icache_req_byteen (core_icache_req_if.byteen), - .icache_req_addr (core_icache_req_if.addr), - .icache_req_data (core_icache_req_if.data), - .icache_req_tag (core_icache_req_if.tag), - .icache_req_ready (core_icache_req_if.ready), + // Icache core request + .icache_req_valid (icache_core_req_if.valid), + .icache_req_addr (icache_core_req_if.addr), + .icache_req_tag (icache_core_req_if.tag), + .icache_req_ready (icache_core_req_if.ready), - // Dcache core reponse - .icache_rsp_valid (core_icache_rsp_if.valid), - .icache_rsp_data (core_icache_rsp_if.data), - .icache_rsp_tag (core_icache_rsp_if.tag), - .icache_rsp_ready (core_icache_rsp_if.ready), + // Icache core reponse + .icache_rsp_valid (icache_core_rsp_if.valid), + .icache_rsp_data (icache_core_rsp_if.data), + .icache_rsp_tag (icache_core_rsp_if.tag), + .icache_rsp_ready (icache_core_rsp_if.ready), // CSR request .csr_req_valid (csr_req_valid), @@ -170,12 +165,12 @@ module VX_core #( .reset (reset), // Core <-> Dcache - .core_dcache_req_if (core_dcache_req_if), - .core_dcache_rsp_if (core_dcache_rsp_if), + .dcache_core_req_if (dcache_core_req_if), + .dcache_core_rsp_if (dcache_core_rsp_if), // Core <-> Icache - .core_icache_req_if (core_icache_req_if), - .core_icache_rsp_if (core_icache_rsp_if), + .icache_core_req_if (icache_core_req_if), + .icache_core_rsp_if (icache_core_rsp_if), // DRAM .dram_req_if (dram_req_if), diff --git a/hw/rtl/VX_databus_arb.v b/hw/rtl/VX_databus_arb.v index c3c4934a..26549c2c 100644 --- a/hw/rtl/VX_databus_arb.v +++ b/hw/rtl/VX_databus_arb.v @@ -5,18 +5,18 @@ module VX_databus_arb ( input wire reset, // input request - VX_cache_core_req_if core_req_if, + VX_dcache_core_req_if core_req_if, // output requests - VX_cache_core_req_if cache_req_if, - VX_cache_core_req_if smem_req_if, + VX_dcache_core_req_if cache_req_if, + VX_dcache_core_req_if smem_req_if, // input responses - VX_cache_core_rsp_if cache_rsp_if, - VX_cache_core_rsp_if smem_rsp_if, + VX_dcache_core_rsp_if cache_rsp_if, + VX_dcache_core_rsp_if smem_rsp_if, // output response - VX_cache_core_rsp_if core_rsp_if + VX_dcache_core_rsp_if core_rsp_if ); localparam SMEM_ASHIFT = `CLOG2(`SHARED_MEM_BASE_ADDR_ALIGN); localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE); diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 407bd223..841c5076 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -259,9 +259,6 @@ // DRAM byte enable bits `define IDRAM_BYTEEN_WIDTH `ICACHE_LINE_SIZE -// Core request size -`define INUM_REQUESTS 1 - ////////////////////////// Dcache Configurable Knobs ////////////////////////// // Cache ID diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index f5be2d57..f560ef08 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -13,8 +13,8 @@ module VX_execute #( VX_csr_io_rsp_if csr_io_rsp_if, // Dcache interface - VX_cache_core_req_if dcache_req_if, - VX_cache_core_rsp_if dcache_rsp_if, + VX_dcache_core_req_if dcache_req_if, + VX_dcache_core_rsp_if dcache_rsp_if, // commit status VX_cmt_to_csr_if cmt_to_csr_if, diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index fd3b1fdc..34741637 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -9,8 +9,8 @@ module VX_fetch #( input wire reset, // Icache interface - VX_cache_core_req_if icache_req_if, - VX_cache_core_rsp_if icache_rsp_if, + VX_icache_core_req_if icache_req_if, + VX_icache_core_rsp_if icache_rsp_if, // inputs VX_wstall_if wstall_if, diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index d0b4ac09..f30e930a 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -9,8 +9,8 @@ module VX_icache_stage #( input wire reset, // Icache interface - VX_cache_core_req_if icache_req_if, - VX_cache_core_rsp_if icache_rsp_if, + VX_icache_core_req_if icache_req_if, + VX_icache_core_rsp_if icache_rsp_if, // request VX_ifetch_req_if ifetch_req_if, @@ -23,7 +23,10 @@ module VX_icache_stage #( wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; wire [`NW_BITS-1:0] req_tag = ifetch_req_if.wid; - wire [`NW_BITS-1:0] rsp_tag = icache_rsp_if.tag[0][`NW_BITS-1:0]; + wire [`NW_BITS-1:0] rsp_tag = icache_rsp_if.tag[`NW_BITS-1:0]; + + wire [31:0] rsp_PC; + wire [`NUM_THREADS-1:0] rsp_tmask; VX_dp_ram #( .DATAW(32 + `NUM_THREADS), @@ -37,15 +40,12 @@ module VX_icache_stage #( .byteen(1'b1), .rden(ifetch_rsp_if.valid), .din({ifetch_req_if.PC, ifetch_req_if.tmask}), - .dout({ifetch_rsp_if.PC, ifetch_rsp_if.tmask}) + .dout({rsp_PC, rsp_tmask}) ); // Icache Request - assign icache_req_if.valid = ifetch_req_if.valid; - assign icache_req_if.rw = 0; - assign icache_req_if.byteen = 4'b1111; - assign icache_req_if.addr = ifetch_req_if.PC[31:2]; - assign icache_req_if.data = 0; + assign icache_req_if.valid = ifetch_req_if.valid; + assign icache_req_if.addr = ifetch_req_if.PC[31:2]; // Can accept new request? assign ifetch_req_if.ready = icache_req_if.ready; @@ -57,8 +57,10 @@ module VX_icache_stage #( `endif assign ifetch_rsp_if.valid = icache_rsp_if.valid; + assign ifetch_rsp_if.tmask = rsp_tmask; assign ifetch_rsp_if.wid = rsp_tag; - assign ifetch_rsp_if.instr = icache_rsp_if.data[0]; + assign ifetch_rsp_if.PC = rsp_PC; + assign ifetch_rsp_if.instr = icache_rsp_if.data; // Can accept new response? assign icache_rsp_if.ready = ifetch_rsp_if.ready; @@ -68,7 +70,7 @@ module VX_icache_stage #( `SCOPE_ASSIGN (icache_req_addr, {icache_req_if.addr, 2'b0}); `SCOPE_ASSIGN (icache_req_tag, req_tag); `SCOPE_ASSIGN (icache_rsp_fire, icache_rsp_if.valid && icache_rsp_if.ready); - `SCOPE_ASSIGN (icache_rsp_data, icache_rsp_if.data[0]); + `SCOPE_ASSIGN (icache_rsp_data, icache_rsp_if.data); `SCOPE_ASSIGN (icache_rsp_tag, rsp_tag); `ifdef DBG_PRINT_CORE_ICACHE diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 253707d3..d33e74e5 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -9,8 +9,8 @@ module VX_lsu_unit #( input wire reset, // Dcache interface - VX_cache_core_req_if dcache_req_if, - VX_cache_core_rsp_if dcache_rsp_if, + VX_dcache_core_req_if dcache_req_if, + VX_dcache_core_rsp_if dcache_rsp_if, // inputs VX_lsu_req_if lsu_req_if, @@ -36,14 +36,14 @@ module VX_lsu_unit #( assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; end - wire [`NUM_THREADS-2:0] addr_matches; - for (genvar i = 1; i < `NUM_THREADS; i++) begin - assign addr_matches[i-1] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i]; + wire [`NUM_THREADS-1:0] addr_matches; + for (genvar i = 0; i < `NUM_THREADS; i++) begin + assign addr_matches[i] = (full_address[0][31:2] == full_address[i][31:2]) || ~lsu_req_if.tmask[i]; end - wire is_dup_load = lsu_req_if.wb && (& addr_matches); + wire is_dup_load = lsu_req_if.wb && lsu_req_if.tmask[0] && (& addr_matches); `IGNORE_WARNINGS_BEGIN - reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH-1:0] pending_tags; + reg [`LSUQ_SIZE-1:0][`DCORE_TAG_ID_BITS-1:0] pending_tags; `IGNORE_WARNINGS_END wire ready_in; @@ -92,7 +92,7 @@ module VX_lsu_unit #( wire mbuf_pop = mbuf_pop_part && (rsp_rem_mask_n == 0 || rsp_is_dup); - assign mbuf_raddr = dcache_rsp_if.tag[0][`DCORE_TAG_ID_BITS-1:0]; + assign mbuf_raddr = dcache_rsp_if.tag[`DCORE_TAG_ID_BITS-1:0]; VX_index_buffer #( .DATAW (`NW_BITS + 32 + `NR_BITS + 1 + `LSU_BITS + (`NUM_THREADS * 2) + 1), @@ -136,7 +136,7 @@ module VX_lsu_unit #( always @(posedge clk) begin if (mbuf_push) begin rsp_rem_mask[mbuf_waddr] <= req_tmask; - pending_tags[mbuf_waddr] <= dcache_req_if.tag[0]; + pending_tags[mbuf_waddr] <= req_tag; end if (mbuf_pop_part) begin rsp_rem_mask[mbuf_raddr] <= rsp_rem_mask_n; @@ -266,16 +266,16 @@ module VX_lsu_unit #( `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin if ((| (dcache_req_if.valid & dcache_req_if.ready))) begin - if (dcache_req_if.rw[0]) + if ((| dcache_req_if.rw)) $display("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h", - $time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data); + $time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data); else $display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d, is_dup=%b", - $time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup); + $time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_addr, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup); end if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h, is_dup=%b", - $time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data, rsp_is_dup); + $time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data, rsp_is_dup); end if (mbuf_full) begin $write("%t: D$%0d queue-full:", $time, CORE_ID); diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 8e4d55cb..5f499b3f 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -13,12 +13,12 @@ module VX_mem_unit # ( `endif // Core <-> Dcache - VX_cache_core_req_if core_dcache_req_if, - VX_cache_core_rsp_if core_dcache_rsp_if, + VX_dcache_core_req_if dcache_core_req_if, + VX_dcache_core_rsp_if dcache_core_rsp_if, // Core <-> Icache - VX_cache_core_req_if core_icache_req_if, - VX_cache_core_rsp_if core_icache_rsp_if, + VX_icache_core_req_if icache_core_req_if, + VX_icache_core_rsp_if icache_core_rsp_if, // DRAM VX_cache_dram_req_if dram_req_if, @@ -40,28 +40,28 @@ module VX_mem_unit # ( .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH) ) dcache_dram_rsp_if(), icache_dram_rsp_if(); - VX_cache_core_req_if #( + VX_dcache_core_req_if #( .NUM_REQS (`DNUM_REQUESTS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) ) dcache_req_if(); - VX_cache_core_rsp_if #( + VX_dcache_core_rsp_if #( .NUM_REQS (`DNUM_REQUESTS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) ) dcache_rsp_if(); - VX_cache_core_req_if #( + VX_dcache_core_req_if #( .NUM_REQS (`DNUM_REQUESTS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) ) smem_req_if(); - VX_cache_core_rsp_if #( + VX_dcache_core_rsp_if #( .NUM_REQS (`DNUM_REQUESTS), .WORD_SIZE (`DWORD_SIZE), .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), @@ -72,13 +72,13 @@ module VX_mem_unit # ( .clk (clk), .reset (reset), - .core_req_if (core_dcache_req_if), + .core_req_if (dcache_core_req_if), .cache_req_if (dcache_req_if), .smem_req_if (smem_req_if), .cache_rsp_if (dcache_rsp_if), .smem_rsp_if (smem_rsp_if), - .core_rsp_if (core_dcache_rsp_if) + .core_rsp_if (dcache_core_rsp_if) ); wire icache_reset, dcache_reset; @@ -97,7 +97,7 @@ module VX_mem_unit # ( .CACHE_LINE_SIZE (`ICACHE_LINE_SIZE), .NUM_BANKS (`INUM_BANKS), .WORD_SIZE (`IWORD_SIZE), - .NUM_REQS (`INUM_REQUESTS), + .NUM_REQS (1), .CREQ_SIZE (`ICREQ_SIZE), .MSHR_SIZE (`IMSHR_SIZE), .DRSQ_SIZE (`IDRSQ_SIZE), @@ -116,19 +116,19 @@ module VX_mem_unit # ( .flush (1'b0), // Core request - .core_req_valid (core_icache_req_if.valid), - .core_req_rw (core_icache_req_if.rw), - .core_req_byteen (core_icache_req_if.byteen), - .core_req_addr (core_icache_req_if.addr), - .core_req_data (core_icache_req_if.data), - .core_req_tag (core_icache_req_if.tag), - .core_req_ready (core_icache_req_if.ready), + .core_req_valid (icache_core_req_if.valid), + .core_req_rw (1'b0), + .core_req_byteen ({`IWORD_SIZE{1'b1}}), + .core_req_addr (icache_core_req_if.addr), + .core_req_data ('x), + .core_req_tag (icache_core_req_if.tag), + .core_req_ready (icache_core_req_if.ready), // Core response - .core_rsp_valid (core_icache_rsp_if.valid), - .core_rsp_data (core_icache_rsp_if.data), - .core_rsp_tag (core_icache_rsp_if.tag), - .core_rsp_ready (core_icache_rsp_if.ready), + .core_rsp_valid (icache_core_rsp_if.valid), + .core_rsp_data (icache_core_rsp_if.data), + .core_rsp_tag (icache_core_rsp_if.tag), + .core_rsp_ready (icache_core_rsp_if.ready), `ifdef PERF_ENABLE .perf_cache_if (perf_icache_if), diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 777e5bbe..90872fc8 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -26,11 +26,8 @@ module VX_pipeline #( // Icache core request output wire icache_req_valid, - output wire icache_req_rw, - output wire [3:0] icache_req_byteen, output wire [29:0] icache_req_addr, - output wire [31:0] icache_req_data, - output wire [`ICORE_TAG_WIDTH-1:0] icache_req_tag, + output wire [`ICORE_TAG_WIDTH-1:0] icache_req_tag, input wire icache_req_ready, // Icache core response @@ -63,71 +60,66 @@ module VX_pipeline #( // Dcache request // - VX_cache_core_req_if #( + VX_dcache_core_req_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_req_if(); + ) dcache_core_req_if(); - assign dcache_req_valid = core_dcache_req_if.valid; - assign dcache_req_rw = core_dcache_req_if.rw; - assign dcache_req_byteen = core_dcache_req_if.byteen; - assign dcache_req_addr = core_dcache_req_if.addr; - assign dcache_req_data = core_dcache_req_if.data; - assign dcache_req_tag = core_dcache_req_if.tag; - assign core_dcache_req_if.ready = dcache_req_ready; + assign dcache_req_valid = dcache_core_req_if.valid; + assign dcache_req_rw = dcache_core_req_if.rw; + assign dcache_req_byteen = dcache_core_req_if.byteen; + assign dcache_req_addr = dcache_core_req_if.addr; + assign dcache_req_data = dcache_core_req_if.data; + assign dcache_req_tag = dcache_core_req_if.tag; + assign dcache_core_req_if.ready = dcache_req_ready; // // Dcache response // - VX_cache_core_rsp_if #( + VX_dcache_core_rsp_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) - ) core_dcache_rsp_if(); + ) dcache_core_rsp_if(); - assign core_dcache_rsp_if.valid = dcache_rsp_valid; - assign core_dcache_rsp_if.data = dcache_rsp_data; - assign core_dcache_rsp_if.tag = dcache_rsp_tag; - assign dcache_rsp_ready = core_dcache_rsp_if.ready; + assign dcache_core_rsp_if.valid = dcache_rsp_valid; + assign dcache_core_rsp_if.data = dcache_rsp_data; + assign dcache_core_rsp_if.tag = dcache_rsp_tag; + assign dcache_rsp_ready = dcache_core_rsp_if.ready; // // Icache request // - VX_cache_core_req_if #( - .NUM_REQS(1), + VX_icache_core_req_if #( .WORD_SIZE(4), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) - ) core_icache_req_if(); + ) icache_core_req_if(); - assign icache_req_valid = core_icache_req_if.valid; - assign icache_req_rw = core_icache_req_if.rw; - assign icache_req_byteen = core_icache_req_if.byteen; - assign icache_req_addr = core_icache_req_if.addr; - assign icache_req_data = core_icache_req_if.data; - assign icache_req_tag = core_icache_req_if.tag; - assign core_icache_req_if.ready = icache_req_ready; + assign icache_req_valid = icache_core_req_if.valid; + assign icache_req_addr = icache_core_req_if.addr; + assign icache_req_tag = icache_core_req_if.tag; + assign icache_core_req_if.ready = icache_req_ready; // // Icache response // - VX_cache_core_rsp_if #( - .NUM_REQS(1), + VX_icache_core_rsp_if #( .WORD_SIZE(4), .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) - ) core_icache_rsp_if(); + ) icache_core_rsp_if(); - assign core_icache_rsp_if.valid = icache_rsp_valid; - assign core_icache_rsp_if.data = icache_rsp_data; - assign core_icache_rsp_if.tag = icache_rsp_tag; - assign icache_rsp_ready = core_icache_rsp_if.ready; + assign icache_core_rsp_if.valid = icache_rsp_valid; + assign icache_core_rsp_if.data = icache_rsp_data; + assign icache_core_rsp_if.tag = icache_rsp_tag; + assign icache_rsp_ready = icache_core_rsp_if.ready; // // CSR IO request @@ -183,8 +175,8 @@ module VX_pipeline #( `SCOPE_BIND_VX_pipeline_fetch .clk (clk), .reset (reset), - .icache_req_if (core_icache_req_if), - .icache_rsp_if (core_icache_rsp_if), + .icache_req_if (icache_core_req_if), + .icache_rsp_if (icache_core_rsp_if), .wstall_if (wstall_if), .join_if (join_if), .warp_ctl_if (warp_ctl_if), @@ -240,8 +232,8 @@ module VX_pipeline #( .perf_pipeline_if (perf_pipeline_if), `endif - .dcache_req_if (core_dcache_req_if), - .dcache_rsp_if (core_dcache_rsp_if), + .dcache_req_if (dcache_core_req_if), + .dcache_rsp_if (dcache_core_rsp_if), .csr_io_req_if (csr_io_req_if), .csr_io_rsp_if (csr_io_rsp_if), diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index a29f2dd3..bfe8b96c 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -55,6 +55,8 @@ `define CORE_REQ_TAG_COUNT ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS) +`define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS) + `define DRAM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET] `define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1 : `BANK_SELECT_BITS] diff --git a/hw/rtl/cache/VX_cache_core_req_bank_sel.v b/hw/rtl/cache/VX_cache_core_req_bank_sel.v index d71bd0e4..665c1cbf 100644 --- a/hw/rtl/cache/VX_cache_core_req_bank_sel.v +++ b/hw/rtl/cache/VX_cache_core_req_bank_sel.v @@ -14,7 +14,9 @@ module VX_cache_core_req_bank_sel #( // core request tag size parameter CORE_TAG_WIDTH = 3, // bank offset from beginning of index range - parameter BANK_ADDR_OFFSET = 0 + parameter BANK_ADDR_OFFSET = 0, + // shared bank ready signal + parameter SHARED_BANK_READY = 0 ) ( input wire clk, input wire reset, @@ -39,7 +41,7 @@ module VX_cache_core_req_bank_sel #( output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data, output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid, output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag, - input wire [NUM_BANKS-1:0] per_bank_core_req_ready + input wire [`BANK_READY_COUNT-1:0] per_bank_core_req_ready ); `STATIC_ASSERT (NUM_REQS >= NUM_BANKS, ("invalid number of banks")); @@ -129,11 +131,21 @@ module VX_cache_core_req_bank_sel #( end end - always @(*) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i] - && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; + if (SHARED_BANK_READY == 0) begin + always @(*) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] + && core_req_line_match[i] + && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; + end + end + end else begin + always @(*) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + core_req_ready_r[i] = per_bank_core_req_ready + && core_req_line_match[i] + && req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]; + end end end @@ -148,7 +160,6 @@ module VX_cache_core_req_bank_sel #( per_bank_core_req_data_r = 'x; per_bank_core_req_tag_r = 'x; per_bank_core_req_tid_r = 'x; - core_req_ready_r = 'x; for (integer i = NUM_REQS-1; i >= 0; --i) begin if (core_req_valid[i]) begin @@ -159,9 +170,29 @@ module VX_cache_core_req_bank_sel #( per_bank_core_req_tid_r[core_req_bid[i]][i % NUM_PORTS] = `REQS_BITS'(i); per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i]; per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i]; - per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i]; - core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] - && core_req_line_match[i]; + per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i]; + end + end + end + + if (SHARED_BANK_READY == 0) begin + always @(*) begin + core_req_ready_r = 'x; + for (integer i = NUM_REQS-1; i >= 0; --i) begin + if (core_req_valid[i]) begin + core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]] + && core_req_line_match[i]; + end + end + end + end else begin + always @(*) begin + core_req_ready_r = 'x; + for (integer i = NUM_REQS-1; i >= 0; --i) begin + if (core_req_valid[i]) begin + core_req_ready_r[i] = per_bank_core_req_ready + && core_req_line_match[i]; + end end end end @@ -193,13 +224,27 @@ module VX_cache_core_req_bank_sel #( end end - always @(*) begin - core_req_ready_r = 0; - for (integer j = 0; j < NUM_BANKS; ++j) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin - core_req_ready_r[i] = per_bank_core_req_ready[j]; - break; + if (SHARED_BANK_READY == 0) begin + always @(*) begin + core_req_ready_r = 0; + for (integer j = 0; j < NUM_BANKS; ++j) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin + core_req_ready_r[i] = per_bank_core_req_ready[j]; + break; + end + end + end + end + end else begin + always @(*) begin + core_req_ready_r = 0; + for (integer j = 0; j < NUM_BANKS; ++j) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin + core_req_ready_r[i] = per_bank_core_req_ready; + break; + end end end end @@ -234,12 +279,25 @@ module VX_cache_core_req_bank_sel #( `ifdef PERF_ENABLE reg [NUM_REQS-1:0] core_req_sel_r; - always @(*) begin - core_req_sel_r = 0; - for (integer j = 0; j < NUM_BANKS; ++j) begin - for (integer i = 0; i < NUM_REQS; ++i) begin - if (core_req_valid[i] && (core_req_bid[i] == `UP(`BANK_SELECT_BITS)'(j))) begin - core_req_sel_r[i] = per_bank_core_req_ready[j]; + if (SHARED_BANK_READY == 0) begin + always @(*) begin + core_req_sel_r = 0; + for (integer j = 0; j < NUM_BANKS; ++j) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + if (core_req_valid[i] && (core_req_bid[i] == `UP(`BANK_SELECT_BITS)'(j))) begin + core_req_sel_r[i] = per_bank_core_req_ready[j]; + end + end + end + end + end else begin + always @(*) begin + core_req_sel_r = 0; + for (integer j = 0; j < NUM_BANKS; ++j) begin + for (integer i = 0; i < NUM_REQS; ++i) begin + if (core_req_valid[i] && (core_req_bid[i] == `UP(`BANK_SELECT_BITS)'(j))) begin + core_req_sel_r[i] = per_bank_core_req_ready; + end end end end diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 5b0871a6..544de776 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -69,7 +69,7 @@ module VX_shared_mem #( wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual; wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual; wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual; - wire [NUM_BANKS-1:0] per_bank_core_req_ready_unqual; + wire per_bank_core_req_ready_unqual; VX_cache_core_req_bank_sel #( .CACHE_LINE_SIZE (WORD_SIZE), @@ -78,7 +78,8 @@ module VX_shared_mem #( .WORD_SIZE (WORD_SIZE), .NUM_REQS (NUM_REQS), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), - .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET) + .BANK_ADDR_OFFSET(BANK_ADDR_OFFSET), + .SHARED_BANK_READY(1) ) core_req_bank_sel ( .clk (clk), .reset (reset), @@ -103,9 +104,6 @@ module VX_shared_mem #( .per_bank_core_req_ready (per_bank_core_req_ready_unqual) ); - `UNUSED_VAR (per_bank_core_req_tag_unqual) - `UNUSED_VAR (per_bank_core_req_rw_unqual) - wire [NUM_BANKS-1:0] per_bank_core_req_valid; wire [NUM_BANKS-1:0] per_bank_core_req_rw; wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr; @@ -120,7 +118,7 @@ module VX_shared_mem #( assign creq_push = (| core_req_valid) && !creq_full; assign creq_pop = ~creq_empty && ~crsq_full; - assign per_bank_core_req_ready_unqual = {NUM_BANKS{~creq_full}}; + assign per_bank_core_req_ready_unqual = ~creq_full; wire [NUM_REQS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr_qual; `UNUSED_VAR (per_bank_core_req_addr_unqual) diff --git a/hw/rtl/interfaces/VX_cache_core_rsp_if.v b/hw/rtl/interfaces/VX_cache_core_rsp_if.v deleted file mode 100644 index 265d19cd..00000000 --- a/hw/rtl/interfaces/VX_cache_core_rsp_if.v +++ /dev/null @@ -1,20 +0,0 @@ -`ifndef VX_CACHE_CORE_RSP_IF -`define VX_CACHE_CORE_RSP_IF - -`include "../cache/VX_cache_config.vh" - -interface VX_cache_core_rsp_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 -) (); - - wire [NUM_REQS-1:0] valid; - wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; - wire ready; - -endinterface - -`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_cache_core_req_if.v b/hw/rtl/interfaces/VX_dcache_core_req_if.v similarity index 86% rename from hw/rtl/interfaces/VX_cache_core_req_if.v rename to hw/rtl/interfaces/VX_dcache_core_req_if.v index 8b01eef3..35a5836e 100644 --- a/hw/rtl/interfaces/VX_cache_core_req_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_req_if.v @@ -1,9 +1,9 @@ -`ifndef VX_CACHE_CORE_REQ_IF -`define VX_CACHE_CORE_REQ_IF +`ifndef VX_DCACHE_CORE_REQ_IF +`define VX_DCACHE_CORE_REQ_IF `include "../cache/VX_cache_config.vh" -interface VX_cache_core_req_if #( +interface VX_dcache_core_req_if #( parameter NUM_REQS = 1, parameter WORD_SIZE = 1, parameter CORE_TAG_WIDTH = 1, diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v new file mode 100644 index 00000000..7f4c5203 --- /dev/null +++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v @@ -0,0 +1,20 @@ +`ifndef VX_DCACHE_CORE_RSP_IF +`define VX_DCACHE_CORE_RSP_IF + +`include "../cache/VX_cache_config.vh" + +interface VX_dcache_core_rsp_if #( + parameter NUM_REQS = 1, + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1, + parameter CORE_TAG_ID_BITS = 0 +) (); + + wire [NUM_REQS-1:0] valid; + wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] data; + wire [CORE_TAG_WIDTH-1:0] tag; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_icache_core_req_if.v b/hw/rtl/interfaces/VX_icache_core_req_if.v new file mode 100644 index 00000000..a683226a --- /dev/null +++ b/hw/rtl/interfaces/VX_icache_core_req_if.v @@ -0,0 +1,19 @@ +`ifndef VX_ICACHE_CORE_REQ_IF +`define VX_ICACHE_CORE_REQ_IF + +`include "../cache/VX_cache_config.vh" + +interface VX_icache_core_req_if #( + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1, + parameter CORE_TAG_ID_BITS = 0 +) (); + + wire valid; + wire [`WORD_ADDR_WIDTH-1:0] addr; + wire [CORE_TAG_WIDTH-1:0] tag; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_icache_core_rsp_if.v b/hw/rtl/interfaces/VX_icache_core_rsp_if.v new file mode 100644 index 00000000..e78e1e0b --- /dev/null +++ b/hw/rtl/interfaces/VX_icache_core_rsp_if.v @@ -0,0 +1,19 @@ +`ifndef VX_ICACHE_CORE_RSP_IF +`define VX_ICACHE_CORE_RSP_IF + +`include "../cache/VX_cache_config.vh" + +interface VX_icache_core_rsp_if #( + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1, + parameter CORE_TAG_ID_BITS = 0 +) (); + + wire valid; + wire [`WORD_WIDTH-1:0] data; + wire [CORE_TAG_WIDTH-1:0] tag; + wire ready; + +endinterface + +`endif \ No newline at end of file diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 87b9a72b..ad84c277 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -14,7 +14,7 @@ interface VX_lsu_req_if (); wire [`NUM_THREADS-1:0][31:0] base_addr; wire [31:0] offset; wire [`NR_BITS-1:0] rd; - wire wb; + wire wb; wire ready; endinterface diff --git a/hw/syn/quartus/project.tcl b/hw/syn/quartus/project.tcl index aeb6c7e8..a1573cf4 100644 --- a/hw/syn/quartus/project.tcl +++ b/hw/syn/quartus/project.tcl @@ -41,10 +41,11 @@ set_global_assignment -name VERILOG_MACRO NDEBUG set_global_assignment -name MESSAGE_DISABLE 16818 set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON set_global_assignment -name USE_HIGH_SPEED_ADDER ON set_global_assignment -name MUX_RESTRUCTURE ON + +#set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED #set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" #set_global_assignment -name FITTER_EFFORT "STANDARD FIT" #set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"