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Memory access information in emulator for timing simulation.

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This commit is contained in:
cdkersey
2015-09-05 16:12:49 -06:00
parent 2bebcd8cc0
commit ae11d80d36
2 changed files with 11 additions and 0 deletions
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7
src/include/core.h
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@@ -105,6 +105,13 @@ namespace Harp {
void printStats() const; void printStats() const;
struct MemAccess {
MemAccess(bool w, Word a): wr(w), addr(a) {}
bool wr;
Word addr;
};
std::vector<MemAccess> memAccesses;
// private: // private:
Core *core; Core *core;

4
src/instruction.cpp
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@@ -138,6 +138,8 @@ void Instruction::executeOn(Warp &c) {
Size wordSz = c.core->a.getWordSize(); Size wordSz = c.core->a.getWordSize();
Word nextPc = c.pc; Word nextPc = c.pc;
c.memAccesses.clear();
// If we have a load, overwriting a register's contents, we have to make sure // If we have a load, overwriting a register's contents, we have to make sure
// ahead of time it will not fault. Otherwise we may perform an indirect load // ahead of time it will not fault. Otherwise we may perform an indirect load
// by mistake. // by mistake.
@@ -271,10 +273,12 @@ void Instruction::executeOn(Warp &c) {
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true); do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
#endif #endif
reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode); reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode);
c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
break; break;
case ST: ++c.stores; case ST: ++c.stores;
memAddr = reg[rsrc[1]] + immsrc; memAddr = reg[rsrc[1]] + immsrc;
c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode); c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
#ifdef EMU_INSTRUMENTATION #ifdef EMU_INSTRUMENTATION
Harp::OSDomain::osDomain-> Harp::OSDomain::osDomain->
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true); do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);