minor ibuffer critical path optimization.

hw/rtl/VX_ibuffer.v

@@ -7,7 +7,6 @@ module VX_ibuffer #(
     input wire reset,
 
     // inputs
-    input wire    freeze,       // keep current warp
     VX_decode_if  ibuf_enq_if,  
 
     // outputs
@@ -119,16 +118,7 @@ module VX_ibuffer #(
         deq_instr_n = 'x;
         schedule_table_n = 'x;  
 
-        if ((0 == num_warps) 
+        if (num_warps > 1) begin
-         || (1 == num_warps && deq_fire && q_alm_empty[deq_wid])) begin
-            deq_valid_n = enq_fire;
-            deq_wid_n   = ibuf_enq_if.wid;
-            deq_instr_n = q_data_in;  
-        end else if ((1 == num_warps) || freeze) begin   
-            deq_valid_n = 1;               
-            deq_wid_n   = deq_wid;
-            deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
-        end else begin
             deq_valid_n = (| schedule_table);
             schedule_table_n = schedule_table;
             for (integer i = 0; i < `NUM_WARPS; i++) begin
@@ -139,6 +129,14 @@ module VX_ibuffer #(
                     break;
                 end
             end
+        end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin
+            deq_valid_n = 1;               
+            deq_wid_n   = deq_wid;
+            deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
+        end else begin
+            deq_valid_n = enq_fire;
+            deq_wid_n   = ibuf_enq_if.wid;
+            deq_instr_n = q_data_in;  
         end   
     end
 

hw/rtl/VX_issue.v

@@ -33,7 +33,6 @@ module VX_issue #(
     ) ibuffer (
         .clk          (clk),
         .reset        (reset), 
-        .freeze       (1'b0),
         .ibuf_enq_if  (decode_if),
         .ibuf_deq_if  (ibuf_deq_if) 
     );

hw/rtl/VX_scoreboard.v

@@ -31,7 +31,7 @@ module VX_scoreboard  #(
             if (release_reg) begin
                 inuse_regs[writeback_if.wid][writeback_if.rd] <= 0;
                 assert(inuse_regs[writeback_if.wid][writeback_if.rd] != 0) 
-                    else $error("*** %t: core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
+                    else $error("%t: *** core%0d: invalid writeback register: wid=%0d, PC=%0h, rd=%0d",
                                 $time, CORE_ID, writeback_if.wid, writeback_if.PC, writeback_if.rd);
             end
         end    
@@ -40,7 +40,7 @@ module VX_scoreboard  #(
 `ifdef DBG_PRINT_PIPELINE
     always @(posedge clk) begin
         if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin            
-            $display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
+            $display("%t: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
                     $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, 
                     deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);            
         end
@@ -54,7 +54,7 @@ module VX_scoreboard  #(
             deadlock_ctr <= 0;
         end else if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin            
             deadlock_ctr <= deadlock_ctr + 1;
-            assert(deadlock_ctr < deadlock_timeout) else $error("*** %t: core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
+            assert(deadlock_ctr < deadlock_timeout) else $error("%t: *** core%0d-deadlock: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b",
                     $time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.PC, ibuf_deq_if.rd, ibuf_deq_if.wb, 
                     deq_inuse_regs[ibuf_deq_if.rd], deq_inuse_regs[ibuf_deq_if.rs1], deq_inuse_regs[ibuf_deq_if.rs2], deq_inuse_regs[ibuf_deq_if.rs3]);            
         end else if (ibuf_deq_if.valid && ibuf_deq_if.ready) begin

hw/rtl/cache/VX_bank.v

@@ -558,11 +558,11 @@ module VX_bank #(
 
 `ifdef DBG_PRINT_CACHE_BANK
     always @(posedge clk) begin  
-        /*if (valid_st1 && pmask_st1 == {NUM_PORTS{1'b1}}) begin
+        /*if (crsq_in_fire && (NUM_PORTS > 1) && $countones(crsq_pmask) > 1) begin
-            $display("%t: cache%0d:%0d full bank multi-porting - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
+            $display("%t: *** cache%0d:%0d multi-port-out: pmask=%b, addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, crsq_pmask, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag);
         end */     
         if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_qual_st1) begin
-            $display("%t: cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
+            $display("%t: *** cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
             assert(!is_mshr_st1);
         end
         if (crsq_in_stall || dreq_alm_full || mshr_alm_full) begin

hw/rtl/cache/VX_cache.v

@@ -176,6 +176,7 @@ module VX_cache #(
     ///////////////////////////////////////////////////////////////////////////
 
     VX_cache_core_req_bank_sel #(
+        .CACHE_ID        (CACHE_ID),
         .CACHE_LINE_SIZE (CACHE_LINE_SIZE),
         .NUM_BANKS       (NUM_BANKS),
         .NUM_PORTS       (NUM_PORTS),
@@ -351,6 +352,7 @@ module VX_cache #(
     end   
 
     VX_cache_core_rsp_merge #(
+        .CACHE_ID           (CACHE_ID),
         .NUM_BANKS          (NUM_BANKS),
         .NUM_PORTS          (NUM_PORTS),
         .WORD_SIZE          (WORD_SIZE),

hw/rtl/cache/VX_cache_core_req_bank_sel.v

@@ -1,6 +1,8 @@
 `include "VX_cache_config.vh"
 
 module VX_cache_core_req_bank_sel #(  
+    parameter CACHE_ID          = 0,
+
     // Size of line inside a bank in bytes
     parameter CACHE_LINE_SIZE   = 64, 
     // Size of a word in bytes

hw/rtl/cache/VX_cache_core_rsp_merge.v

@@ -1,6 +1,8 @@
 `include "VX_cache_config.vh"
 
 module VX_cache_core_rsp_merge #(
+    parameter CACHE_ID          = 0,
+
     // Number of Word requests per cycle
     parameter NUM_REQS          = 1, 
     // Number of banks

hw/rtl/cache/VX_shared_mem.v

@@ -71,6 +71,7 @@ module VX_shared_mem #(
     wire                                    per_bank_core_req_ready_unqual;
     
     VX_cache_core_req_bank_sel #(
+        .CACHE_ID        (CACHE_ID),
         .CACHE_LINE_SIZE (WORD_SIZE),
         .NUM_BANKS       (NUM_BANKS),
         .NUM_PORTS       (1),

hw/rtl/libs/VX_scope.v

@@ -94,13 +94,13 @@ module VX_scope #(
                         delay_val <= $bits(delay_val)'(cmd_data); 
                         cmd_start <= 1;
                     `ifdef DBG_PRINT_SCOPE
-                        $display("*** scope:CMD_SET_START: delay_val=%0d", $bits(delay_val)'(cmd_data));
+                        $display("%t: *** scope: CMD_SET_START: delay_val=%0d", $time, $bits(delay_val)'(cmd_data));
                     `endif
                     end
                     CMD_SET_STOP: begin
                         waddr_end <= $bits(waddr)'(cmd_data);
                     `ifdef DBG_PRINT_SCOPE
-                        $display("*** scope:CMD_SET_STOP: waddr_end=%0d", $bits(waddr)'(cmd_data));
+                        $display("%t: *** scope: CMD_SET_STOP: waddr_end=%0d", $time, $bits(waddr)'(cmd_data));
                     `endif
                     end
                     default:;
@@ -117,7 +117,7 @@ module VX_scope #(
                     delay_cntr  <= 0;
                     start_time  <= timestamp;
                 `ifdef DBG_PRINT_SCOPE
-                    $display("*** scope: recording start - start_time=%0d", timestamp);
+                    $display("%t: *** scope: recording start - start_time=%0d", $time, timestamp);
                 `endif
                 end else begin
                     start_wait <= 1;
@@ -133,7 +133,7 @@ module VX_scope #(
                     delta      <= 0;
                     start_time <= timestamp;
                 `ifdef DBG_PRINT_SCOPE
-                    $display("*** scope: recording start - start_time=%0d", timestamp);
+                    $display("%t: *** scope: recording start - start_time=%0d", $time, timestamp);
                 `endif
                 end 
             end
@@ -162,7 +162,7 @@ module VX_scope #(
                 if (stop
                  || (waddr >= waddr_end)) begin
                 `ifdef DBG_PRINT_SCOPE
-                    $display("*** scope: recording stop - waddr=(%0d, %0d)", waddr, waddr_end);
+                    $display("%t: *** scope: recording stop - waddr=(%0d, %0d)", $time, waddr, waddr_end);
                 `endif
                     waddr      <= waddr;  // keep last address
                     recording  <= 0;

hw/syn/opae/README

@@ -44,6 +44,9 @@ fpgaconf vortex_afu.gbs
 # If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
 fpgaconf --bus 0xaf vortex_afu.gbs
 
+# get portid
+fpgainfo port
+
 # Running the Test case 
 cd /driver/tests/basic
 make run-fpga