diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 83dbad0a..141da4d6 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -5,7 +5,7 @@ CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 DEBUG = 1 diff --git a/driver/tests/basic/common.h b/driver/tests/basic/common.h index dfb4b0a2..9e178034 100644 --- a/driver/tests/basic/common.h +++ b/driver/tests/basic/common.h @@ -3,6 +3,6 @@ #define DEV_MEM_SRC_ADDR 0x10000000 #define DEV_MEM_DST_ADDR 0x20000000 -#define NUM_BLOCKS 1 +#define NUM_BLOCKS 4 #endif \ No newline at end of file diff --git a/driver/tests/basic/kernel.bin b/driver/tests/basic/kernel.bin index 824960c1..7dd503d3 100755 Binary files a/driver/tests/basic/kernel.bin and b/driver/tests/basic/kernel.bin differ diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index ba9c5492..83428229 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -127,9 +127,9 @@ module VX_bank #( assign snp_req_ready = ~snrq_full; - wire dfpq_pop; - wire dfpq_empty; - wire dfpq_full; + wire dfpq_pop; + wire dfpq_empty; + wire dfpq_full; wire [`LINE_ADDR_WIDTH-1:0] dfpq_addr_st0; wire [`BANK_LINE_WIDTH-1:0] dfpq_filldata_st0; @@ -164,11 +164,11 @@ module VX_bank #( wire [`BYTE_EN_BITS-1:0] reqq_req_mem_write_st0; VX_cache_req_queue #( - .WORD_SIZE (WORD_SIZE), - .NUM_REQUESTS (NUM_REQUESTS), - .REQQ_SIZE (REQQ_SIZE), - .CORE_TAG_WIDTH (CORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(CORE_TAG_ID_BITS) + .WORD_SIZE (WORD_SIZE), + .NUM_REQUESTS (NUM_REQUESTS), + .REQQ_SIZE (REQQ_SIZE), + .CORE_TAG_WIDTH (CORE_TAG_WIDTH), + .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS) ) req_queue ( .clk (clk), .reset (reset), @@ -343,21 +343,21 @@ module VX_bank #( assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; VX_tag_data_access #( - .CACHE_SIZE (CACHE_SIZE), - .BANK_LINE_SIZE (BANK_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE), - .STAGE_1_CYCLES (STAGE_1_CYCLES), - .DRAM_ENABLE (DRAM_ENABLE), - .WRITE_ENABLE (WRITE_ENABLE) + .CACHE_SIZE (CACHE_SIZE), + .BANK_LINE_SIZE (BANK_LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .STAGE_1_CYCLES (STAGE_1_CYCLES), + .DRAM_ENABLE (DRAM_ENABLE), + .WRITE_ENABLE (WRITE_ENABLE) ) tag_data_access ( - .clk (clk), - .reset (reset), - .stall (stall_bank_pipe), - .stall_bank_pipe (stall_bank_pipe), + .clk (clk), + .reset (reset), + .stall (stall_bank_pipe), + .stall_bank_pipe(stall_bank_pipe), // Initial Read - .readaddr_st10 (addr_st1[0][`LINE_SELECT_BITS-1:0]), + .readaddr_st10(addr_st1[0][`LINE_SELECT_BITS-1:0]), // Actual Read/Write .valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]), diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index 2e31e8b7..6065fe67 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -18,42 +18,38 @@ module VX_cache_miss_resrv #( input wire reset, // Miss enqueue - input wire miss_add, - input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr, - input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel, - input wire[`WORD_WIDTH-1:0] miss_add_data, - input wire[`REQS_BITS-1:0] miss_add_tid, - input wire[CORE_TAG_WIDTH-1:0] miss_add_tag, - input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read, - input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write, - output wire miss_resrv_full, - output wire miss_resrv_stop, + input wire miss_add, + input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr, + input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel, + input wire[`WORD_WIDTH-1:0] miss_add_data, + input wire[`REQS_BITS-1:0] miss_add_tid, + input wire[CORE_TAG_WIDTH-1:0] miss_add_tag, + input wire[`BYTE_EN_BITS-1:0] miss_add_mem_read, + input wire[`BYTE_EN_BITS-1:0] miss_add_mem_write, + output wire miss_resrv_full, + output wire miss_resrv_stop, // Broadcast Fill - input wire is_fill_st1, - -`IGNORE_WARNINGS_BEGIN - // TODO: should fix this - input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1, -`IGNORE_WARNINGS_END + input wire is_fill_st1, + input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1, // Miss dequeue - input wire miss_resrv_pop, - output wire miss_resrv_valid_st0, - output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0, - output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0, - output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0, - output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, - output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0, - output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0, - output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0 + input wire miss_resrv_pop, + output wire miss_resrv_valid_st0, + output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0, + output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0, + output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0, + output wire[`REQS_BITS-1:0] miss_resrv_tid_st0, + output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0, + output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_read_st0, + output wire[`BYTE_EN_BITS-1:0] miss_resrv_mem_write_st0 ); - reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0]; + reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0]; reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table; - reg [MRVQ_SIZE-1:0] valid_table; - reg [MRVQ_SIZE-1:0] ready_table; - reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr; - reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr; + reg [MRVQ_SIZE-1:0] valid_table; + reg [MRVQ_SIZE-1:0] ready_table; + reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr; + reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr; reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; @@ -99,7 +95,8 @@ module VX_cache_miss_resrv #( tail_ptr <= tail_ptr + 1; end - if (update_ready) begin + // update entry as 'ready' during DRAM fill response + if (update_ready) begin ready_table <= ready_table | make_ready; end diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 0ee2a953..442e5008 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -46,7 +46,6 @@ module VX_snp_forwarder #( wire [SNP_FWD_TAG_WIDTH-1:0] fwdin_tag; wire fwdin_ready; wire fwdin_taken; - assign fwdout_ready = (& snp_fwdout_ready); @@ -113,4 +112,19 @@ module VX_snp_forwarder #( assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i)); end + /*always_comb begin + if (1'($time & 1) && snp_req_valid && snp_req_ready) begin + $display("*** %t: ", $time); + end + if (1'($time & 1) && snp_fwdout_valid && snp_fwdout_ready) begin + $display("*** %t: ", $time); + end + if (1'($time & 1) && fwdin_valid && fwdin_ready) begin + $display("*** %t: ", $time); + end + if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin + $display("*** %t: ", $time); + end + end*/ + endmodule \ No newline at end of file diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index 5683bdc4..82c92e14 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -177,6 +177,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { for (;;) { this->step(); if (vortex_->snp_rsp_valid) { + assert(outstanding_snp_reqs > 0); --outstanding_snp_reqs; } if (vortex_->snp_req_valid && vortex_->snp_req_ready) {