From b0b7cd2b1e311858f8b7d8d5228efb35e5eeb5a4 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 3 Feb 2024 19:09:53 -0800 Subject: [PATCH] minor updates --- README.md | 6 +++--- hw/rtl/VX_config.vh | 12 ++++++++++++ hw/rtl/VX_define.vh | 12 ------------ sim/simx/cluster.cpp | 8 ++++---- sim/simx/core.cpp | 2 +- sim/simx/execute.cpp | 6 +++--- sim/simx/main.cpp | 2 +- sim/simx/processor.cpp | 6 +++--- sim/simx/socket.cpp | 2 +- 9 files changed, 28 insertions(+), 28 deletions(-) diff --git a/README.md b/README.md index 0db8e2ea..bca70da0 100644 --- a/README.md +++ b/README.md @@ -54,9 +54,9 @@ More detailed build instructions can be found [here](docs/install_vortex.md). $ git clone --recursive https://github.com/vortexgpgpu/vortex.git $ cd Vortex ### Install prebuilt toolchain - By default, the toolchain will install to /opt folder. - You can install the toolchain to a different directory by overriding TOOLDIR (e.g. export TOOLDIR=$HOME/tools). - + By default, the toolchain will install to /opt folder which requires sudo access. + You can install the toolchain to a different location of your choice by setting TOOLDIR (e.g. export TOOLDIR=$HOME/tools). + $ export TOOLDIR=/opt $ ./ci/toolchain_install.sh --all $ source ./ci/toolchain_env.sh ### Build Vortex sources diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 23805dcf..eed3cf54 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -136,6 +136,18 @@ `endif `endif +`ifdef L2_ENABLE +`define L2_LINE_SIZE `MEM_BLOCK_SIZE +`else +`define L2_LINE_SIZE `L1_LINE_SIZE +`endif + +`ifdef L3_ENABLE +`define L3_LINE_SIZE `MEM_BLOCK_SIZE +`else +`define L3_LINE_SIZE `L2_LINE_SIZE +`endif + `ifdef XLEN_64 `ifndef STARTUP_ADDR diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 093a5fd2..996c769d 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -298,18 +298,6 @@ `define L1_ENABLE `endif -`ifdef L2_ENABLE -`define L2_LINE_SIZE `MEM_BLOCK_SIZE -`else -`define L2_LINE_SIZE `L1_LINE_SIZE -`endif - -`ifdef L3_ENABLE -`define L3_LINE_SIZE `MEM_BLOCK_SIZE -`else -`define L3_LINE_SIZE `L2_LINE_SIZE -`endif - `define VX_MEM_BYTEEN_WIDTH `L3_LINE_SIZE `define VX_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE)) `define VX_MEM_DATA_WIDTH (`L3_LINE_SIZE * 8) diff --git a/sim/simx/cluster.cpp b/sim/simx/cluster.cpp index 3ac80cb6..c632165a 100644 --- a/sim/simx/cluster.cpp +++ b/sim/simx/cluster.cpp @@ -62,10 +62,10 @@ Cluster::Cluster(const SimContext& ctx, snprintf(sname, 100, "cluster%d-l2cache", cluster_id); l2cache_ = CacheSim::Create(sname, CacheSim::Config{ !L2_ENABLED, - log2ceil(L2_CACHE_SIZE), // C - log2ceil(MEM_BLOCK_SIZE), // L - log2ceil(L2_NUM_WAYS), // W - 0, // A + log2ceil(L2_CACHE_SIZE),// C + log2ceil(MEM_BLOCK_SIZE),// L + log2ceil(L1_LINE_SIZE), // W + log2ceil(L2_NUM_WAYS), // A log2ceil(L2_NUM_BANKS), // B XLEN, // address bits 1, // number of ports diff --git a/sim/simx/core.cpp b/sim/simx/core.cpp index 1c155011..50137a9c 100644 --- a/sim/simx/core.cpp +++ b/sim/simx/core.cpp @@ -210,7 +210,7 @@ void Core::schedule() { void Core::fetch() { perf_stats_.ifetch_latency += pending_ifetches_; - // handle icache reponse + // handle icache response auto& icache_rsp_port = icache_rsp_ports.at(0); if (!icache_rsp_port.empty()){ auto& mem_rsp = icache_rsp_port.front(); diff --git a/sim/simx/execute.cpp b/sim/simx/execute.cpp index 52a95de1..4a8033d0 100644 --- a/sim/simx/execute.cpp +++ b/sim/simx/execute.cpp @@ -339,7 +339,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { break; } case 1: { - // RV64I: SLLI + // RV32I: SLLI rddata[t].i = rsdata[t][0].i << immsrc; break; } @@ -360,11 +360,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) { } case 5: { if (func7) { - // RV64I: SRAI + // RV32I: SRAI Word result = rsdata[t][0].i >> immsrc; rddata[t].i = result; } else { - // RV64I: SRLI + // RV32I: SRLI Word result = rsdata[t][0].u >> immsrc; rddata[t].i = result; } diff --git a/sim/simx/main.cpp b/sim/simx/main.cpp index 64031bb8..b4dcf4ed 100644 --- a/sim/simx/main.cpp +++ b/sim/simx/main.cpp @@ -34,7 +34,7 @@ static void show_usage() { uint32_t num_threads = NUM_THREADS; uint32_t num_warps = NUM_WARPS; uint32_t num_cores = NUM_CORES; -bool showStats = false;; +bool showStats = false; bool riscv_test = false; const char* program = nullptr; diff --git a/sim/simx/processor.cpp b/sim/simx/processor.cpp index 8e8c1062..5382263e 100644 --- a/sim/simx/processor.cpp +++ b/sim/simx/processor.cpp @@ -33,8 +33,8 @@ ProcessorImpl::ProcessorImpl(const Arch& arch) !L3_ENABLED, log2ceil(L3_CACHE_SIZE), // C log2ceil(MEM_BLOCK_SIZE), // L - log2ceil(L3_NUM_WAYS), // W - 0, // A + log2ceil(L2_LINE_SIZE), // W + log2ceil(L3_NUM_WAYS), // A log2ceil(L3_NUM_BANKS), // B XLEN, // address bits 1, // number of ports @@ -58,7 +58,7 @@ ProcessorImpl::ProcessorImpl(const Arch& arch) l3cache_->CoreRspPorts.at(i).bind(&clusters_.at(i)->mem_rsp_port); } - // set up memory perf recording + // set up memory profiling memsim_->MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){ __unused (cycle); perf_mem_reads_ += !req.write; diff --git a/sim/simx/socket.cpp b/sim/simx/socket.cpp index dd9f9697..092e89d0 100644 --- a/sim/simx/socket.cpp +++ b/sim/simx/socket.cpp @@ -44,7 +44,7 @@ Socket::Socket(const SimContext& ctx, XLEN, // address bits 1, // number of ports 1, // number of inputs - true, // write-through + false, // write-through false, // write response (uint8_t)arch.num_warps(), // mshr 2, // pipeline latency