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data/dram bus refactoring

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Blaise Tine
2020-12-06 03:37:22 -08:00
parent d0f2a3984d
commit b2652527bb
9 changed files with 624 additions and 573 deletions
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6
hw/rtl/VX_config.vh
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@@ -267,8 +267,8 @@
// SM Configurable Knobs //////////////////////////////////////////////////////
// Size of cache in bytes
`ifndef SCACHE_SIZE
`define SCACHE_SIZE 4096
`ifndef SMEM_SIZE
`define SMEM_SIZE 4096
`endif
// Number of banks
@@ -295,7 +295,7 @@
// Number of banks
`ifndef L2NUM_BANKS
`define L2NUM_BANKS `MIN((`NUM_CORES * 2), 4)
`define L2NUM_BANKS `MIN(`NUM_CORES, 4)
`endif
// Core Request Queue Size