diff --git a/hw/rtl/VX_commit.v b/hw/rtl/VX_commit.v index 14fa7614..93c02eff 100644 --- a/hw/rtl/VX_commit.v +++ b/hw/rtl/VX_commit.v @@ -20,8 +20,6 @@ module VX_commit #( VX_writeback_if writeback_if, VX_cmt_to_csr_if cmt_to_csr_if ); - localparam CMTW = $clog2(3*`NUM_THREADS+1); - // CSRs update wire alu_commit_fire = alu_commit_if.valid && alu_commit_if.ready; @@ -42,30 +40,24 @@ module VX_commit #( `endif || gpu_commit_fire; - wire [`NUM_THREADS-1:0] commit_tmask1, commit_tmask2, commit_tmask3; - - assign commit_tmask1 = alu_commit_fire ? alu_commit_if.tmask: - ld_commit_fire ? ld_commit_if.tmask: - csr_commit_fire ? csr_commit_if.tmask: + wire [`NUM_THREADS-1:0] commit_tmask; + assign commit_tmask = alu_commit_fire ? alu_commit_if.tmask: + ld_commit_fire ? ld_commit_if.tmask: + st_commit_fire ? st_commit_if.tmask: + csr_commit_fire ? csr_commit_if.tmask: `ifdef EXT_F_ENABLE - fpu_commit_fire ? fpu_commit_if.tmask: + fpu_commit_fire ? fpu_commit_if.tmask: `endif - 0; - - assign commit_tmask2 = st_commit_fire ? st_commit_if.tmask : 0; - assign commit_tmask3 = gpu_commit_fire ? gpu_commit_if.tmask : 0; - - wire [CMTW-1:0] commit_size; - assign commit_size = $countones({commit_tmask3, commit_tmask2, commit_tmask1}); + /*gpu_commit_fire ?*/ gpu_commit_if.tmask; VX_pipe_register #( - .DATAW (1 + CMTW), + .DATAW (1 + $clog2(`NUM_THREADS+1)), .RESETW (1) ) pipe_reg ( .clk (clk), .reset (reset), .enable (1'b1), - .data_in ({commit_fire, commit_size}), + .data_in ({commit_fire, $countones(commit_tmask)}), .data_out ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size}) ); diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index b9a2ef5e..d4d61e44 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -51,9 +51,9 @@ module VX_lsu_unit #( end // detect duplicate addresses - wire [`NUM_THREADS-1:0] addr_matches; - for (genvar i = 0; i < `NUM_THREADS; i++) begin - assign addr_matches[i] = (full_addr[0] == full_addr[i]) || ~lsu_req_if.tmask[i]; + wire [`NUM_THREADS-2:0] addr_matches; + for (genvar i = 0; i < (`NUM_THREADS-1); i++) begin + assign addr_matches[i] = (lsu_req_if.base_addr[i+1] == lsu_req_if.base_addr[0]) || ~lsu_req_if.tmask[i+1]; end wire lsu_is_dup = lsu_req_if.tmask[0] && (& addr_matches); @@ -150,7 +150,7 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0] req_tmask_dup = req_tmask & {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1}; - wire req_ready_all = &(dcache_req_if.ready | req_sent_mask | ~req_tmask_dup); + wire dcache_req_ready = &(dcache_req_if.ready | req_sent_mask | ~req_tmask_dup); wire [`NUM_THREADS-1:0] req_sent_mask_n = req_sent_mask | dcache_req_fire; @@ -159,7 +159,7 @@ module VX_lsu_unit #( req_sent_mask <= 0; is_req_start <= 1; end else begin - if (req_ready_all) begin + if (dcache_req_ready) begin req_sent_mask <= 0; is_req_start <= 1; end else begin @@ -235,11 +235,11 @@ module VX_lsu_unit #( `endif end - assign ready_in = req_dep_ready && req_ready_all; + assign ready_in = req_dep_ready && dcache_req_ready; // send store commit - wire is_store_rsp = req_valid && ~req_wb && req_ready_all; + wire is_store_rsp = req_valid && ~req_wb && dcache_req_ready; assign st_commit_if.valid = is_store_rsp; assign st_commit_if.wid = req_wid; diff --git a/hw/rtl/cache/VX_core_rsp_merge.v b/hw/rtl/cache/VX_core_rsp_merge.v index 826cbb86..92ecefdd 100644 --- a/hw/rtl/cache/VX_core_rsp_merge.v +++ b/hw/rtl/cache/VX_core_rsp_merge.v @@ -48,7 +48,7 @@ module VX_core_rsp_merge #( // We first need to select the current tag to process, // then send all bank responses for that tag as a batch - reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; wire core_rsp_ready_unqual; if (NUM_PORTS > 1) begin @@ -74,19 +74,25 @@ module VX_core_rsp_merge #( end end - always @(*) begin - core_rsp_tag_unqual = 'x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - for (integer p = 0; p < NUM_PORTS; ++p) begin - if (per_bank_core_rsp_valid[i] - && per_bank_core_rsp_pmask[i][p] - && !per_bank_core_rsp_sent_r[i][p]) begin - core_rsp_tag_unqual = per_bank_core_rsp_tag[i][p]; - end - end + wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_rsp_valid_p; + for (genvar i = 0; i < NUM_BANKS; ++i) begin + for (genvar p = 0; p < NUM_PORTS; ++p) begin + assign per_bank_core_rsp_valid_p[i][p] = per_bank_core_rsp_valid[i] + && per_bank_core_rsp_pmask[i][p] + && !per_bank_core_rsp_sent_r[i][p]; end end + VX_find_first #( + .N (NUM_BANKS * NUM_PORTS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (per_bank_core_rsp_valid_p), + .data_i (per_bank_core_rsp_tag), + .data_o (core_rsp_tag_unqual), + `UNUSED_PIN (valid_o) + ); + always @(*) begin core_rsp_valid_unqual = 0; core_rsp_data_unqual = 'x; @@ -116,14 +122,15 @@ module VX_core_rsp_merge #( `UNUSED_VAR (per_bank_core_rsp_pmask) - always @(*) begin - core_rsp_tag_unqual = 'x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_rsp_valid[i]) begin - core_rsp_tag_unqual = per_bank_core_rsp_tag[i]; - end - end - end + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (per_bank_core_rsp_valid), + .data_i (per_bank_core_rsp_tag), + .data_o (core_rsp_tag_unqual), + `UNUSED_PIN (valid_o) + ); always @(*) begin core_rsp_valid_unqual = 0; diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index b7a60580..56dedf54 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -81,14 +81,14 @@ module VX_miss_resrv #( reg [MSHR_SIZE-1:0] valid_table_x; reg [MSHR_SIZE-1:0] ready_table_x; - wire [MSHR_SIZE-1:0] addr_match; + wire [MSHR_SIZE-1:0] addr_matches; wire allocate_fire = allocate_valid && allocate_ready; wire dequeue_fire = dequeue_valid && dequeue_ready; for (genvar i = 0; i < MSHR_SIZE; ++i) begin - assign addr_match[i] = (i != lookup_id) && valid_table[i] && (addr_table[i] == lookup_addr); + assign addr_matches[i] = (addr_table[i] == lookup_addr); end always @(*) begin @@ -98,12 +98,12 @@ module VX_miss_resrv #( valid_table_x[dequeue_id] = 0; end if (lookup_replay) begin - ready_table_x |= addr_match; + ready_table_x |= addr_matches; end end VX_lzc #( - .WIDTH (MSHR_SIZE) + .N (MSHR_SIZE) ) dequeue_sel ( .in_i (valid_table_x & ready_table_x), .cnt_o (dequeue_id_x), @@ -111,7 +111,7 @@ module VX_miss_resrv #( ); VX_lzc #( - .WIDTH (MSHR_SIZE) + .N (MSHR_SIZE) ) allocate_sel ( .in_i (~valid_table_n), .cnt_o (allocate_id_n), @@ -189,7 +189,11 @@ module VX_miss_resrv #( assign dequeue_id = dequeue_id_r; assign dequeue_addr = addr_table[dequeue_id_r]; - assign lookup_match = (| addr_match); + wire [MSHR_SIZE-1:0] lookup_entries; + for (genvar i = 0; i < MSHR_SIZE; ++i) begin + assign lookup_entries[i] = (i != lookup_id); + end + assign lookup_match = |(lookup_entries & valid_table & addr_matches); `UNUSED_VAR (lookup_valid) diff --git a/hw/rtl/cache/VX_nc_bypass.v b/hw/rtl/cache/VX_nc_bypass.v index 9ab575e2..d307b448 100644 --- a/hw/rtl/cache/VX_nc_bypass.v +++ b/hw/rtl/cache/VX_nc_bypass.v @@ -116,7 +116,7 @@ module VX_nc_bypass #( assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_tids; VX_lzc #( - .WIDTH (NUM_REQS) + .N (NUM_REQS) ) core_req_sel ( .in_i (core_req_valid_in_nc), .cnt_o (core_req_nc_tid), diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 00edeab0..1caa18ce 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -215,16 +215,17 @@ module VX_shared_mem #( reg [NUM_REQS-1:0] core_rsp_valids_in; reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_in; - reg [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; - - always @(*) begin - core_rsp_tag_in = 'x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_req_reads[i] && ~bank_rsp_sel_prv[i]) begin - core_rsp_tag_in = per_bank_core_req_tag[i]; - end - end - end + wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; + + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first ( + .valid_i (per_bank_req_reads & ~bank_rsp_sel_prv), + .data_i (per_bank_core_req_tag), + .data_o (core_rsp_tag_in), + `UNUSED_PIN (valid_o) + ); always @(*) begin core_rsp_valids_in = 0; @@ -280,14 +281,15 @@ module VX_shared_mem #( reg [CORE_TAG_WIDTH-1:0] core_req_tag_sel; `IGNORE_UNUSED_END - always @(*) begin - core_req_tag_sel ='x; - for (integer i = NUM_BANKS-1; i >= 0; --i) begin - if (per_bank_core_req_valid[i]) begin - core_req_tag_sel = per_bank_core_req_tag[i]; - end - end - end + VX_find_first #( + .N (NUM_BANKS), + .DATAW (CORE_TAG_WIDTH) + ) find_first_d ( + .valid_i (per_bank_core_req_valid), + .data_i (per_bank_core_req_tag), + .data_o (core_req_tag_sel), + `UNUSED_PIN (valid_o) + ); always @(*) begin is_multi_tag_req = 0; diff --git a/hw/rtl/interfaces/VX_cmt_to_csr_if.v b/hw/rtl/interfaces/VX_cmt_to_csr_if.v index d805f5b4..ce2549d6 100644 --- a/hw/rtl/interfaces/VX_cmt_to_csr_if.v +++ b/hw/rtl/interfaces/VX_cmt_to_csr_if.v @@ -5,8 +5,8 @@ interface VX_cmt_to_csr_if (); - wire valid; - wire [$clog2(3*`NUM_THREADS+1)-1:0] commit_size; + wire valid; + wire [$clog2(`NUM_THREADS+1)-1:0] commit_size; endinterface diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index d3d95709..67fd2cd0 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -68,8 +68,7 @@ module VX_skid_buffer #( end else begin if (ready_out) begin use_buffer <= 0; - end else if (push && valid_out_r) begin - assert(!use_buffer); + end else if (valid_in && valid_out_r) begin use_buffer <= 1; end if (pop) begin @@ -81,7 +80,7 @@ module VX_skid_buffer #( always @(posedge clk) begin if (push) begin buffer <= data_in; - end + end if (pop && !use_buffer) begin data_out_r <= data_in; end else if (ready_out) begin diff --git a/hw/rtl/libs/VX_stream_arbiter.v b/hw/rtl/libs/VX_stream_arbiter.v index b5edca24..b8da4f3f 100644 --- a/hw/rtl/libs/VX_stream_arbiter.v +++ b/hw/rtl/libs/VX_stream_arbiter.v @@ -42,22 +42,18 @@ module VX_stream_arbiter #( end if (TYPE == "X") begin - VX_fixed_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + `UNUSED_VAR (sel_ready) + VX_lzc #( + .N (NUM_REQS) ) sel_arb ( - .clk (clk), - .reset (reset), - .requests (valid_in_any), - .enable (sel_ready), - .grant_valid (sel_valid), - .grant_index (sel_index), - `UNUSED_PIN (grant_onehot) + .in_i (valid_in_any), + .cnt_o (sel_index), + .valid_o (sel_valid) ); end else if (TYPE == "R") begin VX_rr_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset), @@ -69,8 +65,8 @@ module VX_stream_arbiter #( ); end else if (TYPE == "F") begin VX_fair_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset), @@ -82,8 +78,8 @@ module VX_stream_arbiter #( ); end else if (TYPE == "M") begin VX_matrix_arbiter #( - .NUM_REQS(NUM_REQS), - .LOCK_ENABLE(LOCK_ENABLE) + .NUM_REQS (NUM_REQS), + .LOCK_ENABLE (LOCK_ENABLE) ) sel_arb ( .clk (clk), .reset (reset),