fixed assertion in lsu_unit
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@@ -13,6 +13,10 @@ Simulator::Simulator() {
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// force random values for unitialized signals
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Verilated::randReset(2);
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#ifdef NDEBUG
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Verilated::assertOn(false);
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#endif
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ram_ = nullptr;
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vortex_ = new VVortex();
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