wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fixed assertion in lsu_unit

Browse Source
This commit is contained in:
Blaise Tine
2020-06-26 00:27:55 -04:00
parent 62b91ff45a
commit b7d7e69f47
5 changed files with 30 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
driver/rtlsim/Makefile
View File

@@ -4,16 +4,17 @@ CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw
# control RTL debug print states # control RTL debug print states
DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
-DDBG_PRINT_CORE_DCACHE \ DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
-DDBG_PRINT_CACHE_BANK \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
-DDBG_PRINT_CACHE_SNP \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_SNP
-DDBG_PRINT_CACHE_MSRQ \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
-DDBG_PRINT_DRAM \ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
-DDBG_PRINT_PIPELINE \ DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
-DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
#DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4
@@ -46,13 +47,11 @@ VL_FLAGS += --x-assign unique
# Debugigng # Debugigng
ifdef DEBUG ifdef DEBUG
VL_FLAGS += --trace -DVCD_OUTPUT $(DBG_PRINT) VL_FLAGS += -DVCD_OUTPUT --assert --trace $(DBG_FLAGS)
CFLAGS += -DVCD_OUTPUT $(DBG_PRINT) CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
#VL_FLAGS += -DDBG_CORE_REQ_INFO
#CFLAGS += -DDBG_CORE_REQ_INFO
else else
CFLAGS += -DNDEBUG
VL_FLAGS += -DNDEBUG VL_FLAGS += -DNDEBUG
CFLAGS += -DNDEBUG
endif endif
# AFU # AFU

0
driver/tests/basic/kernel.bin Normal file → Executable file
View File

21
hw/simulate/Makefile
View File

@@ -3,16 +3,17 @@
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
# control RTL debug print states # control RTL debug print states
DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE
-DDBG_PRINT_CORE_DCACHE \ DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE
-DDBG_PRINT_CACHE_BANK \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK
-DDBG_PRINT_CACHE_SNP \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_SNP
-DDBG_PRINT_CACHE_MSRQ \ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
-DDBG_PRINT_DRAM \ DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
-DDBG_PRINT_PIPELINE \ DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
-DDBG_PRINT_OPAE DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_FLAGS += $(DBG_PRINT_FLAGS)
#DBG_FLAGS += -DDBG_CORE_REQ_INFO
INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate
@@ -27,7 +28,7 @@ VF += -Wno-DECLFILENAME
VF += --x-initial unique VF += --x-initial unique
VF += -exe $(SRCS) $(INCLUDE) VF += -exe $(SRCS) $(INCLUDE)
DBG += -DVCD_OUTPUT $(DBG_PRINT) DBG += -DVCD_OUTPUT $(DBG_FLAGS)
DBG += -DDBG_CORE_REQ_INFO DBG += -DDBG_CORE_REQ_INFO
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

4
hw/simulate/simulator.cpp
View File

@@ -13,6 +13,10 @@ Simulator::Simulator() {
// force random values for unitialized signals // force random values for unitialized signals
Verilated::randReset(2); Verilated::randReset(2);
#ifdef NDEBUG
Verilated::assertOn(false);
#endif
ram_ = nullptr; ram_ = nullptr;
vortex_ = new VVortex(); vortex_ = new VVortex();