wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

softfloat library integration

Browse Source
This commit is contained in:
Blaise Tine
2021-10-10 13:20:50 -07:00
parent 28e26f3130
commit b8682f56ac
21 changed files with 400 additions and 818 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
sim/Makefile
View File

@@ -1,9 +1,11 @@
all:
$(MAKE) -C common
$(MAKE) -C simX
$(MAKE) -C rtlsim
$(MAKE) -C vlsim
clean:
$(MAKE) -C common clean
$(MAKE) -C simX clean
$(MAKE) -C rtlsim clean
$(MAKE) -C vlsim clean

5
sim/common/Makefile Normal file
View File

@@ -0,0 +1,5 @@
all:
SPECIALIZE_TYPE=RISCV SOFTFLOAT_OPTS="-fPIC -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 -DSOFTFLOAT_FAST_DIV64TO32" $(MAKE) -C softfloat/build/Linux-x86_64-GCC
clean:
$(MAKE) -C softfloat/build/Linux-x86_64-GCC clean

1
sim/common/softfloat Submodule

Submodule sim/common/softfloat added at b64af41c32

84
sim/common/util.cpp
View File

@@ -1,90 +1,8 @@
#include "util.h"
#include <iostream>
#include <stdexcept>
#include <math.h>
#include <climits>
#include <string.h>
#include <bitset>
#include <fcntl.h>
using namespace vortex;
// Apply integer sign extension
uint32_t vortex::signExt(uint32_t w, uint32_t bit, uint32_t mask) {
if (w >> (bit - 1))
w |= ~mask;
return w;
}
// Convert a floating point number to IEEE-754 32-bit representation,
// so that it could be stored in a 32-bit integer register file
// Reference: https://www.wikihow.com/Convert-a-Number-from-Decimal-to-IEEE-754-Floating-Point-Representation
// https://www.technical-recipes.com/2012/converting-between-binary-and-decimal-representations-of-ieee-754-floating-point-numbers-in-c/
uint32_t vortex::floatToBin(float in_value) {
union {
float input; // assumes sizeof(float) == sizeof(int)
int output;
} data;
data.input = in_value;
std::bitset<sizeof(float) * CHAR_BIT> bits(data.output);
std::string mystring = bits.to_string<char, std::char_traits<char>, std::allocator<char>>();
// Convert binary to uint32_t
uint32_t result = stoul(mystring, nullptr, 2);
return result;
}
// https://en.wikipedia.org/wiki/Single-precision_floating-point_format
// check floating-point number in binary format is NaN
uint8_t vortex::fpBinIsNan(uint32_t din) {
bool fsign = din & 0x80000000;
uint32_t expo = (din>>23) & 0x000000FF;
uint32_t fraction = din & 0x007FFFFF;
uint32_t bit_22 = din & 0x00400000;
if ((expo==0xFF) && (fraction!=0)) {
// if (!fsign && (fraction == 0x00400000))
if (!fsign && (bit_22))
return 1; // quiet NaN, return 1
else
return 2; // signaling NaN, return 2
}
return 0;
}
// check floating-point number in binary format is zero
uint8_t vortex::fpBinIsZero(uint32_t din) {
bool fsign = din & 0x80000000;
uint32_t expo = (din>>23) & 0x000000FF;
uint32_t fraction = din & 0x007FFFFF;
if ((expo==0) && (fraction==0)) {
if (fsign)
return 1; // negative 0
else
return 2; // positive 0
}
return 0; // not zero
}
// check floating-point number in binary format is infinity
uint8_t vortex::fpBinIsInf(uint32_t din) {
bool fsign = din & 0x80000000;
uint32_t expo = (din>>23) & 0x000000FF;
uint32_t fraction = din & 0x007FFFFF;
if ((expo==0xFF) && (fraction==0)) {
if (fsign)
return 1; // negative infinity
else
return 2; // positive infinity
}
return 0; // not infinity
}
// return file extension
const char* vortex::fileExtension(const char* filepath) {
const char* fileExtension(const char* filepath) {
const char *ext = strrchr(filepath, '.');
if (ext == NULL || ext == filepath)
return "";

24
sim/common/util.h
View File

@@ -3,8 +3,6 @@
#include <cstdint>
#include <assert.h>
namespace vortex {
template <typename... Args>
void unused(Args&&...) {}
@@ -24,21 +22,11 @@ inline uint64_t align_size(uint64_t size, uint64_t alignment) {
}
// Apply integer sign extension
uint32_t signExt(uint32_t w, uint32_t bit, uint32_t mask);
// Convert a floating point number to IEEE-754 32-bit representation
uint32_t floatToBin(float in_value);
// check floating-point number in binary format is NaN
uint8_t fpBinIsNan(uint32_t din);
// check floating-point number in binary format is zero
uint8_t fpBinIsZero(uint32_t din);
// check floating-point number in binary format is infinity
uint8_t fpBinIsInf(uint32_t din);
inline uint32_t signExt(uint32_t w, uint32_t bit, uint32_t mask) {
if (w >> (bit - 1))
w |= ~mask;
return w;
}
// return file extension
const char* fileExtension(const char* filepath);
}
const char* fileExtension(const char* filepath);

47
sim/rtlsim/Makefile
View File

@@ -1,8 +1,12 @@
CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
#CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
RTL_DIR=../../hw/rtl
DPI_DIR=../../hw/dpi
CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors
CXXFLAGS += -fPIC -Wno-maybe-uninitialized
CXXFLAGS += -I../../../hw -I../../common
CXXFLAGS += -I../../common/softfloat/source/include
LDFLAGS += ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a
# control RTL debug print states
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
@@ -21,16 +25,10 @@ DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CACHE_REQ_INFO
DBG_FLAGS += -DVCD_OUTPUT
SINGLECORE = -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0
MULTICORE = -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
RTL_DIR=../../hw/rtl
DPI_DIR=../../hw/dpi
FPU_INCLUDE = -I$(RTL_DIR)/fp_cores -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include -I$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src -I$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(RTL_DIR)/fp_cores/fpnew/src
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
SRCS = ../common/util.cpp ../common/mem.cpp
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
SRCS += main.cpp simulator.cpp
@@ -52,10 +50,10 @@ VL_FLAGS += $(RTL_INCLUDE)
# Debugigng
ifdef DEBUG
VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)
CXXFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS)
else
VL_FLAGS += -DNDEBUG
CXXFLAGS += -DNDEBUG
CXXFLAGS += -O2 -DNDEBUG
endif
# Enable perf counters
@@ -69,36 +67,21 @@ VL_FLAGS += -DIMUL_DPI
VL_FLAGS += -DIDIV_DPI
# FPU backend
FPU_CORE ?= FPU_FPNEW
FPU_CORE ?= FPU_DPI
VL_FLAGS += -D$(FPU_CORE)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
PROJECT = rtlsim
all: build-s
all: $(PROJECT)
build-s: $(SRCS)
verilator --build $(VL_FLAGS) -DNDEBUG $(SRCS) $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' -o ../$(PROJECT)
$(PROJECT): $(SRCS)
verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
build-sd: $(SRCS)
verilator --build $(VL_FLAGS) $(SRCS) $(SINGLECORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(SINGLECORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT)
build-st: $(SRCS)
verilator --build $(VL_FLAGS) -DNDEBUG $(SRCS) $(SINGLECORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(SINGLECORE)' --threads $(THREADS) -o ../$(PROJECT)
build-m: $(SRCS)
verilator --build $(VL_FLAGS) -DNDEBUG $(SRCS) $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' -o ../$(PROJECT)
build-md: $(SRCS)
verilator --build $(VL_FLAGS) $(SRCS) $(MULTICORE) -CFLAGS '$(CXXFLAGS) $(DBG_FLAGS) $(MULTICORE)' --trace --trace-structs $(DBG_FLAGS) -o ../$(PROJECT)
build-mt: $(SRCS)
verilator --build $(VL_FLAGS) -DNDEBUG $(SRCS) $(MULTICORE) -CFLAGS '$(CXXFLAGS) -DNDEBUG $(MULTICORE)' --threads $(THREADS) -o ../$(PROJECT)
static: $(SRCS)
verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)'
$(AR) rs lib$(PROJECT).a obj_dir/*.o
verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)'
$(AR) rcs lib$(PROJECT).a obj_dir/*.o
clean-static:
rm -rf lib$(PROJECT).a obj_dir

22
sim/simX/Makefile
View File

@@ -1,17 +1,15 @@
#CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
RTL_DIR = ../hw/rtl
CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors
CXXFLAGS += -fPIC -Wno-maybe-uninitialized
CXXFLAGS += -I. -I../common -I../../hw
CXXFLAGS += -DDUMP_PERF_STATS
CXXFLAGS += -I../common/softfloat/source/include
LDFLAGS += ../common/softfloat/build/Linux-x86_64-GCC/softfloat.a
TOP = vx_cache_sim
RTL_DIR = ../hw/rtl
PROJECT = simX
SRCS = ../common/util.cpp ../common/mem.cpp
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += args.cpp pipeline.cpp warp.cpp core.cpp decode.cpp execute.cpp main.cpp
OBJS := $(patsubst %.cpp, obj_dir/%.o, $(notdir $(SRCS)))
@@ -22,11 +20,13 @@ VPATH := $(sort $(dir $(SRCS)))
# Debugigng
ifdef DEBUG
CXXFLAGS += -DDEBUG_LEVEL=$(DEBUG)
CXXFLAGS += -g -O0 -DDEBUG_LEVEL=$(DEBUG)
else
CXXFLAGS += -DNDEBUG
CXXFLAGS += -O2 -DNDEBUG
endif
PROJECT = simX
all: $(PROJECT)
$(PROJECT): $(SRCS)
@@ -37,7 +37,7 @@ obj_dir/%.o: %.cpp
$(CXX) $(CXXFLAGS) -c $< -o $@
static: $(OBJS)
$(AR) rs lib$(PROJECT).a $(OBJS)
$(AR) rcs lib$(PROJECT).a $(OBJS)
.depend: $(SRCS)
$(CXX) $(CXXFLAGS) -MM $^ > .depend;

440
sim/simX/execute.cpp
View File

@@ -6,9 +6,9 @@
#include <climits>
#include <sys/types.h>
#include <sys/stat.h>
#include <cfenv>
#include <assert.h>
#include <util.h>
#include <rvfloats.h>
#include "warp.h"
#include "instr.h"
#include "core.h"
@@ -38,30 +38,14 @@ static bool HasDivergentThreads(const ThreadMask &thread_mask,
return false;
}
static void update_fcrs(Core* core, int tid, int wid, bool outOfRange = false) {
if (fetestexcept(FE_INEXACT)) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x1, tid, wid); // set NX bit
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x1, tid, wid); // set NX bit
}
if (fetestexcept(FE_UNDERFLOW)) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x2, tid, wid); // set UF bit
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x2, tid, wid); // set UF bit
}
inline uint32_t get_fpu_rm(uint32_t func3, Core* core, uint32_t tid, uint32_t wid) {
return (func3 == 0x7) ? core->get_csr(CSR_FRM, tid, wid) : func3;
}
if (fetestexcept(FE_OVERFLOW)) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x4, tid, wid); // set OF bit
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x4, tid, wid); // set OF bit
}
if (fetestexcept(FE_DIVBYZERO)) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x8, tid, wid); // set DZ bit
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x8, tid, wid); // set DZ bit
}
if (fetestexcept(FE_INVALID) || outOfRange) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | 0x10, tid, wid); // set NV bit
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | 0x10, tid, wid); // set NV bit
inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid) {
if (fflags) {
core->set_csr(CSR_FCSR, core->get_csr(CSR_FCSR, tid, wid) | fflags, tid, wid);
core->set_csr(CSR_FFLAGS, core->get_csr(CSR_FFLAGS, tid, wid) | fflags, tid, wid);
}
}
@@ -514,320 +498,120 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
}
}
break;
case FCI: // floating point computational instruction
case FCI: {
uint32_t frm = get_fpu_rm(func3, core_, t, id_);
uint32_t fflags = 0;
switch (func7) {
case 0x00: //FADD
case 0x04: //FSUB
case 0x08: //FMUL
case 0x0c: //FDIV
case 0x2c: //FSQRT
{
if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) {
// if one of op is NaN, one of them is not quiet NaN, them set FCSR
if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) {
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
}
if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1]))
rddata = 0x7fc00000; // canonical(quiet) NaN
else if (fpBinIsNan(rsdata[0]))
rddata = rsdata[1];
else
rddata = rsdata[0];
} else {
float fpsrc_0 = *(float*)&rsdata[0];
float fpsrc_1 = *(float*)&rsdata[1];
float fpDest;
feclearexcept(FE_ALL_EXCEPT);
if (func7 == 0x00) // FADD
fpDest = fpsrc_0 + fpsrc_1;
else if (func7==0x04) // FSUB
fpDest = fpsrc_0 - fpsrc_1;
else if (func7==0x08) // FMUL
fpDest = fpsrc_0 * fpsrc_1;
else if (func7==0x0c) // FDIV
fpDest = fpsrc_0 / fpsrc_1;
else if (func7==0x2c) // FSQRT
fpDest = sqrt(fpsrc_0);
else {
std::abort();
}
// update fcsrs
update_fcrs(core_, t, id_);
D(3, "fpDest: " << fpDest);
if (fpBinIsNan(floatToBin(fpDest)) == 0) {
rddata = floatToBin(fpDest);
} else {
// According to risc-v spec p.64 section 11.3
// If the result is NaN, it is the canonical NaN
rddata = 0x7fc00000;
}
}
} break;
// FSGNJ.S, FSGNJN.S, FSGNJX.S
case 0x10: {
bool fsign1 = rsdata[0] & 0x80000000;
uint32_t fdata1 = rsdata[0] & 0x7FFFFFFF;
bool fsign2 = rsdata[1] & 0x80000000;
switch (func3) {
case 0: // FSGNJ.S
rddata = (fsign2 << 31) | fdata1;
break;
case 1: // FSGNJN.S
fsign2 = !fsign2;
rddata = (fsign2 << 31) | fdata1;
break;
case 2: { // FSGNJX.S
bool sign = fsign1 ^ fsign2;
rddata = (sign << 31) | fdata1;
} break;
}
} break;
// FMIN.S, FMAX.S
case 0x14: {
if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) { // if one of src is NaN
// one of them is not quiet NaN, them set FCSR
if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2)) {
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
}
if (fpBinIsNan(rsdata[0]) && fpBinIsNan(rsdata[1]))
rddata = 0x7fc00000; // canonical(quiet) NaN
else if (fpBinIsNan(rsdata[0]))
rddata = rsdata[1];
else
rddata = rsdata[0];
} else {
uint8_t sr0IsZero = fpBinIsZero(rsdata[0]);
uint8_t sr1IsZero = fpBinIsZero(rsdata[1]);
if (sr0IsZero && sr1IsZero && (sr0IsZero != sr1IsZero)) {
// both are zero and not equal
// handle corner case that compare +0 and -0
if (func3) {
// FMAX.S
rddata = (sr1IsZero==2) ? rsdata[1] : rsdata[0];
} else {
// FMIM.S
rddata = (sr1IsZero==2) ? rsdata[0] : rsdata[1];
}
} else {
float rs1 = *(float*)&rsdata[0];
float rs2 = *(float*)&rsdata[1];
if (func3) {
// FMAX.S
float fmax = std::max(rs1, rs2);
rddata = floatToBin(fmax);
} else {
// FMIN.S
float fmin = std::min(rs1, rs2);
rddata = floatToBin(fmin);
}
}
}
} break;
// FCVT.W.S FCVT.WU.S
case 0x60: {
float fpSrc = *(float*)&rsdata[0];
Word result;
bool outOfRange = false;
if (rsrc1 == 0) {
// FCVT.W.S
// Convert floating point to 32-bit signed integer
if (fpSrc > pow(2.0, 31) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) {
feclearexcept(FE_ALL_EXCEPT);
outOfRange = true;
// result = 2^31 - 1
result = 0x7FFFFFFF;
} else if (fpSrc < -1*pow(2.0, 31) || fpBinIsInf(rsdata[0]) == 1) {
feclearexcept(FE_ALL_EXCEPT);
outOfRange = true;
// result = -1*2^31
result = 0x80000000;
} else {
feclearexcept(FE_ALL_EXCEPT);
result = (int32_t) fpSrc;
}
} else {
// FCVT.WU.S
// Convert floating point to 32-bit unsigned integer
if (fpSrc > pow(2.0, 32) - 1 || fpBinIsNan(rsdata[0]) || fpBinIsInf(rsdata[0]) == 2) {
feclearexcept(FE_ALL_EXCEPT);
outOfRange = true;
// result = 2^32 - 1
result = 0xFFFFFFFF;
} else if (fpSrc <= -1.0 || fpBinIsInf(rsdata[0]) == 1) {
feclearexcept(FE_ALL_EXCEPT);
outOfRange = true;
// result = 0
result = 0x00000000;
} else {
feclearexcept(FE_ALL_EXCEPT);
result = (uint32_t) fpSrc;
}
}
// update fcsrs
update_fcrs(core_, t, id_, outOfRange);
rddata = result;
} break;
// FMV.X.W FCLASS.S
case 0x70: {
// FCLASS.S
if (func3) {
// Examine the value in fpReg rs1 and write to integer rd
// a 10-bit mask to indicate the class of the fp number
rddata = 0; // clear all bits
bool fsign = rsdata[0] & 0x80000000;
uint32_t expo = (rsdata[0]>>23) & 0x000000FF;
uint32_t fraction = rsdata[0] & 0x007FFFFF;
if ((expo==0) && (fraction==0)) {
rddata = fsign ? (1<<3) : (1<<4); // +/- 0
} else if ((expo==0) && (fraction!=0)) {
rddata = fsign ? (1<<2) : (1<<5); // +/- subnormal
} else if ((expo==0xFF) && (fraction==0)) {
rddata = fsign ? (1<<0) : (1<<7); // +/- infinity
} else if ((expo==0xFF) && (fraction!=0)) {
if (!fsign && (fraction == 0x00400000)) {
rddata = (1<<9); // quiet NaN
} else {
rddata = (1<<8); // signaling NaN
}
} else {
rddata = fsign ? (1<<1) : (1<<6); // +/- normal
}
} else {
// FMV.X.W
// Move bit values from floating-point register rs1 to integer register rd
// Since we are using integer register to represent floating point register,
// just simply assign here.
rddata = rsdata[0];
}
} break;
// FEQ.S FLT.S FLE.S
// rdest is integer register
case 0x50: {
// TODO: FLT.S and FLE.S perform IEEE 754-2009, signaling comparisons, set
// TODO: the invalid operation exception flag if either input is NaN
if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1])) {
// FLE.S or FLT.S
if (func3 == 0 || func3 == 1) {
// If either input is NaN, set NV bit
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
} else { // FEQ.S
// Only set NV bit if it is signaling NaN
if (fpBinIsNan(rsdata[0]) == 2 || fpBinIsNan(rsdata[1]) == 2) {
// If either input is NaN, set NV bit
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
}
}
// The result is 0 if either operand is NaN
rddata = 0;
} else {
switch(func3) {
case 0: {
// FLE.S
rddata = (*(float*)&rsdata[0] <= *(float*)&rsdata[1]);
} break;
case 1: {
// FLT.S
rddata = (*(float*)&rsdata[0] < *(float*)&rsdata[1]);
} break;
case 2: {
// FEQ.S
rddata = (*(float*)&rsdata[0] == *(float*)&rsdata[1]);
} break;
default:
std::abort();
}
}
} break;
case 0x68:
// Cast integer to floating point
if (rsrc1) {
// FCVT.S.WU: convert 32-bit unsigned integer to floating point
float data = rsdata[0];
rddata = floatToBin(data);
} else {
// FCVT.S.W: convert 32-bit signed integer to floating point
// rsdata[0] is actually a unsigned number
float data = (WordI)rsdata[0];
rddata = floatToBin(data);
}
case 0x00: //FADD
rddata = rv_fadd(rsdata[0], rsdata[1], frm, &fflags);
break;
case 0x78: {
// FMV.W.X
// Move bit values from integer register rs1 to floating register rd
// Since we are using integer register to represent floating point register,
// just simply assign here.
rddata = rsdata[0];
case 0x04: //FSUB
rddata = rv_fsub(rsdata[0], rsdata[1], frm, &fflags);
break;
case 0x08: //FMUL
rddata = rv_fmul(rsdata[0], rsdata[1], frm, &fflags);
break;
case 0x0c: //FDIV
rddata = rv_fdiv(rsdata[0], rsdata[1], frm, &fflags);
break;
case 0x2c: //FSQRT
rddata = rv_fsqrt(rsdata[0], frm, &fflags);
break;
case 0x10:
switch (func3) {
case 0: // FSGNJ.S
rddata = rv_fsgnj(rsdata[0], rsdata[1]);
break;
case 1: // FSGNJN.S
rddata = rv_fsgnjn(rsdata[0], rsdata[1]);
break;
case 2: // FSGNJX.S
rddata = rv_fsgnjx(rsdata[0], rsdata[1]);
break;
}
break;
case 0x14:
if (func3) {
// FMAX.S
rddata = rv_fmax(rsdata[0], rsdata[1], &fflags);
} else {
// FMIN.S
rddata = rv_fmin(rsdata[0], rsdata[1], &fflags);
}
break;
case 0x60:
if (rsrc1 == 0) {
// FCVT.W.S
rddata = rv_ftoi(rsdata[0], frm, &fflags);
} else {
// FCVT.WU.S
rddata = rv_ftou(rsdata[0], frm, &fflags);
}
break;
case 0x70:
if (func3) {
// FCLASS.S
rddata = rv_fclss(rsdata[0]);
} else {
// FMV.X.W
rddata = rsdata[0];
}
break;
case 0x50:
switch(func3) {
case 0:
// FLE.S
rddata = rv_fle(rsdata[0], rsdata[1], &fflags);
break;
case 1:
// FLT.S
rddata = rv_flt(rsdata[0], rsdata[1], &fflags);
break;
case 2:
// FEQ.S
rddata = rv_feq(rsdata[0], rsdata[1], &fflags);
break;
} break;
case 0x68:
if (rsrc1) {
// FCVT.S.WU:
rddata = rv_utof(rsdata[0], frm, &fflags);
} else {
// FCVT.S.W:
rddata = rv_itof(rsdata[0], frm, &fflags);
}
break;
case 0x78:
// FMV.W.X
rddata = rsdata[0];
break;
}
update_fcrs(fflags, core_, t, id_);
rd_write = true;
break;
} break;
case FMADD:
case FMSUB:
case FMNMADD:
case FMNMSUB: {
// multiplicands are infinity and zero, them set FCSR
if (fpBinIsZero(rsdata[0]) || fpBinIsZero(rsdata[1]) || fpBinIsInf(rsdata[0]) || fpBinIsInf(rsdata[1])) {
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
}
if (fpBinIsNan(rsdata[0]) || fpBinIsNan(rsdata[1]) || fpBinIsNan(rsdata[2])) {
// if one of op is NaN, if addend is not quiet NaN, them set FCSR
if ((fpBinIsNan(rsdata[0])==2) | (fpBinIsNan(rsdata[1])==2) | (fpBinIsNan(rsdata[1])==2)) {
core_->set_csr(CSR_FCSR, core_->get_csr(CSR_FCSR, t, id_) | 0x10, t, id_); // set NV bit
core_->set_csr(CSR_FFLAGS, core_->get_csr(CSR_FFLAGS, t, id_) | 0x10, t, id_); // set NV bit
}
rddata = 0x7fc00000; // canonical(quiet) NaN
} else {
float rs1 = *(float*)&rsdata[0];
float rs2 = *(float*)&rsdata[1];
float rs3 = *(float*)&rsdata[2];
float fpDest(0.0);
feclearexcept(FE_ALL_EXCEPT);
switch (opcode) {
case FMADD:
// rd = (rs1*rs2)+rs3
fpDest = (rs1 * rs2) + rs3; break;
case FMSUB:
// rd = (rs1*rs2)-rs3
fpDest = (rs1 * rs2) - rs3; break;
case FMNMADD:
// rd = -(rs1*rs2)+rs3
fpDest = -1*(rs1 * rs2) - rs3; break;
case FMNMSUB:
// rd = -(rs1*rs2)-rs3
fpDest = -1*(rs1 * rs2) + rs3; break;
default:
std::abort();
break;
}
// update fcsrs
update_fcrs(core_, t, id_);
rddata = floatToBin(fpDest);
}
int frm = get_fpu_rm(func3, core_, t, id_);
Word fflags = 0;
switch (opcode) {
case FMADD:
rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
break;
case FMSUB:
rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
break;
case FMNMADD:
rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
break;
case FMNMSUB:
rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
break;
default:
break;
}
update_fcrs(fflags, core_, t, id_);
rd_write = true;
} break;
case GPGPU:

25
sim/vlsim/Makefile
View File

@@ -1,8 +1,13 @@
CXXFLAGS += -std=c++11 -O2 -Wall -Wextra -Wfatal-errors
#CXXFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
RTL_DIR = ../../hw/rtl
DPI_DIR = ../../hw/dpi
SCRIPT_DIR=../../hw/scripts
CXXFLAGS += -std=c++11 -Wall -Wextra -Wfatal-errors
CXXFLAGS += -fPIC -Wno-maybe-uninitialized
CXXFLAGS += -I.. -I../../../hw -I../../common
CXXFLAGS += -I../../common/softfloat/source/include
LDFLAGS += -shared ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a
# control RTL debug print states
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
@@ -23,15 +28,9 @@ DBG_FLAGS += -DDBG_CACHE_REQ_INFO
CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1
CXXFLAGS += $(CONFIGS)
CXXFLAGS += -DDUMP_PERF_STATS
CXXFLAGS += -D
LDFLAGS += -shared
RTL_DIR = ../../hw/rtl
DPI_DIR = ../../hw/dpi
SCRIPT_DIR=../../hw/scripts
SRCS = ../common/util.cpp ../common/mem.cpp
SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
SRCS += fpga.cpp opae_sim.cpp
@@ -56,10 +55,10 @@ VL_FLAGS += $(RTL_INCLUDE)
# Debugigng
ifdef DEBUG
VL_FLAGS += -DVCD_OUTPUT --trace --trace-structs $(DBG_FLAGS)
CXXFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
CXXFLAGS += -g -O0 -DVCD_OUTPUT $(DBG_FLAGS)
else
VL_FLAGS += -DNDEBUG
CXXFLAGS += -DNDEBUG
CXXFLAGS += -O2 -DNDEBUG
endif
# Enable scope analyzer
@@ -98,7 +97,7 @@ shared: $(SRCS) vortex_afu.h
static: $(SRCS) vortex_afu.h
verilator --build $(VL_FLAGS) $(SRCS) -CFLAGS '$(CXXFLAGS)' -LDFLAGS '$(LDFLAGS)'
$(AR) rs $(PROJECT).a obj_dir/*.o
$(AR) rcs $(PROJECT).a obj_dir/*.o
clean-static:
rm -rf $(PROJECT).a obj_dir vortex_afu.h