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minor updates

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This commit is contained in:
Blaise Tine
2020-05-28 18:34:03 -04:00
parent 611ceb000a
commit b930a822ad
11 changed files with 7005 additions and 17473 deletions
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6
driver/rtlsim/Makefile
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@@ -12,13 +12,13 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_DRAM \ -DDBG_PRINT_DRAM \
-DDBG_PRINT_OPAE -DDBG_PRINT_OPAE
DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_PRINT=$(DBG_PRINT_FLAGS)
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 #MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
DEBUG = 1 #DEBUG = 1
CFLAGS += -fPIC CFLAGS += -fPIC

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driver/tests/basic/kernel.bin
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driver/tests/demo/kernel.bin
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driver/tests/demo/kernel.elf
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24418
driver/tests/demo/run.log
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2
hw/Makefile
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@@ -25,7 +25,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
-DDBG_PRINT_DRAM \ -DDBG_PRINT_DRAM \
-DDBG_PRINT_OPAE -DDBG_PRINT_OPAE
DBG_PRINT=$(DBG_PRINT_FLAGS) #DBG_PRINT=$(DBG_PRINT_FLAGS)
INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate

6
hw/rtl/VX_lsu_unit.v
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@@ -107,9 +107,9 @@ module VX_lsu_unit #(
assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0];
wire [`NUM_THREADS-1:0] mem_rsp_mask_next = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid; wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid;
wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_next); wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd);
VX_indexable_queue #( VX_indexable_queue #(
.DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 5) + `BYTE_EN_BITS + 5 + `NW_BITS), .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 5) + `BYTE_EN_BITS + 5 + `NW_BITS),
@@ -134,7 +134,7 @@ module VX_lsu_unit #(
mem_rsp_mask[mrq_write_addr] <= use_valid; mem_rsp_mask[mrq_write_addr] <= use_valid;
end end
if (mrq_pop_part) begin if (mrq_pop_part) begin
mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_next; mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
assert(mrq_read_addr == dbg_mrq_write_addr); assert(mrq_read_addr == dbg_mrq_write_addr);
end end
end end

3
hw/rtl/Vortex_Cluster.v
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@@ -397,8 +397,7 @@ module Vortex_Cluster #(
.BANK_LINE_SIZE(`L2BANK_LINE_SIZE), .BANK_LINE_SIZE(`L2BANK_LINE_SIZE),
.NUM_REQUESTS(`NUM_CORES), .NUM_REQUESTS(`NUM_CORES),
.SNRQ_SIZE(`L2SNRQ_SIZE), .SNRQ_SIZE(`L2SNRQ_SIZE),
.SNP_REQ_TAG_WIDTH(`L2SNP_TAG_WIDTH), .SNP_REQ_TAG_WIDTH(`L2SNP_TAG_WIDTH)
.SNP_FWD_TAG_WIDTH(`DSNP_TAG_WIDTH)
) snp_forwarder ( ) snp_forwarder (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

24
hw/rtl/cache/VX_bank.v vendored
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@@ -717,6 +717,12 @@ module VX_bank #(
`ifdef DBG_PRINT_CACHE_BANK `ifdef DBG_PRINT_CACHE_BANK
if (NUM_BANKS == 1) begin if (NUM_BANKS == 1) begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
/*if (core_req_valid && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(core_req_addr), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
if (dram_fill_req_valid && dram_fill_req_ready) begin if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr)); $display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_req_addr));
end end
@@ -726,9 +732,21 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data); $display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(dram_fill_rsp_addr), dram_fill_rsp_data);
end end
/*if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR0(snp_req_addr), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end end
end else begin end else begin
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
/*if ((|core_req_valid) && core_req_ready) begin
$display("%t: bank%01d%01d core req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(core_req_addr, BANK_ID), core_req_tag);
end
if (core_rsp_valid && core_rsp_ready) begin
$display("%t: bank%01d%01d core rsp: tag=%0h, data=%0h", $time, CACHE_ID, BANK_ID, core_rsp_tag, core_rsp_data);
end*/
if (dram_fill_req_valid && dram_fill_req_ready) begin if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID)); $display("%t: bank%01d%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end end
@@ -738,6 +756,12 @@ module VX_bank #(
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data); $display("%t: bank%01d%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end end
/*if (snp_req_valid && snp_req_ready) begin
$display("%t: bank%01d%01d snp req: addr=%0h, tag=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(snp_req_addr, BANK_ID), snp_req_tag);
end
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: bank%01d%01d snp rsp: tag=%0h", $time, CACHE_ID, BANK_ID, snp_rsp_tag);
end*/
end end
end end
`endif `endif

3
hw/rtl/cache/VX_cache.v vendored
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@@ -172,8 +172,7 @@ module VX_cache #(
.BANK_LINE_SIZE (BANK_LINE_SIZE), .BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_REQUESTS (NUM_SNP_REQUESTS), .NUM_REQUESTS (NUM_SNP_REQUESTS),
.SNRQ_SIZE (SNRQ_SIZE), .SNRQ_SIZE (SNRQ_SIZE),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH), .SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
.SNP_FWD_TAG_WIDTH (SNP_FWD_TAG_WIDTH)
) snp_forwarder ( ) snp_forwarder (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

14
hw/rtl/cache/VX_snp_forwarder.v vendored
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@@ -25,12 +25,12 @@ module VX_snp_forwarder #(
// Snoop Forwarding out // Snoop Forwarding out
output wire [NUM_REQUESTS-1:0] snp_fwdout_valid, output wire [NUM_REQUESTS-1:0] snp_fwdout_valid,
output wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr, output wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdout_tag, output wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdout_tag,
input wire [NUM_REQUESTS-1:0] snp_fwdout_ready, input wire [NUM_REQUESTS-1:0] snp_fwdout_ready,
// Snoop forwarding in // Snoop forwarding in
input wire [NUM_REQUESTS-1:0] snp_fwdin_valid, input wire [NUM_REQUESTS-1:0] snp_fwdin_valid,
input wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag, input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
); );
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
@@ -40,7 +40,7 @@ module VX_snp_forwarder #(
wire sfq_push, sfq_pop, sfq_full; wire sfq_push, sfq_pop, sfq_full;
wire fwdin_valid; wire fwdin_valid;
wire [SNP_FWD_TAG_WIDTH-1:0] fwdin_tag; wire [`LOG2UP(SNRQ_SIZE)-1:0] fwdin_tag;
wire fwdin_ready = snp_rsp_ready; wire fwdin_ready = snp_rsp_ready;
wire fwdin_taken = fwdin_valid && fwdin_ready; wire fwdin_taken = fwdin_valid && fwdin_ready;
@@ -49,9 +49,9 @@ module VX_snp_forwarder #(
assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[sfq_read_addr]); // send response assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[sfq_read_addr]); // send response
assign sfq_read_addr = fwdin_tag[`LOG2UP(SNRQ_SIZE)-1:0]; assign sfq_read_addr = fwdin_tag;
assign sfq_push = snp_req_valid && fwdout_ready; assign sfq_push = snp_req_valid && !sfq_full && fwdout_ready;
assign sfq_pop = snp_rsp_valid; assign sfq_pop = snp_rsp_valid;
VX_indexable_queue #( VX_indexable_queue #(
@@ -111,10 +111,10 @@ module VX_snp_forwarder #(
`ifdef DBG_PRINT_CACHE_SNP `ifdef DBG_PRINT_CACHE_SNP
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin if (snp_req_valid && snp_req_ready) begin
$display("%t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag); $display("%t: snp req: addr=%0h, tag=%0h", $time, {snp_req_addr, `LOG2UP(BANK_LINE_SIZE)'(0)}, snp_req_tag);
end end
if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]); $display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, {snp_fwdout_addr[0], `LOG2UP(BANK_LINE_SIZE)'(0)}, snp_fwdout_tag[0]);
end end
if (fwdin_valid && fwdin_ready) begin if (fwdin_valid && fwdin_ready) begin
$display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag); $display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);