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cocogfx fixes and refactoring

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This commit is contained in:
Blaise Tine
2021-11-25 13:58:09 -05:00
parent a671e1a05d
commit b995843a5b
44 changed files with 339 additions and 3921 deletions
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11
hw/rtl/tex_unit/VX_tex_define.vh
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@@ -24,11 +24,12 @@
`define TEX_BLEND_FRAC 8
`define TEX_BLEND_ONE (2 ** `TEX_BLEND_FRAC)
`define TEX_FORMAT_R8G8B8A8 `TEX_FORMAT_BITS'(0)
`define TEX_FORMAT_A8R8G8B8 `TEX_FORMAT_BITS'(0)
`define TEX_FORMAT_R5G6B5 `TEX_FORMAT_BITS'(1)
`define TEX_FORMAT_R4G4B4A4 `TEX_FORMAT_BITS'(2)
`define TEX_FORMAT_L8A8 `TEX_FORMAT_BITS'(3)
`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(4)
`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(5)
`define TEX_FORMAT_A1R5G5B5 `TEX_FORMAT_BITS'(2)
`define TEX_FORMAT_A4R4G4B4 `TEX_FORMAT_BITS'(3)
`define TEX_FORMAT_A8L8 `TEX_FORMAT_BITS'(4)
`define TEX_FORMAT_L8 `TEX_FORMAT_BITS'(5)
`define TEX_FORMAT_A8 `TEX_FORMAT_BITS'(6)
`endif

26
hw/rtl/tex_unit/VX_tex_format.sv
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@@ -13,25 +13,31 @@ module VX_tex_format #(
always @(*) begin
case (format)
`TEX_FORMAT_R8G8B8A8: begin
`TEX_FORMAT_A8R8G8B8: begin
texel_out_r[07:00] = texel_in[7:0];
texel_out_r[15:08] = texel_in[15:8];
texel_out_r[23:16] = texel_in[23:16];
texel_out_r[31:24] = texel_in[31:24];
end
`TEX_FORMAT_R5G6B5: begin
texel_out_r[07:00] = {texel_in[15:11], texel_in[15:13]};
texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]};
texel_out_r[15:08] = {texel_in[10:5], texel_in[10:9]};
texel_out_r[23:16] = {texel_in[4:0], texel_in[4:2]};
texel_out_r[23:16] = {texel_in[15:11], texel_in[15:13]};
texel_out_r[31:24] = 8'hff;
end
`TEX_FORMAT_R4G4B4A4: begin
texel_out_r[07:00] = {texel_in[11:8], texel_in[15:12]};
`TEX_FORMAT_A1R5G5B5: begin
texel_out_r[07:00] = {texel_in[4:0], texel_in[4:2]};
texel_out_r[15:08] = {texel_in[9:5], texel_in[9:7]};
texel_out_r[23:16] = {texel_in[14:10], texel_in[14:12]};
texel_out_r[31:24] = {8{texel_in[15]}};
end
`TEX_FORMAT_A4R4G4B4: begin
texel_out_r[07:00] = {2{texel_in[3:0]}};
texel_out_r[15:08] = {2{texel_in[7:4]}};
texel_out_r[23:16] = {2{texel_in[3:0]}};
texel_out_r[23:16] = {2{texel_in[11:8]}};
texel_out_r[31:24] = {2{texel_in[15:12]}};
end
`TEX_FORMAT_L8A8: begin
`TEX_FORMAT_A8L8: begin
texel_out_r[07:00] = texel_in[7:0];
texel_out_r[15:08] = texel_in[7:0];
texel_out_r[23:16] = texel_in[7:0];
@@ -45,9 +51,9 @@ module VX_tex_format #(
end
//`TEX_FORMAT_A8
default: begin
texel_out_r[07:00] = 0;
texel_out_r[15:08] = 0;
texel_out_r[23:16] = 0;
texel_out_r[07:00] = 8'hff;
texel_out_r[15:08] = 8'hff;
texel_out_r[23:16] = 8'hff;
texel_out_r[31:24] = texel_in[7:0];
end
endcase

15
hw/rtl/tex_unit/VX_tex_stride.sv
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@@ -12,13 +12,14 @@ module VX_tex_stride #(
always @(*) begin
case (format)
`TEX_FORMAT_A8: log_stride_r = 0;
`TEX_FORMAT_L8: log_stride_r = 0;
`TEX_FORMAT_L8A8: log_stride_r = 1;
`TEX_FORMAT_R5G6B5: log_stride_r = 1;
`TEX_FORMAT_R4G4B4A4: log_stride_r = 1;
//`TEX_FORMAT_R8G8B8A8
default: log_stride_r = 2;
`TEX_FORMAT_A8R8G8B8: log_stride_r = 2;
`TEX_FORMAT_R5G6B5,
`TEX_FORMAT_A1R5G5B5,
`TEX_FORMAT_A4R4G4B4,
`TEX_FORMAT_A8L8: log_stride_r = 1;
// `TEX_FORMAT_L8:
// `TEX_FORMAT_A8:
default: log_stride_r = 0;
endcase
end

3
hw/syn/quartus/core/Makefile
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@@ -2,6 +2,7 @@ PROJECT = Core
TOP_LEVEL_ENTITY = VX_core
SRC_FILE = VX_core.v
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/fpu_core/Makefile
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@@ -2,6 +2,7 @@ PROJECT = VX_fpu_fpga
TOP_LEVEL_ENTITY = VX_fpu_fpga
SRC_FILE = VX_fpu_fpga.v
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
RTL_INCLUDE = $(FPU_INCLUDE);$(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf

3
hw/syn/quartus/pipeline/Makefile
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@@ -2,6 +2,7 @@ PROJECT = VX_pipeline
TOP_LEVEL_ENTITY = VX_pipeline
SRC_FILE = VX_pipeline.v
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top1/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top16/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top2/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top32/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top4/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

5
hw/syn/quartus/top64/Makefile
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@@ -1,7 +1,8 @@
PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR=../../../../rtl
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
#FAMILY = "Arria 10"
#DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
FPU_CORE_PATH=$(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/top8/Makefile
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@@ -2,6 +2,7 @@ PROJECT = vortex_afu
TOP_LEVEL_ENTITY = vortex_afu
SRC_FILE = vortex_afu.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(RTL_DIR)/afu;$(RTL_DIR)/afu/ccip;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/unittest/Makefile
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@@ -2,6 +2,7 @@ PROJECT = Unittest
TOP_LEVEL_ENTITY = VX_core_req_bank_sel
SRC_FILE = VX_core_req_bank_sel.v
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)

3
hw/syn/quartus/vortex/Makefile
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@@ -2,6 +2,7 @@ PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex
SRC_FILE = Vortex.sv
RTL_DIR = ../../../../rtl
THIRD_PARTY_DIR = ../../../../../third_party
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
@@ -11,7 +12,7 @@ FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/arria10
#DEVICE = 1SX280HN2F43E2VG
#FPU_CORE_PATH = $(RTL_DIR)/fp_cores/altera/stratix10
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(RTL_DIR)/fp_cores/fpnew/src;$(RTL_DIR)/fp_cores/fpnew/src/fpu_div_sqrt_mvp/hdl;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/include;$(RTL_DIR)/fp_cores/fpnew/src/common_cells/src
FPU_INCLUDE = $(RTL_DIR)/fp_cores;$(FPU_CORE_PATH);$(THIRD_PARTY_DIR)/fpnew/src;$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include;$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = $(RTL_DIR)/tex_unit
RTL_INCLUDE = $(RTL_DIR);$(RTL_DIR)/libs;$(RTL_DIR)/interfaces;$(RTL_DIR)/cache;$(FPU_INCLUDE);$(TEX_INCLUDE)