From bd70afa6883e1e5427ea3755681ee78357003eef Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sun, 14 Nov 2021 04:44:25 -0500 Subject: [PATCH] cache multi-porting fix - ensure per-bank uniform rw --- hw/rtl/cache/VX_cache_define.vh | 9 ++++----- hw/rtl/cache/VX_core_req_bank_sel.sv | 11 +++++++---- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/hw/rtl/cache/VX_cache_define.vh b/hw/rtl/cache/VX_cache_define.vh index c0709cce..8af2921b 100644 --- a/hw/rtl/cache/VX_cache_define.vh +++ b/hw/rtl/cache/VX_cache_define.vh @@ -24,7 +24,7 @@ `define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE)) `define MEM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE)) -`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`BANK_SELECT_BITS) +`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS)) // Word select `define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE) @@ -46,10 +46,9 @@ `define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END) `define TAG_SELECT_ADDR_END (`WORD_ADDR_WIDTH-1) -`define BANK_SELECT_ADDR(x) x[`BANK_SELECT_ADDR_END : `BANK_SELECT_ADDR_START] - -`define LINE_SELECT_ADDR0(x) x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START] -`define LINE_SELECT_ADDRX(x) {x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START], x[`BANK_SELECT_ADDR_START-1 : 1+`WORD_SELECT_ADDR_END]} +`define SELECT_BANK_ID(x) x[`BANK_SELECT_ADDR_END : `BANK_SELECT_ADDR_START] +`define SELECT_LINE_ADDR0(x) x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START] +`define SELECT_LINE_ADDRX(x) {x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START], x[`BANK_SELECT_ADDR_START-1 : 1+`WORD_SELECT_ADDR_END]} `define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SELECT_BITS] diff --git a/hw/rtl/cache/VX_core_req_bank_sel.sv b/hw/rtl/cache/VX_core_req_bank_sel.sv index 01c9f12b..1197edfb 100644 --- a/hw/rtl/cache/VX_core_req_bank_sel.sv +++ b/hw/rtl/cache/VX_core_req_bank_sel.sv @@ -57,16 +57,16 @@ module VX_core_req_bank_sel #( for (genvar i = 0; i < NUM_REQS; i++) begin if (BANK_ADDR_OFFSET == 0) begin - assign core_req_line_addr[i] = `LINE_SELECT_ADDR0(core_req_addr[i]); + assign core_req_line_addr[i] = `SELECT_LINE_ADDR0(core_req_addr[i]); end else begin - assign core_req_line_addr[i] = `LINE_SELECT_ADDRX(core_req_addr[i]); + assign core_req_line_addr[i] = `SELECT_LINE_ADDRX(core_req_addr[i]); end assign core_req_wsel[i] = core_req_addr[i][`UP(`WORD_SELECT_BITS)-1:0]; end for (genvar i = 0; i < NUM_REQS; ++i) begin if (NUM_BANKS > 1) begin - assign core_req_bid[i] = `BANK_SELECT_ADDR(core_req_addr[i]); + assign core_req_bid[i] = `SELECT_BANK_ID(core_req_addr[i]); end else begin assign core_req_bid[i] = 0; end @@ -88,6 +88,7 @@ module VX_core_req_bank_sel #( if (NUM_PORTS > 1) begin reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_line_addr_r; + reg [NUM_BANKS-1:0] per_bank_rw_r; wire [NUM_REQS-1:0] core_req_line_match; always @(*) begin @@ -95,12 +96,14 @@ module VX_core_req_bank_sel #( for (integer i = NUM_REQS-1; i >= 0; --i) begin if (core_req_valid[i]) begin per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i]; + per_bank_rw_r[core_req_bid[i]] = core_req_rw[i]; end end end for (genvar i = 0; i < NUM_REQS; ++i) begin - assign core_req_line_match[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]]); + assign core_req_line_match[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]]) + && (core_req_rw[i] == per_bank_rw_r[core_req_bid[i]]); end if (NUM_PORTS < NUM_REQS) begin