From bc6b2969ef4201f9d91331eb2577275acbb8abfa Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Apr 2020 15:41:12 -0700 Subject: [PATCH 1/3] minor opae hw fixed --- driver/hw/vortex_afu.sv | 22 ++++++++-------- driver/hw/wave.do | 50 +++++++++++++++++++++++++++++++++++++ driver/tests/basic/Makefile | 2 +- 3 files changed, 62 insertions(+), 12 deletions(-) create mode 100644 driver/hw/wave.do diff --git a/driver/hw/vortex_afu.sv b/driver/hw/vortex_afu.sv index d34dac2a..c65afe45 100644 --- a/driver/hw/vortex_afu.sv +++ b/driver/hw/vortex_afu.sv @@ -281,7 +281,6 @@ begin avs_writedata <= 0; avs_read <= 0; avs_write <= 0; - avs_read_ctr <= 0; avs_write_ctr <= 0; end @@ -323,9 +322,7 @@ begin STATE_RUN: begin if (vx_dram_req_read - && !avs_waitrequest - && !avs_raq_full - && !avs_rdq_full) + && !vx_dram_req_delay) begin avs_address <= (vx_dram_req_addr >> 6); avs_read <= 1; @@ -333,7 +330,7 @@ begin end if (vx_dram_req_write - && !avs_waitrequest) + && !vx_dram_req_delay) begin avs_writedata <= {>>{vx_dram_req_data}}; avs_address <= (vx_dram_req_addr >> 6); @@ -351,7 +348,10 @@ begin end // Vortex DRAM requests stalling -assign vx_dram_req_delay = !(avs_read || avs_write); +assign vx_dram_req_delay = !((STATE_RUN == state) + && !avs_waitrequest + && !avs_raq_full + && !avs_rdq_full); // Vortex DRAM fill response always_comb @@ -369,7 +369,7 @@ always_comb begin avs_raq_pop = vx_dram_fill_rsp || cci_write_req; avs_raq_din = avs_address; - avs_raq_push = avs_write; + avs_raq_push = avs_read; end VX_generic_queue_ll #( @@ -463,10 +463,10 @@ logic cci_write_pending; always_comb begin cci_write_req = (STATE_READ == state) - && !avs_rdq_empty - && !cp2af_sRxPort.c1TxAlmFull - && !cci_write_pending - && cci_write_ctr < csr_data_size; + && !avs_rdq_empty + && !cp2af_sRxPort.c1TxAlmFull + && !cci_write_pending + && cci_write_ctr < csr_data_size; wr_hdr = t_ccip_c1_ReqMemHdr'(0); wr_hdr.address = csr_io_addr + cci_write_ctr; diff --git a/driver/hw/wave.do b/driver/hw/wave.do new file mode 100644 index 00000000..4078ad38 --- /dev/null +++ b/driver/hw/wave.do @@ -0,0 +1,50 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -label clk /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/clk +add wave -noupdate -label reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/SoftReset +add wave -noupdate -label state /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/state +add wave -noupdate -label cci_write_pending /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_pending +add wave -noupdate -label cci_write_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_ctr +add wave -noupdate -label csr_data_size -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/csr_data_size +add wave -noupdate -label avs_read_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read_ctr +add wave -noupdate -label avs_waitrequest /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_waitrequest +add wave -noupdate -label avs_address -radix hexadecimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_address +add wave -noupdate -label avs_readdata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdata +add wave -noupdate -label avs_writedata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_writedata +add wave -noupdate -label avs_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_write +add wave -noupdate -label avs_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read +add wave -noupdate -label avs_readdatavalid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdatavalid +add wave -noupdate -label sRx.c0.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c0.rspValid +add wave -noupdate -label sRx.c1.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c1.rspValid +add wave -noupdate -label sTx.c0.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c0.valid +add wave -noupdate -label sTx.c1.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c1.valid +add wave -noupdate -label cci_write_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_req +add wave -noupdate -label avs_raq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_push +add wave -noupdate -label avs_rdq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_push +add wave -noupdate -label avs_raq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_pop +add wave -noupdate -label avs_rdq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_pop +add wave -noupdate -label avs_raq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_full +add wave -noupdate -label avs_rdq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_full +add wave -noupdate -label avs_raq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_empty +add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_empty +add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write +add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay +add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 2} {77894400 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 195 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {77712056 ps} {78076744 ps} diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index f29b8e64..d04e756f 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -18,7 +18,7 @@ run-fpga: $(PROJECT) LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT) run-ase: $(PROJECT) - ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) + ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -t 1 run-rtlsim: $(PROJECT) LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT) From f590d6acc8228fd1c6531166dbc9991bb8696500 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Apr 2020 20:09:08 -0700 Subject: [PATCH 2/3] minor update --- driver/hw/vortex_afu.sv | 4 ++-- driver/hw/wave.do | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/driver/hw/vortex_afu.sv b/driver/hw/vortex_afu.sv index c65afe45..c24dab2f 100644 --- a/driver/hw/vortex_afu.sv +++ b/driver/hw/vortex_afu.sv @@ -342,7 +342,7 @@ begin if (avs_readdatavalid) begin - $display("%t: AVS Rd Rsp: value=%h", $time, avs_readdata[63:0]); + $display("%t: AVS Rd Rsp", $time); end end end @@ -357,7 +357,7 @@ assign vx_dram_req_delay = !((STATE_RUN == state) always_comb begin vx_dram_fill_rsp = (STATE_RUN == state) && !avs_rdq_empty && vx_dram_fill_accept; - vx_dram_fill_rsp_addr = avs_raq_dout; + vx_dram_fill_rsp_addr = (avs_raq_dout << 6); {>>{vx_dram_fill_rsp_data}} = avs_rdq_dout; end diff --git a/driver/hw/wave.do b/driver/hw/wave.do index 4078ad38..58548f72 100644 --- a/driver/hw/wave.do +++ b/driver/hw/wave.do @@ -30,8 +30,22 @@ add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_c add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read +add wave -noupdate -label vx_reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/reset +add wave -noupdate -label out_dram_fill_rsp /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_rsp +add wave -noupdate -label out_dram_fill_accept /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_accept +add wave -noupdate -label llc_snp_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req +add wave -noupdate -label llc_snp_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req_delay +add wave -noupdate -label out_break /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_ebreak +add wave -noupdate -label warp_pc -radix hexadecimal -radixshowbase 0 {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_pc} +add wave -noupdate -label scheduled_warp {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/scheduled_warp} +add wave -noupdate -label thread_mask {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/thread_mask} +add wave -noupdate -label warp_num {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_num} +add wave -noupdate -label warp_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_active} +add wave -noupdate -label warp_stalled {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_stalled} +add wave -noupdate -label warp_lock {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_lock} +add wave -noupdate -label use_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/use_active} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {77894400 ps} 0} +WaveRestoreCursors {{Cursor 2} {66234495 ps} 0} quietly wave cursor active 1 configure wave -namecolwidth 195 configure wave -valuecolwidth 100 @@ -47,4 +61,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {77712056 ps} {78076744 ps} +WaveRestoreZoom {66041656 ps} {66406344 ps} From 7d1cc5234e173bcdaef3c71c0c7d883c95ce01c8 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Thu, 2 Apr 2020 20:26:37 -0700 Subject: [PATCH 3/3] Fixed dram_fill_accept dependant on input address --- rtl/VX_cache/VX_cache.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rtl/VX_cache/VX_cache.v b/rtl/VX_cache/VX_cache.v index 6d206b0f..4b9630b2 100644 --- a/rtl/VX_cache/VX_cache.v +++ b/rtl/VX_cache/VX_cache.v @@ -147,7 +147,8 @@ module VX_cache assign snp_req_delay = (|per_bank_snrq_full); - assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + // assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]]; + assign dram_fill_accept = (|per_bank_dram_fill_accept); VX_cache_dram_req_arb #( .CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),